diff options
Diffstat (limited to 'arch/arm/mach-versatile')
-rw-r--r-- | arch/arm/mach-versatile/core.c | 58 |
1 files changed, 5 insertions, 53 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 90023745b23a..9ebbe808b41d 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <asm/leds.h> | 35 | #include <asm/leds.h> |
36 | #include <asm/hardware/arm_timer.h> | 36 | #include <asm/hardware/arm_timer.h> |
37 | #include <asm/hardware/icst307.h> | 37 | #include <asm/hardware/icst307.h> |
38 | #include <asm/hardware/vic.h> | ||
38 | 39 | ||
39 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
40 | #include <asm/mach/flash.h> | 41 | #include <asm/mach/flash.h> |
@@ -56,24 +57,6 @@ | |||
56 | #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) | 57 | #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) |
57 | #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) | 58 | #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) |
58 | 59 | ||
59 | static void vic_mask_irq(unsigned int irq) | ||
60 | { | ||
61 | irq -= IRQ_VIC_START; | ||
62 | writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR); | ||
63 | } | ||
64 | |||
65 | static void vic_unmask_irq(unsigned int irq) | ||
66 | { | ||
67 | irq -= IRQ_VIC_START; | ||
68 | writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE); | ||
69 | } | ||
70 | |||
71 | static struct irqchip vic_chip = { | ||
72 | .ack = vic_mask_irq, | ||
73 | .mask = vic_mask_irq, | ||
74 | .unmask = vic_unmask_irq, | ||
75 | }; | ||
76 | |||
77 | static void sic_mask_irq(unsigned int irq) | 60 | static void sic_mask_irq(unsigned int irq) |
78 | { | 61 | { |
79 | irq -= IRQ_SIC_START; | 62 | irq -= IRQ_SIC_START; |
@@ -127,43 +110,12 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs) | |||
127 | 110 | ||
128 | void __init versatile_init_irq(void) | 111 | void __init versatile_init_irq(void) |
129 | { | 112 | { |
130 | unsigned int i, value; | 113 | unsigned int i; |
131 | |||
132 | /* Disable all interrupts initially. */ | ||
133 | 114 | ||
134 | writel(0, VA_VIC_BASE + VIC_INT_SELECT); | 115 | vic_init(VA_VIC_BASE, ~(1 << 31)); |
135 | writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE); | ||
136 | writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR); | ||
137 | writel(0, VA_VIC_BASE + VIC_IRQ_STATUS); | ||
138 | writel(0, VA_VIC_BASE + VIC_ITCR); | ||
139 | writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR); | ||
140 | |||
141 | /* | ||
142 | * Make sure we clear all existing interrupts | ||
143 | */ | ||
144 | writel(0, VA_VIC_BASE + VIC_VECT_ADDR); | ||
145 | for (i = 0; i < 19; i++) { | ||
146 | value = readl(VA_VIC_BASE + VIC_VECT_ADDR); | ||
147 | writel(value, VA_VIC_BASE + VIC_VECT_ADDR); | ||
148 | } | ||
149 | |||
150 | for (i = 0; i < 16; i++) { | ||
151 | value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4)); | ||
152 | writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4)); | ||
153 | } | ||
154 | |||
155 | writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR); | ||
156 | |||
157 | for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) { | ||
158 | if (i != IRQ_VICSOURCE31) { | ||
159 | set_irq_chip(i, &vic_chip); | ||
160 | set_irq_handler(i, do_level_IRQ); | ||
161 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | ||
162 | } | ||
163 | } | ||
164 | 116 | ||
165 | set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); | 117 | set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq); |
166 | vic_unmask_irq(IRQ_VICSOURCE31); | 118 | enable_irq(IRQ_VICSOURCE31); |
167 | 119 | ||
168 | /* Do second interrupt controller */ | 120 | /* Do second interrupt controller */ |
169 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); | 121 | writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); |
@@ -877,7 +829,7 @@ static unsigned long versatile_gettimeoffset(void) | |||
877 | ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; | 829 | ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; |
878 | do { | 830 | do { |
879 | ticks1 = ticks2; | 831 | ticks1 = ticks2; |
880 | status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS); | 832 | status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS); |
881 | ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; | 833 | ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff; |
882 | } while (ticks2 > ticks1); | 834 | } while (ticks2 > ticks1); |
883 | 835 | ||