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-rw-r--r--arch/arm/mach-versatile/core.c18
-rw-r--r--arch/arm/mach-versatile/core.h1
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c5
3 files changed, 0 insertions, 24 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 606e046905e3..630a1c96f90b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -634,53 +634,35 @@ static struct pl022_ssp_controller ssp0_plat_data = {
634}; 634};
635 635
636#define AACI_IRQ { IRQ_AACI, NO_IRQ } 636#define AACI_IRQ { IRQ_AACI, NO_IRQ }
637#define AACI_DMA { 0x80, 0x81 }
638#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } 637#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
639#define MMCI0_DMA { 0x84, 0 }
640#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } 638#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
641#define KMI0_DMA { 0, 0 }
642#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } 639#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
643#define KMI1_DMA { 0, 0 }
644 640
645/* 641/*
646 * These devices are connected directly to the multi-layer AHB switch 642 * These devices are connected directly to the multi-layer AHB switch
647 */ 643 */
648#define SMC_IRQ { NO_IRQ, NO_IRQ } 644#define SMC_IRQ { NO_IRQ, NO_IRQ }
649#define SMC_DMA { 0, 0 }
650#define MPMC_IRQ { NO_IRQ, NO_IRQ } 645#define MPMC_IRQ { NO_IRQ, NO_IRQ }
651#define MPMC_DMA { 0, 0 }
652#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } 646#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
653#define CLCD_DMA { 0, 0 }
654#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } 647#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
655#define DMAC_DMA { 0, 0 }
656 648
657/* 649/*
658 * These devices are connected via the core APB bridge 650 * These devices are connected via the core APB bridge
659 */ 651 */
660#define SCTL_IRQ { NO_IRQ, NO_IRQ } 652#define SCTL_IRQ { NO_IRQ, NO_IRQ }
661#define SCTL_DMA { 0, 0 }
662#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } 653#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
663#define WATCHDOG_DMA { 0, 0 }
664#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } 654#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
665#define GPIO0_DMA { 0, 0 }
666#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } 655#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
667#define GPIO1_DMA { 0, 0 }
668#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } 656#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
669#define RTC_DMA { 0, 0 }
670 657
671/* 658/*
672 * These devices are connected via the DMA APB bridge 659 * These devices are connected via the DMA APB bridge
673 */ 660 */
674#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } 661#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
675#define SCI_DMA { 7, 6 }
676#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } 662#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
677#define UART0_DMA { 15, 14 }
678#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } 663#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
679#define UART1_DMA { 13, 12 }
680#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } 664#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
681#define UART2_DMA { 11, 10 }
682#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } 665#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
683#define SSP_DMA { 9, 8 }
684 666
685/* FPGA Primecells */ 667/* FPGA Primecells */
686AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 668AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index e04768a6c5dc..fd6404e5d788 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -45,7 +45,6 @@ static struct amba_device name##_device = { \
45 }, \ 45 }, \
46 .dma_mask = ~0, \ 46 .dma_mask = ~0, \
47 .irq = base##_IRQ, \ 47 .irq = base##_IRQ, \
48 /* .dma = base##_DMA,*/ \
49} 48}
50 49
51#endif 50#endif
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 97fb30691c47..37c23dfeefb7 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -59,19 +59,14 @@ static struct pl061_platform_data gpio3_plat_data = {
59}; 59};
60 60
61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } 61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ }
62#define UART3_DMA { 0x86, 0x87 }
63#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ } 62#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ }
64#define SCI1_DMA { 0x88, 0x89 }
65#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } 63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
66#define MMCI1_DMA { 0x85, 0 }
67 64
68/* 65/*
69 * These devices are connected via the core APB bridge 66 * These devices are connected via the core APB bridge
70 */ 67 */
71#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } 68#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
72#define GPIO2_DMA { 0, 0 }
73#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } 69#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
74#define GPIO3_DMA { 0, 0 }
75 70
76/* 71/*
77 * These devices are connected via the DMA APB bridge 72 * These devices are connected via the DMA APB bridge