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-rw-r--r--arch/arm/mach-versatile/Kconfig11
-rw-r--r--arch/arm/mach-versatile/core.c292
-rw-r--r--arch/arm/mach-versatile/core.h2
-rw-r--r--arch/arm/mach-versatile/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-versatile/include/mach/memory.h2
-rw-r--r--arch/arm/mach-versatile/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-versatile/versatile_ab.c1
-rw-r--r--arch/arm/mach-versatile/versatile_pb.c6
8 files changed, 81 insertions, 237 deletions
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index c781f30c8368..9cdec5aa04a0 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -2,16 +2,19 @@ menu "Versatile platform type"
2 depends on ARCH_VERSATILE 2 depends on ARCH_VERSATILE
3 3
4config ARCH_VERSATILE_PB 4config ARCH_VERSATILE_PB
5 bool "Support Versatile/PB platform" 5 bool "Support Versatile Platform Baseboard for ARM926EJ-S"
6 select CPU_ARM926T 6 select CPU_ARM926T
7 select MIGHT_HAVE_PCI
7 default y 8 default y
8 help 9 help
9 Include support for the ARM(R) Versatile/PB platform. 10 Include support for the ARM(R) Versatile Platform Baseboard
11 for the ARM926EJ-S.
10 12
11config MACH_VERSATILE_AB 13config MACH_VERSATILE_AB
12 bool "Support Versatile/AB platform" 14 bool "Support Versatile Application Baseboard for ARM926EJ-S"
13 select CPU_ARM926T 15 select CPU_ARM926T
14 help 16 help
15 Include support for the ARM(R) Versatile/AP platform. 17 Include support for the ARM(R) Versatile Application Baseboard
18 for the ARM926EJ-S.
16 19
17endmenu 20endmenu
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e38acb0f89c8..eb7ffa0ee8b5 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -31,8 +31,8 @@
31#include <linux/amba/pl022.h> 31#include <linux/amba/pl022.h>
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/gfp.h> 33#include <linux/gfp.h>
34#include <linux/clkdev.h>
34 35
35#include <asm/clkdev.h>
36#include <asm/system.h> 36#include <asm/system.h>
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/leds.h> 38#include <asm/leds.h>
@@ -46,10 +46,13 @@
46#include <asm/mach/irq.h> 46#include <asm/mach/irq.h>
47#include <asm/mach/time.h> 47#include <asm/mach/time.h>
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49#include <mach/clkdev.h>
50#include <mach/hardware.h> 49#include <mach/hardware.h>
51#include <mach/platform.h> 50#include <mach/platform.h>
52#include <plat/timer-sp.h> 51#include <asm/hardware/timer-sp.h>
52
53#include <plat/clcd.h>
54#include <plat/fpga-irq.h>
55#include <plat/sched_clock.h>
53 56
54#include "core.h" 57#include "core.h"
55 58
@@ -62,45 +65,12 @@
62#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE) 65#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
63#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE) 66#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
64 67
65static void sic_mask_irq(unsigned int irq) 68static struct fpga_irq_data sic_irq = {
66{ 69 .base = VA_SIC_BASE,
67 irq -= IRQ_SIC_START; 70 .irq_start = IRQ_SIC_START,
68 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 71 .chip.name = "SIC",
69}
70
71static void sic_unmask_irq(unsigned int irq)
72{
73 irq -= IRQ_SIC_START;
74 writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
75}
76
77static struct irq_chip sic_chip = {
78 .name = "SIC",
79 .ack = sic_mask_irq,
80 .mask = sic_mask_irq,
81 .unmask = sic_unmask_irq,
82}; 72};
83 73
84static void
85sic_handle_irq(unsigned int irq, struct irq_desc *desc)
86{
87 unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
88
89 if (status == 0) {
90 do_bad_IRQ(irq, desc);
91 return;
92 }
93
94 do {
95 irq = ffs(status) - 1;
96 status &= ~(1 << irq);
97
98 irq += IRQ_SIC_START;
99
100 generic_handle_irq(irq);
101 } while (status);
102}
103
104#if 1 74#if 1
105#define IRQ_MMCI0A IRQ_VICSOURCE22 75#define IRQ_MMCI0A IRQ_VICSOURCE22
106#define IRQ_AACI IRQ_VICSOURCE24 76#define IRQ_AACI IRQ_VICSOURCE24
@@ -115,22 +85,11 @@ sic_handle_irq(unsigned int irq, struct irq_desc *desc)
115 85
116void __init versatile_init_irq(void) 86void __init versatile_init_irq(void)
117{ 87{
118 unsigned int i;
119
120 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0); 88 vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
121 89
122 set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
123
124 /* Do second interrupt controller */
125 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); 90 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
126 91
127 for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { 92 fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
128 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
129 set_irq_chip(i, &sic_chip);
130 set_irq_handler(i, handle_level_irq);
131 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
132 }
133 }
134 93
135 /* 94 /*
136 * Interrupts on secondary controller from 0 to 8 are routed to 95 * Interrupts on secondary controller from 0 to 8 are routed to
@@ -473,127 +432,7 @@ static struct clk_lookup lookups[] = {
473#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8) 432#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
474#define SYS_CLCD_ID_VGA (0x1f << 8) 433#define SYS_CLCD_ID_VGA (0x1f << 8)
475 434
476static struct clcd_panel vga = { 435static bool is_sanyo_2_5_lcd;
477 .mode = {
478 .name = "VGA",
479 .refresh = 60,
480 .xres = 640,
481 .yres = 480,
482 .pixclock = 39721,
483 .left_margin = 40,
484 .right_margin = 24,
485 .upper_margin = 32,
486 .lower_margin = 11,
487 .hsync_len = 96,
488 .vsync_len = 2,
489 .sync = 0,
490 .vmode = FB_VMODE_NONINTERLACED,
491 },
492 .width = -1,
493 .height = -1,
494 .tim2 = TIM2_BCD | TIM2_IPC,
495 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
496 .bpp = 16,
497};
498
499static struct clcd_panel sanyo_3_8_in = {
500 .mode = {
501 .name = "Sanyo QVGA",
502 .refresh = 116,
503 .xres = 320,
504 .yres = 240,
505 .pixclock = 100000,
506 .left_margin = 6,
507 .right_margin = 6,
508 .upper_margin = 5,
509 .lower_margin = 5,
510 .hsync_len = 6,
511 .vsync_len = 6,
512 .sync = 0,
513 .vmode = FB_VMODE_NONINTERLACED,
514 },
515 .width = -1,
516 .height = -1,
517 .tim2 = TIM2_BCD,
518 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
519 .bpp = 16,
520};
521
522static struct clcd_panel sanyo_2_5_in = {
523 .mode = {
524 .name = "Sanyo QVGA Portrait",
525 .refresh = 116,
526 .xres = 240,
527 .yres = 320,
528 .pixclock = 100000,
529 .left_margin = 20,
530 .right_margin = 10,
531 .upper_margin = 2,
532 .lower_margin = 2,
533 .hsync_len = 10,
534 .vsync_len = 2,
535 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
536 .vmode = FB_VMODE_NONINTERLACED,
537 },
538 .width = -1,
539 .height = -1,
540 .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
541 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
542 .bpp = 16,
543};
544
545static struct clcd_panel epson_2_2_in = {
546 .mode = {
547 .name = "Epson QCIF",
548 .refresh = 390,
549 .xres = 176,
550 .yres = 220,
551 .pixclock = 62500,
552 .left_margin = 3,
553 .right_margin = 2,
554 .upper_margin = 1,
555 .lower_margin = 0,
556 .hsync_len = 3,
557 .vsync_len = 2,
558 .sync = 0,
559 .vmode = FB_VMODE_NONINTERLACED,
560 },
561 .width = -1,
562 .height = -1,
563 .tim2 = TIM2_BCD | TIM2_IPC,
564 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
565 .bpp = 16,
566};
567
568/*
569 * Detect which LCD panel is connected, and return the appropriate
570 * clcd_panel structure. Note: we do not have any information on
571 * the required timings for the 8.4in panel, so we presently assume
572 * VGA timings.
573 */
574static struct clcd_panel *versatile_clcd_panel(void)
575{
576 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
577 struct clcd_panel *panel = &vga;
578 u32 val;
579
580 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
581 if (val == SYS_CLCD_ID_SANYO_3_8)
582 panel = &sanyo_3_8_in;
583 else if (val == SYS_CLCD_ID_SANYO_2_5)
584 panel = &sanyo_2_5_in;
585 else if (val == SYS_CLCD_ID_EPSON_2_2)
586 panel = &epson_2_2_in;
587 else if (val == SYS_CLCD_ID_VGA)
588 panel = &vga;
589 else {
590 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
591 val);
592 panel = &vga;
593 }
594
595 return panel;
596}
597 436
598/* 437/*
599 * Disable all display connectors on the interface module. 438 * Disable all display connectors on the interface module.
@@ -611,7 +450,7 @@ static void versatile_clcd_disable(struct clcd_fb *fb)
611 /* 450 /*
612 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off 451 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
613 */ 452 */
614 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { 453 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
615 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); 454 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
616 unsigned long ctrl; 455 unsigned long ctrl;
617 456
@@ -627,18 +466,22 @@ static void versatile_clcd_disable(struct clcd_fb *fb)
627 */ 466 */
628static void versatile_clcd_enable(struct clcd_fb *fb) 467static void versatile_clcd_enable(struct clcd_fb *fb)
629{ 468{
469 struct fb_var_screeninfo *var = &fb->fb.var;
630 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET; 470 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
631 u32 val; 471 u32 val;
632 472
633 val = readl(sys_clcd); 473 val = readl(sys_clcd);
634 val &= ~SYS_CLCD_MODE_MASK; 474 val &= ~SYS_CLCD_MODE_MASK;
635 475
636 switch (fb->fb.var.green.length) { 476 switch (var->green.length) {
637 case 5: 477 case 5:
638 val |= SYS_CLCD_MODE_5551; 478 val |= SYS_CLCD_MODE_5551;
639 break; 479 break;
640 case 6: 480 case 6:
641 val |= SYS_CLCD_MODE_565_RLSB; 481 if (var->red.offset == 0)
482 val |= SYS_CLCD_MODE_565_RLSB;
483 else
484 val |= SYS_CLCD_MODE_565_BLSB;
642 break; 485 break;
643 case 8: 486 case 8:
644 val |= SYS_CLCD_MODE_888; 487 val |= SYS_CLCD_MODE_888;
@@ -660,7 +503,7 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
660 /* 503 /*
661 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on 504 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
662 */ 505 */
663 if (machine_is_versatile_ab() && fb->panel == &sanyo_2_5_in) { 506 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
664 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL); 507 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
665 unsigned long ctrl; 508 unsigned long ctrl;
666 509
@@ -671,50 +514,62 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
671#endif 514#endif
672} 515}
673 516
674static unsigned long framesize = SZ_1M; 517/*
675 518 * Detect which LCD panel is connected, and return the appropriate
519 * clcd_panel structure. Note: we do not have any information on
520 * the required timings for the 8.4in panel, so we presently assume
521 * VGA timings.
522 */
676static int versatile_clcd_setup(struct clcd_fb *fb) 523static int versatile_clcd_setup(struct clcd_fb *fb)
677{ 524{
678 dma_addr_t dma; 525 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
526 const char *panel_name;
527 u32 val;
679 528
680 fb->panel = versatile_clcd_panel(); 529 is_sanyo_2_5_lcd = false;
681 530
682 fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, 531 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
683 &dma, GFP_KERNEL); 532 if (val == SYS_CLCD_ID_SANYO_3_8)
684 if (!fb->fb.screen_base) { 533 panel_name = "Sanyo TM38QV67A02A";
685 printk(KERN_ERR "CLCD: unable to map framebuffer\n"); 534 else if (val == SYS_CLCD_ID_SANYO_2_5) {
686 return -ENOMEM; 535 panel_name = "Sanyo QVGA Portrait";
536 is_sanyo_2_5_lcd = true;
537 } else if (val == SYS_CLCD_ID_EPSON_2_2)
538 panel_name = "Epson L2F50113T00";
539 else if (val == SYS_CLCD_ID_VGA)
540 panel_name = "VGA";
541 else {
542 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
543 val);
544 panel_name = "VGA";
687 } 545 }
688 546
689 fb->fb.fix.smem_start = dma; 547 fb->panel = versatile_clcd_get_panel(panel_name);
690 fb->fb.fix.smem_len = framesize; 548 if (!fb->panel)
549 return -EINVAL;
691 550
692 return 0; 551 return versatile_clcd_setup_dma(fb, SZ_1M);
693} 552}
694 553
695static int versatile_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) 554static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
696{ 555{
697 return dma_mmap_writecombine(&fb->dev->dev, vma, 556 clcdfb_decode(fb, regs);
698 fb->fb.screen_base,
699 fb->fb.fix.smem_start,
700 fb->fb.fix.smem_len);
701}
702 557
703static void versatile_clcd_remove(struct clcd_fb *fb) 558 /* Always clear BGR for RGB565: we do the routing externally */
704{ 559 if (fb->fb.var.green.length == 6)
705 dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, 560 regs->cntl &= ~CNTL_BGR;
706 fb->fb.screen_base, fb->fb.fix.smem_start);
707} 561}
708 562
709static struct clcd_board clcd_plat_data = { 563static struct clcd_board clcd_plat_data = {
710 .name = "Versatile", 564 .name = "Versatile",
565 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
711 .check = clcdfb_check, 566 .check = clcdfb_check,
712 .decode = clcdfb_decode, 567 .decode = versatile_clcd_decode,
713 .disable = versatile_clcd_disable, 568 .disable = versatile_clcd_disable,
714 .enable = versatile_clcd_enable, 569 .enable = versatile_clcd_enable,
715 .setup = versatile_clcd_setup, 570 .setup = versatile_clcd_setup,
716 .mmap = versatile_clcd_mmap, 571 .mmap = versatile_clcd_mmap_dma,
717 .remove = versatile_clcd_remove, 572 .remove = versatile_clcd_remove_dma,
718}; 573};
719 574
720static struct pl061_platform_data gpio0_plat_data = { 575static struct pl061_platform_data gpio0_plat_data = {
@@ -734,53 +589,35 @@ static struct pl022_ssp_controller ssp0_plat_data = {
734}; 589};
735 590
736#define AACI_IRQ { IRQ_AACI, NO_IRQ } 591#define AACI_IRQ { IRQ_AACI, NO_IRQ }
737#define AACI_DMA { 0x80, 0x81 }
738#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } 592#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
739#define MMCI0_DMA { 0x84, 0 }
740#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ } 593#define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
741#define KMI0_DMA { 0, 0 }
742#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ } 594#define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
743#define KMI1_DMA { 0, 0 }
744 595
745/* 596/*
746 * These devices are connected directly to the multi-layer AHB switch 597 * These devices are connected directly to the multi-layer AHB switch
747 */ 598 */
748#define SMC_IRQ { NO_IRQ, NO_IRQ } 599#define SMC_IRQ { NO_IRQ, NO_IRQ }
749#define SMC_DMA { 0, 0 }
750#define MPMC_IRQ { NO_IRQ, NO_IRQ } 600#define MPMC_IRQ { NO_IRQ, NO_IRQ }
751#define MPMC_DMA { 0, 0 }
752#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ } 601#define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
753#define CLCD_DMA { 0, 0 }
754#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ } 602#define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
755#define DMAC_DMA { 0, 0 }
756 603
757/* 604/*
758 * These devices are connected via the core APB bridge 605 * These devices are connected via the core APB bridge
759 */ 606 */
760#define SCTL_IRQ { NO_IRQ, NO_IRQ } 607#define SCTL_IRQ { NO_IRQ, NO_IRQ }
761#define SCTL_DMA { 0, 0 }
762#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ } 608#define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
763#define WATCHDOG_DMA { 0, 0 }
764#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ } 609#define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
765#define GPIO0_DMA { 0, 0 }
766#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ } 610#define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
767#define GPIO1_DMA { 0, 0 }
768#define RTC_IRQ { IRQ_RTCINT, NO_IRQ } 611#define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
769#define RTC_DMA { 0, 0 }
770 612
771/* 613/*
772 * These devices are connected via the DMA APB bridge 614 * These devices are connected via the DMA APB bridge
773 */ 615 */
774#define SCI_IRQ { IRQ_SCIINT, NO_IRQ } 616#define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
775#define SCI_DMA { 7, 6 }
776#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ } 617#define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
777#define UART0_DMA { 15, 14 }
778#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ } 618#define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
779#define UART1_DMA { 13, 12 }
780#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ } 619#define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
781#define UART2_DMA { 11, 10 }
782#define SSP_IRQ { IRQ_SSPINT, NO_IRQ } 620#define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
783#define SSP_DMA { 9, 8 }
784 621
785/* FPGA Primecells */ 622/* FPGA Primecells */
786AMBA_DEVICE(aaci, "fpga:04", AACI, NULL); 623AMBA_DEVICE(aaci, "fpga:04", AACI, NULL);
@@ -862,14 +699,21 @@ static void versatile_leds_event(led_event_t ledevt)
862} 699}
863#endif /* CONFIG_LEDS */ 700#endif /* CONFIG_LEDS */
864 701
865void __init versatile_init(void) 702/* Early initializations */
703void __init versatile_init_early(void)
866{ 704{
867 int i; 705 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
868
869 osc4_clk.vcoreg = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_OSCCLCD_OFFSET;
870 706
707 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
871 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 708 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
872 709
710 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
711}
712
713void __init versatile_init(void)
714{
715 int i;
716
873 platform_device_register(&versatile_flash_device); 717 platform_device_register(&versatile_flash_device);
874 platform_device_register(&versatile_i2c_device); 718 platform_device_register(&versatile_i2c_device);
875 platform_device_register(&smc91x_device); 719 platform_device_register(&smc91x_device);
diff --git a/arch/arm/mach-versatile/core.h b/arch/arm/mach-versatile/core.h
index 9d39886a8351..fd6404e5d788 100644
--- a/arch/arm/mach-versatile/core.h
+++ b/arch/arm/mach-versatile/core.h
@@ -25,6 +25,7 @@
25#include <linux/amba/bus.h> 25#include <linux/amba/bus.h>
26 26
27extern void __init versatile_init(void); 27extern void __init versatile_init(void);
28extern void __init versatile_init_early(void);
28extern void __init versatile_init_irq(void); 29extern void __init versatile_init_irq(void);
29extern void __init versatile_map_io(void); 30extern void __init versatile_map_io(void);
30extern struct sys_timer versatile_timer; 31extern struct sys_timer versatile_timer;
@@ -44,7 +45,6 @@ static struct amba_device name##_device = { \
44 }, \ 45 }, \
45 .dma_mask = ~0, \ 46 .dma_mask = ~0, \
46 .irq = base##_IRQ, \ 47 .irq = base##_IRQ, \
47 /* .dma = base##_DMA,*/ \
48} 48}
49 49
50#endif 50#endif
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index b5e75bb44965..6911e1f5f156 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -39,6 +39,6 @@
39/* macro to get at IO space when running virtually */ 39/* macro to get at IO space when running virtually */
40#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) 40#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
41 41
42#define __io_address(n) __io(IO_ADDRESS(n)) 42#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n))
43 43
44#endif 44#endif
diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h
index 79aeab86b903..dacc9d8e4e6a 100644
--- a/arch/arm/mach-versatile/include/mach/memory.h
+++ b/arch/arm/mach-versatile/include/mach/memory.h
@@ -23,6 +23,6 @@
23/* 23/*
24 * Physical DRAM offset. 24 * Physical DRAM offset.
25 */ 25 */
26#define PHYS_OFFSET UL(0x00000000) 26#define PLAT_PHYS_OFFSET UL(0x00000000)
27 27
28#endif 28#endif
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
index ebd8a2543d3b..7d8e069ad51b 100644
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#define VMALLOC_END 0xd8000000 21#define VMALLOC_END 0xd8000000UL
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index aa9730fb13bf..f8ae64b3eed0 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -37,6 +37,7 @@ MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
38 .boot_params = 0x00000100, 38 .boot_params = 0x00000100,
39 .map_io = versatile_map_io, 39 .map_io = versatile_map_io,
40 .init_early = versatile_init_early,
40 .init_irq = versatile_init_irq, 41 .init_irq = versatile_init_irq,
41 .timer = &versatile_timer, 42 .timer = &versatile_timer,
42 .init_machine = versatile_init, 43 .init_machine = versatile_init,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index bf469642a3f8..37c23dfeefb7 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -59,19 +59,14 @@ static struct pl061_platform_data gpio3_plat_data = {
59}; 59};
60 60
61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } 61#define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ }
62#define UART3_DMA { 0x86, 0x87 }
63#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ } 62#define SCI1_IRQ { IRQ_SIC_SCI3, NO_IRQ }
64#define SCI1_DMA { 0x88, 0x89 }
65#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B } 63#define MMCI1_IRQ { IRQ_MMCI1A, IRQ_SIC_MMCI1B }
66#define MMCI1_DMA { 0x85, 0 }
67 64
68/* 65/*
69 * These devices are connected via the core APB bridge 66 * These devices are connected via the core APB bridge
70 */ 67 */
71#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ } 68#define GPIO2_IRQ { IRQ_GPIOINT2, NO_IRQ }
72#define GPIO2_DMA { 0, 0 }
73#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ } 69#define GPIO3_IRQ { IRQ_GPIOINT3, NO_IRQ }
74#define GPIO3_DMA { 0, 0 }
75 70
76/* 71/*
77 * These devices are connected via the DMA APB bridge 72 * These devices are connected via the DMA APB bridge
@@ -110,6 +105,7 @@ MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
110 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 105 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
111 .boot_params = 0x00000100, 106 .boot_params = 0x00000100,
112 .map_io = versatile_map_io, 107 .map_io = versatile_map_io,
108 .init_early = versatile_init_early,
113 .init_irq = versatile_init_irq, 109 .init_irq = versatile_init_irq,
114 .timer = &versatile_timer, 110 .timer = &versatile_timer,
115 .init_machine = versatile_pb_init, 111 .init_machine = versatile_pb_init,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 00:08:54 -0500