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-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/Makefile4
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c (renamed from arch/arm/mach-ux500/board-mop500-msp.c)102
-rw-r--r--arch/arm/mach-ux500/board-mop500-msp.h14
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c4
-rw-r--r--arch/arm/mach-ux500/board-mop500.c39
-rw-r--r--arch/arm/mach-ux500/board-mop500.h11
-rw-r--r--arch/arm/mach-ux500/clock.c715
-rw-r--r--arch/arm/mach-ux500/clock.h164
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c10
-rw-r--r--arch/arm/mach-ux500/cpu.c14
-rw-r--r--arch/arm/mach-ux500/include/mach/msp.h2
12 files changed, 59 insertions, 1021 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 53d3d46dec12..a258996d954b 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -11,6 +11,7 @@ config UX500_SOC_COMMON
11 select CACHE_L2X0 11 select CACHE_L2X0
12 select PINCTRL 12 select PINCTRL
13 select PINCTRL_NOMADIK 13 select PINCTRL_NOMADIK
14 select COMMON_CLK
14 15
15config UX500_SOC_DB8500 16config UX500_SOC_DB8500
16 bool 17 bool
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 026086ff9e6c..f24710dfc395 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U8500 machine. 2# Makefile for the linux kernel, U8500 machine.
3# 3#
4 4
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := cpu.o devices.o devices-common.o \
6 id.o usb.o timer.o 6 id.o usb.o timer.o
7obj-$(CONFIG_CPU_IDLE) += cpuidle.o 7obj-$(CONFIG_CPU_IDLE) += cpuidle.o
8obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 8obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
12 board-mop500-uib.o board-mop500-stuib.o \ 12 board-mop500-uib.o board-mop500-stuib.o \
13 board-mop500-u8500uib.o \ 13 board-mop500-u8500uib.o \
14 board-mop500-pins.o \ 14 board-mop500-pins.o \
15 board-mop500-msp.o 15 board-mop500-audio.o
16obj-$(CONFIG_SMP) += platsmp.o headsmp.o 16obj-$(CONFIG_SMP) += platsmp.o headsmp.o
17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
index df15646036aa..070629a95625 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,7 +7,6 @@
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/gpio.h> 9#include <linux/gpio.h>
10#include <linux/pinctrl/consumer.h>
11 10
12#include <plat/gpio-nomadik.h> 11#include <plat/gpio-nomadik.h>
13#include <plat/pincfg.h> 12#include <plat/pincfg.h>
@@ -23,53 +22,6 @@
23#include "devices-db8500.h" 22#include "devices-db8500.h"
24#include "pins-db8500.h" 23#include "pins-db8500.h"
25 24
26/* MSP1/3 Tx/Rx usage protection */
27static DEFINE_SPINLOCK(msp_rxtx_lock);
28
29/* Reference Count */
30static int msp_rxtx_ref;
31
32/* Pin modes */
33struct pinctrl *msp1_p;
34struct pinctrl_state *msp1_def;
35struct pinctrl_state *msp1_sleep;
36
37int msp13_i2s_init(void)
38{
39 int retval = 0;
40 unsigned long flags;
41
42 spin_lock_irqsave(&msp_rxtx_lock, flags);
43 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
44 retval = pinctrl_select_state(msp1_p, msp1_def);
45 if (retval)
46 pr_err("could not set MSP1 defstate\n");
47 }
48 if (!retval)
49 msp_rxtx_ref++;
50 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
51
52 return retval;
53}
54
55int msp13_i2s_exit(void)
56{
57 int retval = 0;
58 unsigned long flags;
59
60 spin_lock_irqsave(&msp_rxtx_lock, flags);
61 WARN_ON(!msp_rxtx_ref);
62 msp_rxtx_ref--;
63 if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
64 retval = pinctrl_select_state(msp1_p, msp1_sleep);
65 if (retval)
66 pr_err("could not set MSP1 sleepstate\n");
67 }
68 spin_unlock_irqrestore(&msp_rxtx_lock, flags);
69
70 return retval;
71}
72
73static struct stedma40_chan_cfg msp0_dma_rx = { 25static struct stedma40_chan_cfg msp0_dma_rx = {
74 .high_priority = true, 26 .high_priority = true,
75 .dir = STEDMA40_PERIPH_TO_MEM, 27 .dir = STEDMA40_PERIPH_TO_MEM,
@@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
96 /* data_width is set during configuration */ 48 /* data_width is set during configuration */
97}; 49};
98 50
99static struct msp_i2s_platform_data msp0_platform_data = { 51struct msp_i2s_platform_data msp0_platform_data = {
100 .id = MSP_I2S_0, 52 .id = MSP_I2S_0,
101 .msp_i2s_dma_rx = &msp0_dma_rx, 53 .msp_i2s_dma_rx = &msp0_dma_rx,
102 .msp_i2s_dma_tx = &msp0_dma_tx, 54 .msp_i2s_dma_tx = &msp0_dma_tx,
@@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
128 /* data_width is set during configuration */ 80 /* data_width is set during configuration */
129}; 81};
130 82
131static struct msp_i2s_platform_data msp1_platform_data = { 83struct msp_i2s_platform_data msp1_platform_data = {
132 .id = MSP_I2S_1, 84 .id = MSP_I2S_1,
133 .msp_i2s_dma_rx = NULL, 85 .msp_i2s_dma_rx = NULL,
134 .msp_i2s_dma_tx = &msp1_dma_tx, 86 .msp_i2s_dma_tx = &msp1_dma_tx,
135 .msp_i2s_init = msp13_i2s_init,
136 .msp_i2s_exit = msp13_i2s_exit,
137}; 87};
138 88
139static struct stedma40_chan_cfg msp2_dma_rx = { 89static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
193 143
194/* Platform device for ASoC MOP500 machine */ 144/* Platform device for ASoC MOP500 machine */
195static struct platform_device snd_soc_mop500 = { 145static struct platform_device snd_soc_mop500 = {
196 .name = "snd-soc-mop500", 146 .name = "snd-soc-mop500",
197 .id = 0, 147 .id = 0,
198 .dev = { 148 .dev = {
199 .platform_data = NULL, 149 .platform_data = NULL,
200 }, 150 },
201}; 151};
202 152
203/* Platform device for Ux500-PCM */ 153/* Platform device for Ux500-PCM */
@@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = {
209 }, 159 },
210}; 160};
211 161
212static struct msp_i2s_platform_data msp2_platform_data = { 162struct msp_i2s_platform_data msp2_platform_data = {
213 .id = MSP_I2S_2, 163 .id = MSP_I2S_2,
214 .msp_i2s_dma_rx = &msp2_dma_rx, 164 .msp_i2s_dma_rx = &msp2_dma_rx,
215 .msp_i2s_dma_tx = &msp2_dma_tx, 165 .msp_i2s_dma_tx = &msp2_dma_tx,
216}; 166};
217 167
218static struct msp_i2s_platform_data msp3_platform_data = { 168struct msp_i2s_platform_data msp3_platform_data = {
219 .id = MSP_I2S_3, 169 .id = MSP_I2S_3,
220 .msp_i2s_dma_rx = &msp1_dma_rx, 170 .msp_i2s_dma_rx = &msp1_dma_rx,
221 .msp_i2s_dma_tx = NULL, 171 .msp_i2s_dma_tx = NULL,
222 .msp_i2s_init = msp13_i2s_init,
223 .msp_i2s_exit = msp13_i2s_exit,
224}; 172};
225 173
226int mop500_msp_init(struct device *parent) 174void mop500_audio_init(struct device *parent)
227{ 175{
228 struct platform_device *msp1;
229
230 pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__); 176 pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
231 platform_device_register(&snd_soc_mop500); 177 platform_device_register(&snd_soc_mop500);
232 178
233 pr_info("Initialize MSP I2S-devices.\n"); 179 pr_info("Initialize MSP I2S-devices.\n");
234 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, 180 db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
235 &msp0_platform_data); 181 &msp0_platform_data);
236 msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, 182 db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
237 &msp1_platform_data); 183 &msp1_platform_data);
238 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, 184 db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
239 &msp2_platform_data); 185 &msp2_platform_data);
240 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, 186 db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
241 &msp3_platform_data); 187 &msp3_platform_data);
188}
242 189
243 /* Get the pinctrl handle for MSP1 */ 190/* Due for removal once the MSP driver has been fully DT:ed. */
244 if (msp1) { 191void mop500_of_audio_init(struct device *parent)
245 msp1_p = pinctrl_get(&msp1->dev); 192{
246 if (IS_ERR(msp1_p))
247 dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
248 else {
249 msp1_def = pinctrl_lookup_state(msp1_p,
250 PINCTRL_STATE_DEFAULT);
251 if (IS_ERR(msp1_def)) {
252 dev_err(&msp1->dev,
253 "could not get MSP1 defstate\n");
254 }
255 msp1_sleep = pinctrl_lookup_state(msp1_p,
256 PINCTRL_STATE_SLEEP);
257 if (IS_ERR(msp1_sleep))
258 dev_err(&msp1->dev,
259 "could not get MSP1 idlestate\n");
260 }
261 }
262
263 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__); 193 pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
264 platform_device_register(&ux500_pcm); 194 platform_device_register(&ux500_pcm);
265
266 return 0;
267} 195}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e2cc94..000000000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2012
3 *
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * for ST-Ericsson.
6 *
7 * License terms:
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 18ff781cfbe4..9c8e4a9e83ee 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
152}; 152};
153#endif 153#endif
154 154
155static struct mmci_platform_data mop500_sdi1_data = { 155struct mmci_platform_data mop500_sdi1_data = {
156 .ocr_mask = MMC_VDD_29_30, 156 .ocr_mask = MMC_VDD_29_30,
157 .f_max = 50000000, 157 .f_max = 50000000,
158 .capabilities = MMC_CAP_4_BIT_DATA, 158 .capabilities = MMC_CAP_4_BIT_DATA,
@@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
189}; 189};
190#endif 190#endif
191 191
192static struct mmci_platform_data mop500_sdi2_data = { 192struct mmci_platform_data mop500_sdi2_data = {
193 .ocr_mask = MMC_VDD_165_195, 193 .ocr_mask = MMC_VDD_165_195,
194 .f_max = 50000000, 194 .f_max = 50000000,
195 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | 195 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 1d2e3c6f8b59..12ab21d5511f 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -54,7 +54,6 @@
54#include "devices-db8500.h" 54#include "devices-db8500.h"
55#include "board-mop500.h" 55#include "board-mop500.h"
56#include "board-mop500-regulators.h" 56#include "board-mop500-regulators.h"
57#include "board-mop500-msp.h"
58 57
59static struct gpio_led snowball_led_array[] = { 58static struct gpio_led snowball_led_array[] = {
60 { 59 {
@@ -587,7 +586,7 @@ static void __init mop500_init_machine(void)
587 mop500_i2c_init(parent); 586 mop500_i2c_init(parent);
588 mop500_sdi_init(parent); 587 mop500_sdi_init(parent);
589 mop500_spi_init(parent); 588 mop500_spi_init(parent);
590 mop500_msp_init(parent); 589 mop500_audio_init(parent);
591 mop500_uart_init(parent); 590 mop500_uart_init(parent);
592 591
593 u8500_cryp1_hash1_init(parent); 592 u8500_cryp1_hash1_init(parent);
@@ -621,7 +620,7 @@ static void __init snowball_init_machine(void)
621 mop500_i2c_init(parent); 620 mop500_i2c_init(parent);
622 snowball_sdi_init(parent); 621 snowball_sdi_init(parent);
623 mop500_spi_init(parent); 622 mop500_spi_init(parent);
624 mop500_msp_init(parent); 623 mop500_audio_init(parent);
625 mop500_uart_init(parent); 624 mop500_uart_init(parent);
626 625
627 /* This board has full regulator constraints */ 626 /* This board has full regulator constraints */
@@ -653,7 +652,7 @@ static void __init hrefv60_init_machine(void)
653 mop500_i2c_init(parent); 652 mop500_i2c_init(parent);
654 hrefv60_sdi_init(parent); 653 hrefv60_sdi_init(parent);
655 mop500_spi_init(parent); 654 mop500_spi_init(parent);
656 mop500_msp_init(parent); 655 mop500_audio_init(parent);
657 mop500_uart_init(parent); 656 mop500_uart_init(parent);
658 657
659 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 658 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -705,12 +704,9 @@ MACHINE_END
705 704
706#ifdef CONFIG_MACH_UX500_DT 705#ifdef CONFIG_MACH_UX500_DT
707 706
708static struct platform_device *snowball_of_platform_devs[] __initdata = {
709 &snowball_led_dev,
710 &snowball_key_dev,
711};
712
713struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { 707struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
708 /* Requires call-back bindings. */
709 OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
714 /* Requires DMA and call-back bindings. */ 710 /* Requires DMA and call-back bindings. */
715 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), 711 OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
716 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat), 712 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
@@ -718,6 +714,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
718 /* Requires DMA bindings. */ 714 /* Requires DMA bindings. */
719 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 715 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
720 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 716 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
717 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
718 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
721 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), 719 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
722 /* Requires clock name bindings. */ 720 /* Requires clock name bindings. */
723 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), 721 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
@@ -736,6 +734,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
736 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), 734 OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
737 /* Requires device name bindings. */ 735 /* Requires device name bindings. */
738 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), 736 OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
737 /* Requires clock name and DMA bindings. */
738 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
739 "ux500-msp-i2s.0", &msp0_platform_data),
740 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
741 "ux500-msp-i2s.1", &msp1_platform_data),
742 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
743 "ux500-msp-i2s.2", &msp2_platform_data),
744 OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
745 "ux500-msp-i2s.3", &msp3_platform_data),
739 {}, 746 {},
740}; 747};
741 748
@@ -776,7 +783,7 @@ static void __init u8500_init_machine(void)
776 ARRAY_SIZE(mop500_platform_devs)); 783 ARRAY_SIZE(mop500_platform_devs));
777 784
778 mop500_sdi_init(parent); 785 mop500_sdi_init(parent);
779 mop500_msp_init(parent); 786 mop500_audio_init(parent);
780 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); 787 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
781 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); 788 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
782 i2c_register_board_info(2, mop500_i2c2_devices, 789 i2c_register_board_info(2, mop500_i2c2_devices,
@@ -785,7 +792,7 @@ static void __init u8500_init_machine(void)
785 mop500_uib_init(); 792 mop500_uib_init();
786 793
787 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { 794 } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
788 mop500_msp_init(parent); 795 mop500_of_audio_init(parent);
789 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { 796 } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
790 /* 797 /*
791 * The HREFv60 board removed a GPIO expander and routed 798 * The HREFv60 board removed a GPIO expander and routed
@@ -796,16 +803,6 @@ static void __init u8500_init_machine(void)
796 platform_add_devices(mop500_platform_devs, 803 platform_add_devices(mop500_platform_devs,
797 ARRAY_SIZE(mop500_platform_devs)); 804 ARRAY_SIZE(mop500_platform_devs));
798 805
799 hrefv60_sdi_init(parent);
800 mop500_msp_init(parent);
801
802 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
803 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
804
805 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
806 i2c_register_board_info(2, mop500_i2c2_devices,
807 ARRAY_SIZE(mop500_i2c2_devices));
808
809 mop500_uib_init(); 806 mop500_uib_init();
810 } 807 }
811 808
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index b5bfc1a78b1a..aca39a68712a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
9 9
10/* For NOMADIK_NR_GPIO */ 10/* For NOMADIK_NR_GPIO */
11#include <mach/irqs.h> 11#include <mach/irqs.h>
12#include <mach/msp.h>
12#include <linux/amba/mmci.h> 13#include <linux/amba/mmci.h>
13 14
14/* Snowball specific GPIO assignments, this board has no GPIO expander */ 15/* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -80,7 +81,14 @@
80struct device; 81struct device;
81struct i2c_board_info; 82struct i2c_board_info;
82extern struct mmci_platform_data mop500_sdi0_data; 83extern struct mmci_platform_data mop500_sdi0_data;
84extern struct mmci_platform_data mop500_sdi1_data;
85extern struct mmci_platform_data mop500_sdi2_data;
83extern struct mmci_platform_data mop500_sdi4_data; 86extern struct mmci_platform_data mop500_sdi4_data;
87extern struct msp_i2s_platform_data msp0_platform_data;
88extern struct msp_i2s_platform_data msp1_platform_data;
89extern struct msp_i2s_platform_data msp2_platform_data;
90extern struct msp_i2s_platform_data msp3_platform_data;
91extern struct arm_pmu_platdata db8500_pmu_platdata;
84 92
85extern void mop500_sdi_init(struct device *parent); 93extern void mop500_sdi_init(struct device *parent);
86extern void snowball_sdi_init(struct device *parent); 94extern void snowball_sdi_init(struct device *parent);
@@ -91,6 +99,9 @@ void __init mop500_stuib_init(void);
91void __init mop500_pinmaps_init(void); 99void __init mop500_pinmaps_init(void);
92void __init snowball_pinmaps_init(void); 100void __init snowball_pinmaps_init(void);
93void __init hrefv60_pinmaps_init(void); 101void __init hrefv60_pinmaps_init(void);
102void mop500_audio_init(struct device *parent);
103/* Due for removal once the MSP driver has been fully DT:ed. */
104void mop500_of_audio_init(struct device *parent);
94 105
95int __init mop500_uib_init(void); 106int __init mop500_uib_init(void);
96void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info, 107void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
deleted file mode 100644
index 8d73b066a18d..000000000000
--- a/arch/arm/mach-ux500/clock.c
+++ /dev/null
@@ -1,715 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/clkdev.h>
17#include <linux/cpufreq.h>
18
19#include <plat/mtu.h>
20#include <mach/hardware.h>
21#include "clock.h"
22
23#ifdef CONFIG_DEBUG_FS
24#include <linux/debugfs.h>
25#include <linux/uaccess.h> /* for copy_from_user */
26static LIST_HEAD(clk_list);
27#endif
28
29#define PRCC_PCKEN 0x00
30#define PRCC_PCKDIS 0x04
31#define PRCC_KCKEN 0x08
32#define PRCC_KCKDIS 0x0C
33
34#define PRCM_YYCLKEN0_MGT_SET 0x510
35#define PRCM_YYCLKEN1_MGT_SET 0x514
36#define PRCM_YYCLKEN0_MGT_CLR 0x518
37#define PRCM_YYCLKEN1_MGT_CLR 0x51C
38#define PRCM_YYCLKEN0_MGT_VAL 0x520
39#define PRCM_YYCLKEN1_MGT_VAL 0x524
40
41#define PRCM_SVAMMDSPCLK_MGT 0x008
42#define PRCM_SIAMMDSPCLK_MGT 0x00C
43#define PRCM_SGACLK_MGT 0x014
44#define PRCM_UARTCLK_MGT 0x018
45#define PRCM_MSP02CLK_MGT 0x01C
46#define PRCM_MSP1CLK_MGT 0x288
47#define PRCM_I2CCLK_MGT 0x020
48#define PRCM_SDMMCCLK_MGT 0x024
49#define PRCM_SLIMCLK_MGT 0x028
50#define PRCM_PER1CLK_MGT 0x02C
51#define PRCM_PER2CLK_MGT 0x030
52#define PRCM_PER3CLK_MGT 0x034
53#define PRCM_PER5CLK_MGT 0x038
54#define PRCM_PER6CLK_MGT 0x03C
55#define PRCM_PER7CLK_MGT 0x040
56#define PRCM_LCDCLK_MGT 0x044
57#define PRCM_BMLCLK_MGT 0x04C
58#define PRCM_HSITXCLK_MGT 0x050
59#define PRCM_HSIRXCLK_MGT 0x054
60#define PRCM_HDMICLK_MGT 0x058
61#define PRCM_APEATCLK_MGT 0x05C
62#define PRCM_APETRACECLK_MGT 0x060
63#define PRCM_MCDECLK_MGT 0x064
64#define PRCM_IPI2CCLK_MGT 0x068
65#define PRCM_DSIALTCLK_MGT 0x06C
66#define PRCM_DMACLK_MGT 0x074
67#define PRCM_B2R2CLK_MGT 0x078
68#define PRCM_TVCLK_MGT 0x07C
69#define PRCM_TCR 0x1C8
70#define PRCM_TCR_STOPPED (1 << 16)
71#define PRCM_TCR_DOZE_MODE (1 << 17)
72#define PRCM_UNIPROCLK_MGT 0x278
73#define PRCM_SSPCLK_MGT 0x280
74#define PRCM_RNGCLK_MGT 0x284
75#define PRCM_UICCCLK_MGT 0x27C
76
77#define PRCM_MGT_ENABLE (1 << 8)
78
79static DEFINE_SPINLOCK(clocks_lock);
80
81static void __clk_enable(struct clk *clk)
82{
83 if (clk->enabled++ == 0) {
84 if (clk->parent_cluster)
85 __clk_enable(clk->parent_cluster);
86
87 if (clk->parent_periph)
88 __clk_enable(clk->parent_periph);
89
90 if (clk->ops && clk->ops->enable)
91 clk->ops->enable(clk);
92 }
93}
94
95int clk_enable(struct clk *clk)
96{
97 unsigned long flags;
98
99 spin_lock_irqsave(&clocks_lock, flags);
100 __clk_enable(clk);
101 spin_unlock_irqrestore(&clocks_lock, flags);
102
103 return 0;
104}
105EXPORT_SYMBOL(clk_enable);
106
107static void __clk_disable(struct clk *clk)
108{
109 if (--clk->enabled == 0) {
110 if (clk->ops && clk->ops->disable)
111 clk->ops->disable(clk);
112
113 if (clk->parent_periph)
114 __clk_disable(clk->parent_periph);
115
116 if (clk->parent_cluster)
117 __clk_disable(clk->parent_cluster);
118 }
119}
120
121void clk_disable(struct clk *clk)
122{
123 unsigned long flags;
124
125 WARN_ON(!clk->enabled);
126
127 spin_lock_irqsave(&clocks_lock, flags);
128 __clk_disable(clk);
129 spin_unlock_irqrestore(&clocks_lock, flags);
130}
131EXPORT_SYMBOL(clk_disable);
132
133/*
134 * The MTU has a separate, rather complex muxing setup
135 * with alternative parents (peripheral cluster or
136 * ULP or fixed 32768 Hz) depending on settings
137 */
138static unsigned long clk_mtu_get_rate(struct clk *clk)
139{
140 void __iomem *addr;
141 u32 tcr;
142 int mtu = (int) clk->data;
143 /*
144 * One of these is selected eventually
145 * TODO: Replace the constant with a reference
146 * to the ULP source once this is modeled.
147 */
148 unsigned long clk32k = 32768;
149 unsigned long mturate;
150 unsigned long retclk;
151
152 if (cpu_is_u8500_family())
153 addr = __io_address(U8500_PRCMU_BASE);
154 else
155 ux500_unknown_soc();
156
157 /*
158 * On a startup, always conifgure the TCR to the doze mode;
159 * bootloaders do it for us. Do this in the kernel too.
160 */
161 writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
162
163 tcr = readl(addr + PRCM_TCR);
164
165 /* Get the rate from the parent as a default */
166 if (clk->parent_periph)
167 mturate = clk_get_rate(clk->parent_periph);
168 else if (clk->parent_cluster)
169 mturate = clk_get_rate(clk->parent_cluster);
170 else
171 /* We need to be connected SOMEWHERE */
172 BUG();
173
174 /* Return the clock selected for this MTU */
175 if (tcr & (1 << mtu))
176 retclk = clk32k;
177 else
178 retclk = mturate;
179
180 pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
181 return retclk;
182}
183
184unsigned long clk_get_rate(struct clk *clk)
185{
186 unsigned long rate;
187
188 /*
189 * If there is a custom getrate callback for this clock,
190 * it will take precedence.
191 */
192 if (clk->get_rate)
193 return clk->get_rate(clk);
194
195 if (clk->ops && clk->ops->get_rate)
196 return clk->ops->get_rate(clk);
197
198 rate = clk->rate;
199 if (!rate) {
200 if (clk->parent_periph)
201 rate = clk_get_rate(clk->parent_periph);
202 else if (clk->parent_cluster)
203 rate = clk_get_rate(clk->parent_cluster);
204 }
205
206 return rate;
207}
208EXPORT_SYMBOL(clk_get_rate);
209
210long clk_round_rate(struct clk *clk, unsigned long rate)
211{
212 /*TODO*/
213 return rate;
214}
215EXPORT_SYMBOL(clk_round_rate);
216
217int clk_set_rate(struct clk *clk, unsigned long rate)
218{
219 clk->rate = rate;
220 return 0;
221}
222EXPORT_SYMBOL(clk_set_rate);
223
224int clk_set_parent(struct clk *clk, struct clk *parent)
225{
226 /*TODO*/
227 return -ENOSYS;
228}
229EXPORT_SYMBOL(clk_set_parent);
230
231static void clk_prcmu_enable(struct clk *clk)
232{
233 void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
234 + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
235
236 writel(1 << clk->prcmu_cg_bit, cg_set_reg);
237}
238
239static void clk_prcmu_disable(struct clk *clk)
240{
241 void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
242 + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
243
244 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
245}
246
247static struct clkops clk_prcmu_ops = {
248 .enable = clk_prcmu_enable,
249 .disable = clk_prcmu_disable,
250};
251
252static unsigned int clkrst_base[] = {
253 [1] = U8500_CLKRST1_BASE,
254 [2] = U8500_CLKRST2_BASE,
255 [3] = U8500_CLKRST3_BASE,
256 [5] = U8500_CLKRST5_BASE,
257 [6] = U8500_CLKRST6_BASE,
258};
259
260static void clk_prcc_enable(struct clk *clk)
261{
262 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
263
264 if (clk->prcc_kernel != -1)
265 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
266
267 if (clk->prcc_bus != -1)
268 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
269}
270
271static void clk_prcc_disable(struct clk *clk)
272{
273 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
274
275 if (clk->prcc_bus != -1)
276 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
277
278 if (clk->prcc_kernel != -1)
279 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
280}
281
282static struct clkops clk_prcc_ops = {
283 .enable = clk_prcc_enable,
284 .disable = clk_prcc_disable,
285};
286
287static struct clk clk_32khz = {
288 .name = "clk_32khz",
289 .rate = 32000,
290};
291
292/*
293 * PRCMU level clock gating
294 */
295
296/* Bank 0 */
297static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
298static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
299static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
300static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
301static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
302static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
303static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
304static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 100000000);
305static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
306static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
307static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
308static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
309static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
310static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
311static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
312static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
313static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
314static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
315static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
316static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
317static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
318static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
319static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
320static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
321static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
322static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
323static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
324static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
325static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
326
327/* Bank 1 */
328static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
329static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
330
331/*
332 * PRCC level clock gating
333 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
334 */
335
336/* Peripheral Cluster #1 */
337static DEFINE_PRCC_CLK(1, msp3, 11, 10, &clk_msp1clk);
338static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
339static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
340static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
341static DEFINE_PRCC_CLK(1, spi3, 7, -1, NULL);
342static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
343static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
344static DEFINE_PRCC_CLK(1, msp1, 4, 4, &clk_msp1clk);
345static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
346static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
347static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
348static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
349
350/* Peripheral Cluster #2 */
351static DEFINE_PRCC_CLK(2, gpio1, 11, -1, NULL);
352static DEFINE_PRCC_CLK(2, ssitx, 10, 7, NULL);
353static DEFINE_PRCC_CLK(2, ssirx, 9, 6, NULL);
354static DEFINE_PRCC_CLK(2, spi0, 8, -1, NULL);
355static DEFINE_PRCC_CLK(2, sdi3, 7, 5, &clk_sdmmcclk);
356static DEFINE_PRCC_CLK(2, sdi1, 6, 4, &clk_sdmmcclk);
357static DEFINE_PRCC_CLK(2, msp2, 5, 3, &clk_msp02clk);
358static DEFINE_PRCC_CLK(2, sdi4, 4, 2, &clk_sdmmcclk);
359static DEFINE_PRCC_CLK(2, pwl, 3, 1, NULL);
360static DEFINE_PRCC_CLK(2, spi1, 2, -1, NULL);
361static DEFINE_PRCC_CLK(2, spi2, 1, -1, NULL);
362static DEFINE_PRCC_CLK(2, i2c3, 0, 0, &clk_i2cclk);
363
364/* Peripheral Cluster #3 */
365static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
366static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
367static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
368static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
369static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
370static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
371static DEFINE_PRCC_CLK(3, ssp1, 2, 2, &clk_sspclk);
372static DEFINE_PRCC_CLK(3, ssp0, 1, 1, &clk_sspclk);
373static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
374
375/* Peripheral Cluster #4 is in the always on domain */
376
377/* Peripheral Cluster #5 */
378static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
379static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
380
381/* Peripheral Cluster #6 */
382
383/* MTU ID in data */
384static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
385static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
386static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
387static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
388static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
389static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
390static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
391static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
392static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
393static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
394
395static struct clk clk_dummy_apb_pclk = {
396 .name = "apb_pclk",
397};
398
399static struct clk_lookup u8500_clks[] = {
400 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
401
402 /* Peripheral Cluster #1 */
403 CLK(gpio0, "gpio.0", NULL),
404 CLK(gpio0, "gpio.1", NULL),
405 CLK(slimbus0, "slimbus0", NULL),
406 CLK(i2c2, "nmk-i2c.2", NULL),
407 CLK(sdi0, "sdi0", NULL),
408 CLK(msp0, "ux500-msp-i2s.0", NULL),
409 CLK(i2c1, "nmk-i2c.1", NULL),
410 CLK(uart1, "uart1", NULL),
411 CLK(uart0, "uart0", NULL),
412
413 /* Peripheral Cluster #3 */
414 CLK(gpio2, "gpio.2", NULL),
415 CLK(gpio2, "gpio.3", NULL),
416 CLK(gpio2, "gpio.4", NULL),
417 CLK(gpio2, "gpio.5", NULL),
418 CLK(sdi5, "sdi5", NULL),
419 CLK(uart2, "uart2", NULL),
420 CLK(ske, "ske", NULL),
421 CLK(ske, "nmk-ske-keypad", NULL),
422 CLK(sdi2, "sdi2", NULL),
423 CLK(i2c0, "nmk-i2c.0", NULL),
424 CLK(fsmc, "fsmc", NULL),
425
426 /* Peripheral Cluster #5 */
427 CLK(gpio3, "gpio.8", NULL),
428
429 /* Peripheral Cluster #6 */
430 CLK(hash1, "hash1", NULL),
431 CLK(pka, "pka", NULL),
432 CLK(hash0, "hash0", NULL),
433 CLK(cryp0, "cryp0", NULL),
434 CLK(cryp1, "cryp1", NULL),
435
436 /* PRCMU level clock gating */
437
438 /* Bank 0 */
439 CLK(svaclk, "sva", NULL),
440 CLK(siaclk, "sia", NULL),
441 CLK(sgaclk, "sga", NULL),
442 CLK(slimclk, "slim", NULL),
443 CLK(lcdclk, "lcd", NULL),
444 CLK(bmlclk, "bml", NULL),
445 CLK(hsitxclk, "stm-hsi.0", NULL),
446 CLK(hsirxclk, "stm-hsi.1", NULL),
447 CLK(hdmiclk, "hdmi", NULL),
448 CLK(apeatclk, "apeat", NULL),
449 CLK(apetraceclk, "apetrace", NULL),
450 CLK(mcdeclk, "mcde", NULL),
451 CLK(ipi2clk, "ipi2", NULL),
452 CLK(dmaclk, "dma40.0", NULL),
453 CLK(b2r2clk, "b2r2", NULL),
454 CLK(tvclk, "tv", NULL),
455
456 /* Peripheral Cluster #1 */
457 CLK(i2c4, "nmk-i2c.4", NULL),
458 CLK(spi3, "spi3", NULL),
459 CLK(msp1, "ux500-msp-i2s.1", NULL),
460 CLK(msp3, "ux500-msp-i2s.3", NULL),
461
462 /* Peripheral Cluster #2 */
463 CLK(gpio1, "gpio.6", NULL),
464 CLK(gpio1, "gpio.7", NULL),
465 CLK(ssitx, "ssitx", NULL),
466 CLK(ssirx, "ssirx", NULL),
467 CLK(spi0, "spi0", NULL),
468 CLK(sdi3, "sdi3", NULL),
469 CLK(sdi1, "sdi1", NULL),
470 CLK(msp2, "ux500-msp-i2s.2", NULL),
471 CLK(sdi4, "sdi4", NULL),
472 CLK(pwl, "pwl", NULL),
473 CLK(spi1, "spi1", NULL),
474 CLK(spi2, "spi2", NULL),
475 CLK(i2c3, "nmk-i2c.3", NULL),
476
477 /* Peripheral Cluster #3 */
478 CLK(ssp1, "ssp1", NULL),
479 CLK(ssp0, "ssp0", NULL),
480
481 /* Peripheral Cluster #5 */
482 CLK(usb, "musb-ux500.0", "usb"),
483
484 /* Peripheral Cluster #6 */
485 CLK(mtu1, "mtu1", NULL),
486 CLK(mtu0, "mtu0", NULL),
487 CLK(cfgreg, "cfgreg", NULL),
488 CLK(hash1, "hash1", NULL),
489 CLK(unipro, "unipro", NULL),
490 CLK(rng, "rng", NULL),
491
492 /* PRCMU level clock gating */
493
494 /* Bank 0 */
495 CLK(uniproclk, "uniproclk", NULL),
496 CLK(dsialtclk, "dsialt", NULL),
497
498 /* Bank 1 */
499 CLK(rngclk, "rng", NULL),
500 CLK(uiccclk, "uicc", NULL),
501};
502
503#ifdef CONFIG_DEBUG_FS
504/*
505 * debugfs support to trace clock tree hierarchy and attributes with
506 * powerdebug
507 */
508static struct dentry *clk_debugfs_root;
509
510void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
511{
512 while (num--) {
513 /* Check that the clock has not been already registered */
514 if (!(cl->clk->list.prev != cl->clk->list.next))
515 list_add_tail(&cl->clk->list, &clk_list);
516
517 cl++;
518 }
519}
520
521static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
522 size_t size, loff_t *off)
523{
524 struct clk *clk = file->f_dentry->d_inode->i_private;
525 char cusecount[128];
526 unsigned int len;
527
528 len = sprintf(cusecount, "%u\n", clk->enabled);
529 return simple_read_from_buffer(buf, size, off, cusecount, len);
530}
531
532static ssize_t rate_dbg_read(struct file *file, char __user *buf,
533 size_t size, loff_t *off)
534{
535 struct clk *clk = file->f_dentry->d_inode->i_private;
536 char crate[128];
537 unsigned int rate;
538 unsigned int len;
539
540 rate = clk_get_rate(clk);
541 len = sprintf(crate, "%u\n", rate);
542 return simple_read_from_buffer(buf, size, off, crate, len);
543}
544
545static const struct file_operations usecount_fops = {
546 .read = usecount_dbg_read,
547};
548
549static const struct file_operations set_rate_fops = {
550 .read = rate_dbg_read,
551};
552
553static struct dentry *clk_debugfs_register_dir(struct clk *c,
554 struct dentry *p_dentry)
555{
556 struct dentry *d, *clk_d;
557 const char *p = c->name;
558
559 if (!p)
560 p = "BUG";
561
562 clk_d = debugfs_create_dir(p, p_dentry);
563 if (!clk_d)
564 return NULL;
565
566 d = debugfs_create_file("usecount", S_IRUGO,
567 clk_d, c, &usecount_fops);
568 if (!d)
569 goto err_out;
570 d = debugfs_create_file("rate", S_IRUGO,
571 clk_d, c, &set_rate_fops);
572 if (!d)
573 goto err_out;
574 /*
575 * TODO : not currently available in ux500
576 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
577 * if (!d)
578 * goto err_out;
579 */
580
581 return clk_d;
582
583err_out:
584 debugfs_remove_recursive(clk_d);
585 return NULL;
586}
587
588static int clk_debugfs_register_one(struct clk *c)
589{
590 struct clk *pa = c->parent_periph;
591 struct clk *bpa = c->parent_cluster;
592
593 if (!(bpa && !pa)) {
594 c->dent = clk_debugfs_register_dir(c,
595 pa ? pa->dent : clk_debugfs_root);
596 if (!c->dent)
597 return -ENOMEM;
598 }
599
600 if (bpa) {
601 c->dent_bus = clk_debugfs_register_dir(c,
602 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
603 if ((!c->dent_bus) && (c->dent)) {
604 debugfs_remove_recursive(c->dent);
605 c->dent = NULL;
606 return -ENOMEM;
607 }
608 }
609 return 0;
610}
611
612static int clk_debugfs_register(struct clk *c)
613{
614 int err;
615 struct clk *pa = c->parent_periph;
616 struct clk *bpa = c->parent_cluster;
617
618 if (pa && (!pa->dent && !pa->dent_bus)) {
619 err = clk_debugfs_register(pa);
620 if (err)
621 return err;
622 }
623
624 if (bpa && (!bpa->dent && !bpa->dent_bus)) {
625 err = clk_debugfs_register(bpa);
626 if (err)
627 return err;
628 }
629
630 if ((!c->dent) && (!c->dent_bus)) {
631 err = clk_debugfs_register_one(c);
632 if (err)
633 return err;
634 }
635 return 0;
636}
637
638int __init clk_debugfs_init(void)
639{
640 struct clk *c;
641 struct dentry *d;
642 int err;
643
644 d = debugfs_create_dir("clock", NULL);
645 if (!d)
646 return -ENOMEM;
647 clk_debugfs_root = d;
648
649 list_for_each_entry(c, &clk_list, list) {
650 err = clk_debugfs_register(c);
651 if (err)
652 goto err_out;
653 }
654 return 0;
655err_out:
656 debugfs_remove_recursive(clk_debugfs_root);
657 return err;
658}
659
660#endif /* defined(CONFIG_DEBUG_FS) */
661
662unsigned long clk_smp_twd_rate = 500000000;
663
664unsigned long clk_smp_twd_get_rate(struct clk *clk)
665{
666 return clk_smp_twd_rate;
667}
668
669static struct clk clk_smp_twd = {
670 .get_rate = clk_smp_twd_get_rate,
671 .name = "smp_twd",
672};
673
674static struct clk_lookup clk_smp_twd_lookup = {
675 .dev_id = "smp_twd",
676 .clk = &clk_smp_twd,
677};
678
679#ifdef CONFIG_CPU_FREQ
680
681static int clk_twd_cpufreq_transition(struct notifier_block *nb,
682 unsigned long state, void *data)
683{
684 struct cpufreq_freqs *f = data;
685
686 if (state == CPUFREQ_PRECHANGE) {
687 /* Save frequency in simple Hz */
688 clk_smp_twd_rate = (f->new * 1000) / 2;
689 }
690
691 return NOTIFY_OK;
692}
693
694static struct notifier_block clk_twd_cpufreq_nb = {
695 .notifier_call = clk_twd_cpufreq_transition,
696};
697
698int clk_init_smp_twd_cpufreq(void)
699{
700 return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
701 CPUFREQ_TRANSITION_NOTIFIER);
702}
703
704#endif
705
706int __init clk_init(void)
707{
708 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
709 clkdev_add(&clk_smp_twd_lookup);
710
711#ifdef CONFIG_DEBUG_FS
712 clk_debugfs_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
713#endif
714 return 0;
715}
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
deleted file mode 100644
index 65d27a13f46d..000000000000
--- a/arch/arm/mach-ux500/clock.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * Copyright (C) 2010 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/**
11 * struct clkops - ux500 clock operations
12 * @enable: function to enable the clock
13 * @disable: function to disable the clock
14 * @get_rate: function to get the current clock rate
15 *
16 * This structure contains function pointers to functions that will be used to
17 * control the clock. All of these functions are optional. If get_rate is
18 * NULL, the rate in the struct clk will be used.
19 */
20struct clkops {
21 void (*enable) (struct clk *);
22 void (*disable) (struct clk *);
23 unsigned long (*get_rate) (struct clk *);
24 int (*set_parent)(struct clk *, struct clk *);
25};
26
27/**
28 * struct clk - ux500 clock structure
29 * @ops: pointer to clkops struct used to control this clock
30 * @name: name, for debugging
31 * @enabled: refcount. positive if enabled, zero if disabled
32 * @get_rate: custom callback for getting the clock rate
33 * @data: custom per-clock data for example for the get_rate
34 * callback
35 * @rate: fixed rate for clocks which don't implement
36 * ops->getrate
37 * @prcmu_cg_off: address offset of the combined enable/disable register
38 * (used on u8500v1)
39 * @prcmu_cg_bit: bit in the combined enable/disable register (used on
40 * u8500v1)
41 * @prcmu_cg_mgt: address of the enable/disable register (used on
42 * u8500ed)
43 * @cluster: peripheral cluster number
44 * @prcc_bus: bit for the bus clock in the peripheral's CLKRST
45 * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
46 * -1 if no kernel clock exists.
47 * @parent_cluster: pointer to parent's cluster clk struct
48 * @parent_periph: pointer to parent's peripheral clk struct
49 *
50 * Peripherals are organised into clusters, and each cluster has an associated
51 * bus clock. Some peripherals also have a parent peripheral clock.
52 *
53 * In order to enable a clock for a peripheral, we need to enable:
54 * (1) the parent cluster (bus) clock at the PRCMU level
55 * (2) the parent peripheral clock (if any) at the PRCMU level
56 * (3) the peripheral's bus & kernel clock at the PRCC level
57 *
58 * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
59 * of the cluster and peripheral clocks, and hooking these as the parents of
60 * the individual peripheral clocks.
61 *
62 * (3) is handled by specifying the bits in the PRCC control registers required
63 * to enable these clocks and modifying them in the ->enable and
64 * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
65 *
66 * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
67 * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
68 * prcc, and parent pointers are only used for the PRCC-level clocks.
69 */
70struct clk {
71 const struct clkops *ops;
72 const char *name;
73 unsigned int enabled;
74 unsigned long (*get_rate)(struct clk *);
75 void *data;
76
77 unsigned long rate;
78 struct list_head list;
79
80 /* These three are only for PRCMU clks */
81
82 unsigned int prcmu_cg_off;
83 unsigned int prcmu_cg_bit;
84 unsigned int prcmu_cg_mgt;
85
86 /* The rest are only for PRCC clks */
87
88 int cluster;
89 unsigned int prcc_bus;
90 unsigned int prcc_kernel;
91
92 struct clk *parent_cluster;
93 struct clk *parent_periph;
94#if defined(CONFIG_DEBUG_FS)
95 struct dentry *dent; /* For visible tree hierarchy */
96 struct dentry *dent_bus; /* For visible tree hierarchy */
97#endif
98};
99
100#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
101struct clk clk_##_name = { \
102 .name = #_name, \
103 .ops = &clk_prcmu_ops, \
104 .prcmu_cg_off = _cg_off, \
105 .prcmu_cg_bit = _cg_bit, \
106 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
107 }
108
109#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
110struct clk clk_##_name = { \
111 .name = #_name, \
112 .ops = &clk_prcmu_ops, \
113 .prcmu_cg_off = _cg_off, \
114 .prcmu_cg_bit = _cg_bit, \
115 .rate = _rate, \
116 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
117 }
118
119#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
120struct clk clk_##_name = { \
121 .name = #_name, \
122 .ops = &clk_prcc_ops, \
123 .cluster = _pclust, \
124 .prcc_bus = _bus_en, \
125 .prcc_kernel = _kernel_en, \
126 .parent_cluster = &clk_per##_pclust##clk, \
127 .parent_periph = _kernclk \
128 }
129
130#define DEFINE_PRCC_CLK_CUSTOM(_pclust, _name, _bus_en, _kernel_en, _kernclk, _callback, _data) \
131struct clk clk_##_name = { \
132 .name = #_name, \
133 .ops = &clk_prcc_ops, \
134 .cluster = _pclust, \
135 .prcc_bus = _bus_en, \
136 .prcc_kernel = _kernel_en, \
137 .parent_cluster = &clk_per##_pclust##clk, \
138 .parent_periph = _kernclk, \
139 .get_rate = _callback, \
140 .data = (void *) _data \
141 }
142
143
144#define CLK(_clk, _devname, _conname) \
145 { \
146 .clk = &clk_##_clk, \
147 .dev_id = _devname, \
148 .con_id = _conname, \
149 }
150
151int __init clk_db8500_ed_fixup(void);
152int __init clk_init(void);
153
154#ifdef CONFIG_DEBUG_FS
155int clk_debugfs_init(void);
156#else
157static inline int clk_debugfs_init(void) { return 0; }
158#endif
159
160#ifdef CONFIG_CPU_FREQ
161int clk_init_smp_twd_cpufreq(void);
162#else
163static inline int clk_init_smp_twd_cpufreq(void) { return 0; }
164#endif
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d56ca4..38b7f9c4788b 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -138,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = {
138 &db8500_prcmu_device, 138 &db8500_prcmu_device,
139}; 139};
140 140
141static struct platform_device *of_platform_devs[] __initdata = {
142 &u8500_dma40_device,
143};
144
145static resource_size_t __initdata db8500_gpio_base[] = { 141static resource_size_t __initdata db8500_gpio_base[] = {
146 U8500_GPIOBANK0_BASE, 142 U8500_GPIOBANK0_BASE,
147 U8500_GPIOBANK1_BASE, 143 U8500_GPIOBANK1_BASE,
@@ -235,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
235struct device * __init u8500_of_init_devices(void) 231struct device * __init u8500_of_init_devices(void)
236{ 232{
237 struct device *parent; 233 struct device *parent;
238 int i;
239 234
240 parent = db8500_soc_device_init(); 235 parent = db8500_soc_device_init();
241 236
@@ -244,8 +239,7 @@ struct device * __init u8500_of_init_devices(void)
244 platform_device_register_data(parent, 239 platform_device_register_data(parent,
245 "cpufreq-u8500", -1, NULL, 0); 240 "cpufreq-u8500", -1, NULL, 0);
246 241
247 for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++) 242 u8500_dma40_device.dev.parent = parent;
248 of_platform_devs[i]->dev.parent = parent;
249 243
250 /* 244 /*
251 * Devices to be DT:ed: 245 * Devices to be DT:ed:
@@ -253,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
253 * db8500_pmu_device = done 247 * db8500_pmu_device = done
254 * db8500_prcmu_device = done 248 * db8500_prcmu_device = done
255 */ 249 */
256 platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); 250 platform_device_register(&u8500_dma40_device);
257 251
258 return parent; 252 return parent;
259} 253}
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7c770d..17a78ec516ff 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,6 @@
8 8
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/io.h> 10#include <linux/io.h>
11#include <linux/clk.h>
12#include <linux/mfd/db8500-prcmu.h> 11#include <linux/mfd/db8500-prcmu.h>
13#include <linux/clksrc-dbx500-prcmu.h> 12#include <linux/clksrc-dbx500-prcmu.h>
14#include <linux/sys_soc.h> 13#include <linux/sys_soc.h>
@@ -17,6 +16,7 @@
17#include <linux/stat.h> 16#include <linux/stat.h>
18#include <linux/of.h> 17#include <linux/of.h>
19#include <linux/of_irq.h> 18#include <linux/of_irq.h>
19#include <linux/platform_data/clk-ux500.h>
20 20
21#include <asm/hardware/gic.h> 21#include <asm/hardware/gic.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
@@ -25,8 +25,6 @@
25#include <mach/setup.h> 25#include <mach/setup.h>
26#include <mach/devices.h> 26#include <mach/devices.h>
27 27
28#include "clock.h"
29
30void __iomem *_PRCMU_BASE; 28void __iomem *_PRCMU_BASE;
31 29
32/* 30/*
@@ -70,13 +68,17 @@ void __init ux500_init_irq(void)
70 */ 68 */
71 if (cpu_is_u8500_family()) 69 if (cpu_is_u8500_family())
72 db8500_prcmu_early_init(); 70 db8500_prcmu_early_init();
73 clk_init(); 71
72 if (cpu_is_u8500_family())
73 u8500_clk_init();
74 else if (cpu_is_u9540())
75 u9540_clk_init();
76 else if (cpu_is_u8540())
77 u8540_clk_init();
74} 78}
75 79
76void __init ux500_init_late(void) 80void __init ux500_init_late(void)
77{ 81{
78 clk_debugfs_init();
79 clk_init_smp_twd_cpufreq();
80} 82}
81 83
82static const char * __init ux500_get_machine(void) 84static const char * __init ux500_get_machine(void)
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19129ef..3cc7142eee02 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
22 enum msp_i2s_id id; 22 enum msp_i2s_id id;
23 struct stedma40_chan_cfg *msp_i2s_dma_rx; 23 struct stedma40_chan_cfg *msp_i2s_dma_rx;
24 struct stedma40_chan_cfg *msp_i2s_dma_tx; 24 struct stedma40_chan_cfg *msp_i2s_dma_tx;
25 int (*msp_i2s_init) (void);
26 int (*msp_i2s_exit) (void);
27}; 25};
28 26
29#endif 27#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 07:00:01 -0500