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-rw-r--r--arch/arm/mach-ux500/Kconfig15
-rw-r--r--arch/arm/mach-ux500/Makefile8
-rw-r--r--arch/arm/mach-ux500/Makefile.boot4
-rw-r--r--arch/arm/mach-ux500/board-mop500.c158
-rw-r--r--arch/arm/mach-ux500/clock.c95
-rw-r--r--arch/arm/mach-ux500/cpu-u8500.c64
-rw-r--r--arch/arm/mach-ux500/headsmp.S38
-rw-r--r--arch/arm/mach-ux500/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S19
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S89
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h131
-rw-r--r--arch/arm/mach-ux500/include/mach/io.h22
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h71
-rw-r--r--arch/arm/mach-ux500/include/mach/memory.h18
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h23
-rw-r--r--arch/arm/mach-ux500/include/mach/smp.h32
-rw-r--r--arch/arm/mach-ux500/include/mach/system.h25
-rw-r--r--arch/arm/mach-ux500/include/mach/timex.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h58
-rw-r--r--arch/arm/mach-ux500/include/mach/vmalloc.h18
-rw-r--r--arch/arm/mach-ux500/localtimer.c28
-rw-r--r--arch/arm/mach-ux500/platsmp.c177
22 files changed, 1106 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
new file mode 100644
index 000000000000..03625d744857
--- /dev/null
+++ b/arch/arm/mach-ux500/Kconfig
@@ -0,0 +1,15 @@
1menu "ST-Ericsson platform type"
2 depends on ARCH_U8500
3
4comment "ST-Ericsson Multicore Mobile Platforms"
5
6config MACH_U8500_MOP
7 bool "U8500 Early Development platform"
8 default y
9 select ARM_GIC
10 select HAS_MTU
11 help
12 Include support for mop500 development platform
13 based on U8500 architecture. The platform is based
14 on early drop silicon version of 8500.
15endmenu
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
new file mode 100644
index 000000000000..95e6e24c0042
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel, U8500 machine.
3#
4
5obj-y := clock.o
6obj-$(CONFIG_ARCH_U8500) += cpu-u8500.o
7obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o
8obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
diff --git a/arch/arm/mach-ux500/Makefile.boot b/arch/arm/mach-ux500/Makefile.boot
new file mode 100644
index 000000000000..c7e75acfe6c9
--- /dev/null
+++ b/arch/arm/mach-ux500/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
4
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
new file mode 100644
index 000000000000..aa5afbcc90f9
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2008-2009 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/amba/bus.h>
17#include <linux/amba/pl022.h>
18#include <linux/spi/spi.h>
19
20#include <asm/localtimer.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23
24#include <plat/mtu.h>
25
26#include <mach/hardware.h>
27#include <mach/setup.h>
28
29#define __MEM_4K_RESOURCE(x) \
30 .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
31
32/* These are active devices on this board */
33static struct amba_device uart0_device = {
34 .dev = { .init_name = "uart0" },
35 __MEM_4K_RESOURCE(U8500_UART0_BASE),
36 .irq = {IRQ_UART0, NO_IRQ},
37};
38
39static struct amba_device uart1_device = {
40 .dev = { .init_name = "uart1" },
41 __MEM_4K_RESOURCE(U8500_UART1_BASE),
42 .irq = {IRQ_UART1, NO_IRQ},
43};
44
45static struct amba_device uart2_device = {
46 .dev = { .init_name = "uart2" },
47 __MEM_4K_RESOURCE(U8500_UART2_BASE),
48 .irq = {IRQ_UART2, NO_IRQ},
49};
50
51static void ab4500_spi_cs_control(u32 command)
52{
53 /* set the FRM signal, which is CS - TODO */
54}
55
56struct pl022_config_chip ab4500_chip_info = {
57 .lbm = LOOPBACK_DISABLED,
58 .com_mode = INTERRUPT_TRANSFER,
59 .iface = SSP_INTERFACE_MOTOROLA_SPI,
60 /* we can act as master only */
61 .hierarchy = SSP_MASTER,
62 .slave_tx_disable = 0,
63 .endian_rx = SSP_RX_MSB,
64 .endian_tx = SSP_TX_MSB,
65 .data_size = SSP_DATA_BITS_24,
66 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
67 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
68 .clk_phase = SSP_CLK_SECOND_EDGE,
69 .clk_pol = SSP_CLK_POL_IDLE_HIGH,
70 .cs_control = ab4500_spi_cs_control,
71};
72
73static struct spi_board_info u8500_spi_devices[] = {
74 {
75 .modalias = "ab4500",
76 .controller_data = &ab4500_chip_info,
77 .max_speed_hz = 12000000,
78 .bus_num = 0,
79 .chip_select = 0,
80 .mode = SPI_MODE_0,
81 .irq = IRQ_AB4500,
82 },
83};
84
85static struct pl022_ssp_controller ssp0_platform_data = {
86 .bus_id = 0,
87 /* pl022 not yet supports dma */
88 .enable_dma = 0,
89 /* on this platform, gpio 31,142,144,214 &
90 * 224 are connected as chip selects
91 */
92 .num_chipselect = 5,
93};
94
95static struct amba_device pl022_device = {
96 .dev = {
97 .coherent_dma_mask = ~0,
98 .init_name = "pl022",
99 .platform_data = &ssp0_platform_data,
100 },
101 .res = {
102 .start = U8500_SSP0_BASE,
103 .end = U8500_SSP0_BASE + SZ_4K - 1,
104 .flags = IORESOURCE_MEM,
105 },
106 .irq = {IRQ_SSP0, NO_IRQ },
107 /* ST-Ericsson modified id */
108 .periphid = SSP_PER_ID,
109};
110
111static struct amba_device *amba_devs[] __initdata = {
112 &uart0_device,
113 &uart1_device,
114 &uart2_device,
115 &pl022_device,
116};
117
118static void __init u8500_timer_init(void)
119{
120#ifdef CONFIG_LOCAL_TIMERS
121 /* Setup the local timer base */
122 twd_base = __io_address(U8500_TWD_BASE);
123#endif
124 /* Setup the MTU base */
125 mtu_base = __io_address(U8500_MTU0_BASE);
126
127 nmdk_timer_init();
128}
129
130static struct sys_timer u8500_timer = {
131 .init = u8500_timer_init,
132};
133
134static void __init u8500_init_machine(void)
135{
136 int i;
137
138 /* Register the active AMBA devices on this board */
139 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
140 amba_device_register(amba_devs[i], &iomem_resource);
141
142 spi_register_board_info(u8500_spi_devices,
143 ARRAY_SIZE(u8500_spi_devices));
144
145 u8500_init_devices();
146}
147
148MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
149 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
150 .phys_io = U8500_UART2_BASE,
151 .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
152 .boot_params = 0x100,
153 .map_io = u8500_map_io,
154 .init_irq = u8500_init_irq,
155 /* we re-use nomadik timer here */
156 .timer = &u8500_timer,
157 .init_machine = u8500_init_machine,
158MACHINE_END
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
new file mode 100644
index 000000000000..20b6ebb6783a
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * heavily based on realview platform
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/list.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/mutex.h>
16
17#include <asm/clkdev.h>
18
19/* currently the clk structure
20 * just supports rate. This would
21 * be extended as and when new devices are
22 * added - TODO
23 */
24struct clk {
25 unsigned long rate;
26};
27
28int clk_enable(struct clk *clk)
29{
30 return 0;
31}
32EXPORT_SYMBOL(clk_enable);
33
34void clk_disable(struct clk *clk)
35{
36}
37EXPORT_SYMBOL(clk_disable);
38
39unsigned long clk_get_rate(struct clk *clk)
40{
41 return clk->rate;
42}
43EXPORT_SYMBOL(clk_get_rate);
44
45long clk_round_rate(struct clk *clk, unsigned long rate)
46{
47 /*TODO*/
48 return rate;
49}
50EXPORT_SYMBOL(clk_round_rate);
51
52int clk_set_rate(struct clk *clk, unsigned long rate)
53{
54 clk->rate = rate;
55 return 0;
56}
57EXPORT_SYMBOL(clk_set_rate);
58
59/* ssp clock */
60static struct clk ssp_clk = {
61 .rate = 48000000,
62};
63
64/* fixed clock */
65static struct clk f38_clk = {
66 .rate = 38400000,
67};
68
69static struct clk_lookup lookups[] = {
70 {
71 /* UART0 */
72 .dev_id = "uart0",
73 .clk = &f38_clk,
74 }, { /* UART1 */
75 .dev_id = "uart1",
76 .clk = &f38_clk,
77 }, { /* UART2 */
78 .dev_id = "uart2",
79 .clk = &f38_clk,
80 }, { /* SSP */
81 .dev_id = "pl022",
82 .clk = &ssp_clk,
83 }
84};
85
86static int __init clk_init(void)
87{
88 int i;
89
90 /* register the clock lookups */
91 for (i = 0; i < ARRAY_SIZE(lookups); i++)
92 clkdev_add(&lookups[i]);
93 return 0;
94}
95arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
new file mode 100644
index 000000000000..5f05e5850f71
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2008-2009 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 */
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/amba/bus.h>
15#include <linux/irq.h>
16#include <linux/platform_device.h>
17
18#include <asm/hardware/gic.h>
19#include <asm/mach/map.h>
20#include <mach/hardware.h>
21
22/* add any platform devices here - TODO */
23static struct platform_device *platform_devs[] __initdata = {
24 /* yet to be added, add i2c0, gpio.. */
25};
26
27#define __IO_DEV_DESC(x, sz) { \
28 .virtual = IO_ADDRESS(x), \
29 .pfn = __phys_to_pfn(x), \
30 .length = sz, \
31 .type = MT_DEVICE, \
32}
33
34/* minimum static i/o mapping required to boot U8500 platforms */
35static struct map_desc u8500_io_desc[] __initdata = {
36 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
37 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
38 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
39 __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
40 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
42};
43
44void __init u8500_map_io(void)
45{
46 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
47}
48
49void __init u8500_init_irq(void)
50{
51 gic_dist_init(0, __io_address(U8500_GIC_DIST_BASE), 29);
52 gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
53}
54
55/*
56 * This function is called from the board init
57 */
58void __init u8500_init_devices(void)
59{
60 /* Register the platform devices */
61 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
62
63 return ;
64}
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
new file mode 100644
index 000000000000..a6be2cdf2b2f
--- /dev/null
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -0,0 +1,38 @@
1/*
2 * Copyright (c) 2009 ST-Ericsson
3 * This file is based ARM Realview platform
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * U8500 specific entry point for secondary CPUs.
18 */
19ENTRY(u8500_secondary_startup)
20 mrc p15, 0, r0, c0, c0, 5
21 and r0, r0, #15
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 add r6, r6, r4
26 dsb
27pen: ldr r7, [r6]
28 cmp r7, r0
29 bne pen
30
31 /*
32 * we've been released from the holding pen: secondary_stack
33 * should now contain the SVC stack for this core
34 */
35 b secondary_startup
36
371: .long .
38 .long pen_release
diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
new file mode 100644
index 000000000000..8f21b6a95dce
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -0,0 +1,19 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright (C) 2009 ST-Ericsson
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @MMU enabled?
14 moveq \rx, #0x80000000 @MMU off, Physical address
15 movne \rx, #0xF0000000 @MMU on, Virtual address
16 orr \rx, \rx, #0x7000
17 .endm
18
19#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
new file mode 100644
index 000000000000..eece3301fef7
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -0,0 +1,89 @@
1/*
2 * Low-level IRQ helper macros for U8500 platforms
3 *
4 * Copyright (C) 2009 ST-Ericsson.
5 *
6 * This file is a copy of ARM Realview platform.
7 * -just satisfied checkpatch script.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <asm/hardware/gic.h>
15
16 .macro disable_fiq
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE)
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2
24 .endm
25
26 /*
27 * The interrupt numbering scheme is defined in the
28 * interrupt controller spec. To wit:
29 *
30 * Interrupts 0-15 are IPI
31 * 16-28 are reserved
32 * 29-31 are local. We allow 30 to be used for the watchdog.
33 * 32-1020 are global
34 * 1021-1022 are reserved
35 * 1023 is "spurious" (no interrupt)
36 *
37 * For now, we ignore all local interrupts so only return an
38 * interrupt if it's between 30 and 1020. The test_for_ipi
39 * routine below will pick up on IPIs.
40 *
41 * A simple read from the controller will tell us the number
42 * of the highest priority enabled interrupt. We then just
43 * need to check whether it is in the valid range for an
44 * IRQ (30-1020 inclusive).
45 */
46
47 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
48
49 /* bits 12-10 = src CPU, 9-0 = int # */
50 ldr \irqstat, [\base, #GIC_CPU_INTACK]
51
52 ldr \tmp, =1021
53
54 bic \irqnr, \irqstat, #0x1c00
55
56 cmp \irqnr, #29
57 cmpcc \irqnr, \irqnr
58 cmpne \irqnr, \tmp
59 cmpcs \irqnr, \irqnr
60
61 .endm
62
63 /* We assume that irqstat (the raw value of the IRQ
64 * acknowledge register) is preserved from the macro above.
65 * If there is an IPI, we immediately signal end of
66 * interrupt on the controller, since this requires the
67 * original irqstat value which we won't easily be able
68 * to recreate later.
69 */
70
71 .macro test_for_ipi, irqnr, irqstat, base, tmp
72 bic \irqnr, \irqstat, #0x1c00
73 cmp \irqnr, #16
74 strcc \irqstat, [\base, #GIC_CPU_EOI]
75 cmpcs \irqnr, \irqnr
76 .endm
77
78 /* As above, this assumes that irqstat and base
79 * are preserved..
80 */
81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
84 mov \tmp, #0
85 cmp \irqnr, #29
86 moveq \tmp, #1
87 streq \irqstat, [\base, #GIC_CPU_EOI]
88 cmp \tmp, #0
89 .endm
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
new file mode 100644
index 000000000000..6da650202dc7
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * U8500 hardware definitions
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10#ifndef __MACH_HARDWARE_H
11#define __MACH_HARDWARE_H
12
13/* macros to get at IO space when running virtually
14 * We dont map all the peripherals, let ioremap do
15 * this for us. We map only very basic peripherals here.
16 */
17#define U8500_IO_VIRTUAL 0xf0000000
18#define U8500_IO_PHYSICAL 0xa0000000
19
20/* this macro is used in assembly, so no cast */
21#define IO_ADDRESS(x) \
22 (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
23
24/* typesafe io address */
25#define __io_address(n) __io(IO_ADDRESS(n))
26
27/*
28 * Base address definitions for U8500 Onchip IPs. All the
29 * peripherals are contained in a single 1 Mbyte region, with
30 * AHB peripherals at the bottom and APB peripherals at the
31 * top of the region. PER stands for PERIPHERAL region which
32 * itself divided into sub regions.
33 */
34#define U8500_PER3_BASE 0x80000000
35#define U8500_PER2_BASE 0x80110000
36#define U8500_PER1_BASE 0x80120000
37#define U8500_PER4_BASE 0x80150000
38
39#define U8500_PER6_BASE 0xa03c0000
40#define U8500_PER5_BASE 0xa03e0000
41#define U8500_PER7_BASE 0xa03d0000
42
43#define U8500_SVA_BASE 0xa0100000
44#define U8500_SIA_BASE 0xa0200000
45
46#define U8500_SGA_BASE 0xa0300000
47#define U8500_MCDE_BASE 0xa0350000
48#define U8500_DMA_BASE 0xa0362000
49
50#define U8500_SCU_BASE 0xa0410000
51#define U8500_GIC_CPU_BASE 0xa0410100
52#define U8500_TWD_BASE 0xa0410600
53#define U8500_GIC_DIST_BASE 0xa0411000
54#define U8500_L2CC_BASE 0xa0412000
55
56#define U8500_TWD_SIZE 0x100
57
58/* per7 base addressess */
59#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
60#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
61#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
62#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
63#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
64
65/* per6 base addressess */
66#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
67#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
68#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
69#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
70#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
71#define U8500_CLKRST6_BASE (U8500_PER7_BASE + 0xf000)
72
73/* per5 base addressess */
74#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
75#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
76#define U8500_CLKRST5_BASE (U8500_PER7_BASE + 0x1f000)
77
78/* per4 base addressess */
79#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
80#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
81#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
82#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
83#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
84#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
85#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
86#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
87
88/* per3 base addressess */
89#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
90#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
91#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
92#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
93#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
94#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
95#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
96#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
97#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
98#define U8500_CLKRST3_BASE (U8500_PER7_BASE + 0xf000)
99
100/* per2 base addressess */
101#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
102#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
103#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
104#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
105#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
106#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
107#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
108#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
109#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
110#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
111#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
112#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
113#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
114
115/* per1 base addresses */
116#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
117#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
118#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
119#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
120#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
121#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
122#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
123#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
124#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
125#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
126#define U8500_CLKRST1_BASE (U8500_PER2_BASE + 0xf000)
127
128/* ST-Ericsson modified pl022 id */
129#define SSP_PER_ID 0x01080022
130
131#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
new file mode 100644
index 000000000000..1cf3f44ce5b2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-u8500/include/mach/io.h
3 *
4 * Copyright (C) 1997-1999 Russell King
5 *
6 * Modifications:
7 * 06-12-1997 RMK Created.
8 * 07-04-1999 RMK Major cleanup
9 */
10#ifndef __ASM_ARM_ARCH_IO_H
11#define __ASM_ARM_ARCH_IO_H
12
13#define IO_SPACE_LIMIT 0xffffffff
14
15/*
16 * We don't actually have real ISA nor PCI buses, but there is so many
17 * drivers out there that might just work if we fake them...
18 */
19#define __io(a) __typesafe_io(a)
20#define __mem_pci(a) (a)
21
22#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
new file mode 100644
index 000000000000..394b5dd2200f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2008 STMicroelectronics
3 * Copyright (C) 2009 ST-Ericsson.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#ifndef ASM_ARCH_IRQS_H
11#define ASM_ARCH_IRQS_H
12
13#include <mach/hardware.h>
14
15#define IRQ_LOCALTIMER 29
16#define IRQ_LOCALWDOG 30
17
18/* Shared Peripheral Interrupt (SHPI) */
19#define IRQ_SHPI_START 32
20
21/* Interrupt numbers generic for shared peripheral */
22#define IRQ_MTU0 (IRQ_SHPI_START + 4)
23#define IRQ_SPI2 (IRQ_SHPI_START + 6)
24#define IRQ_SPI0 (IRQ_SHPI_START + 8)
25#define IRQ_UART0 (IRQ_SHPI_START + 11)
26#define IRQ_I2C3 (IRQ_SHPI_START + 12)
27#define IRQ_SSP0 (IRQ_SHPI_START + 14)
28#define IRQ_MTU1 (IRQ_SHPI_START + 17)
29#define IRQ_RTC_RTT (IRQ_SHPI_START + 18)
30#define IRQ_UART1 (IRQ_SHPI_START + 19)
31#define IRQ_I2C0 (IRQ_SHPI_START + 21)
32#define IRQ_I2C1 (IRQ_SHPI_START + 22)
33#define IRQ_USBOTG (IRQ_SHPI_START + 23)
34#define IRQ_DMA (IRQ_SHPI_START + 25)
35#define IRQ_UART2 (IRQ_SHPI_START + 26)
36#define IRQ_HSIR_EXCEP (IRQ_SHPI_START + 29)
37#define IRQ_MSP0 (IRQ_SHPI_START + 31)
38#define IRQ_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32)
39#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
40#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
41#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
42#define IRQ_AB4500 (IRQ_SHPI_START + 40)
43#define IRQ_DISP (IRQ_SHPI_START + 48)
44#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
45#define IRQ_SSP1 (IRQ_SHPI_START + 52)
46#define IRQ_I2C2 (IRQ_SHPI_START + 55)
47#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
48#define IRQ_MSP1 (IRQ_SHPI_START + 62)
49#define IRQ_SPI1 (IRQ_SHPI_START + 96)
50#define IRQ_MSP2 (IRQ_SHPI_START + 98)
51#define IRQ_SDMMC4 (IRQ_SHPI_START + 99)
52#define IRQ_HSIRD0 (IRQ_SHPI_START + 104)
53#define IRQ_HSIRD1 (IRQ_SHPI_START + 105)
54#define IRQ_HSITD0 (IRQ_SHPI_START + 106)
55#define IRQ_HSITD1 (IRQ_SHPI_START + 107)
56#define IRQ_GPIO0 (IRQ_SHPI_START + 119)
57#define IRQ_GPIO1 (IRQ_SHPI_START + 120)
58#define IRQ_GPIO2 (IRQ_SHPI_START + 121)
59#define IRQ_GPIO3 (IRQ_SHPI_START + 122)
60#define IRQ_GPIO4 (IRQ_SHPI_START + 123)
61#define IRQ_GPIO5 (IRQ_SHPI_START + 124)
62#define IRQ_GPIO6 (IRQ_SHPI_START + 125)
63#define IRQ_GPIO7 (IRQ_SHPI_START + 126)
64#define IRQ_GPIO8 (IRQ_SHPI_START + 127)
65
66/* There are 128 shared peripheral interrupts assigned to
67 * INTID[160:32]. The first 32 interrupts are reserved.
68 */
69#define NR_IRQS 161
70
71#endif /*ASM_ARCH_IRQS_H*/
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
new file mode 100644
index 000000000000..510571a59e25
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/memory.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12/*
13 * Physical DRAM offset.
14 */
15#define PHYS_OFFSET UL(0x00000000)
16#define BUS_OFFSET UL(0x00000000)
17
18#endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
new file mode 100644
index 000000000000..cf0ce1687f24
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * These symbols are needed for board-specific files to call their
9 * own cpu-specific files
10 */
11#ifndef __ASM_ARCH_SETUP_H
12#define __ASM_ARCH_SETUP_H
13
14#include <asm/mach/time.h>
15#include <linux/init.h>
16
17extern void u8500_map_io(void);
18extern void u8500_init_devices(void);
19extern void u8500_init_irq(void);
20/* We re-use nomadik_timer for this platform */
21extern void nmdk_timer_init(void);
22
23#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
new file mode 100644
index 000000000000..b59f7bc9725d
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -0,0 +1,32 @@
1/*
2 * This file is based ARM realview platform.
3 * Copyright (C) ARM Limited.
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9#ifndef ASMARM_ARCH_SMP_H
10#define ASMARM_ARCH_SMP_H
11
12#include <asm/hardware/gic.h>
13
14/* This is required to wakeup the secondary core */
15extern void u8500_secondary_startup(void);
16
17#define hard_smp_processor_id() \
18 ({ \
19 unsigned int cpunum; \
20 __asm__("mrc p15, 0, %0, c0, c0, 5" \
21 : "=r" (cpunum)); \
22 cpunum &= 0x0F; \
23 })
24
25/*
26 * We use IRQ1 as the IPI
27 */
28static inline void smp_cross_call(const struct cpumask *mask)
29{
30 gic_raise_softirq(mask, 1);
31}
32#endif
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
new file mode 100644
index 000000000000..c0cd8006f1a2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/system.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson.
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8#ifndef __ASM_ARCH_SYSTEM_H
9#define __ASM_ARCH_SYSTEM_H
10
11static inline void arch_idle(void)
12{
13 /*
14 * This should do all the clock switching
15 * and wait for interrupt tricks
16 */
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode, const char *cmd)
21{
22 /* yet to be implemented - TODO */
23}
24
25#endif
diff --git a/arch/arm/mach-ux500/include/mach/timex.h b/arch/arm/mach-ux500/include/mach/timex.h
new file mode 100644
index 000000000000..d0942c174018
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/timex.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_TIMEX_H
2#define __ASM_ARCH_TIMEX_H
3
4#define CLOCK_TICK_RATE 110000000
5
6#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
new file mode 100644
index 000000000000..8552eb188b50
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -0,0 +1,58 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef __ASM_ARCH_UNCOMPRESS_H
19#define __ASM_ARCH_UNCOMPRESS_H
20
21#include <asm/setup.h>
22#include <linux/io.h>
23#include <mach/hardware.h>
24
25#define U8500_UART_DR 0x80007000
26#define U8500_UART_LCRH 0x8000702c
27#define U8500_UART_CR 0x80007030
28#define U8500_UART_FR 0x80007018
29
30static void putc(const char c)
31{
32 /* Do nothing if the UART is not enabled. */
33 if (!(readb(U8500_UART_CR) & 0x1))
34 return;
35
36 if (c == '\n')
37 putc('\r');
38
39 while (readb(U8500_UART_FR) & (1 << 5))
40 barrier();
41 writeb(c, U8500_UART_DR);
42}
43
44static void flush(void)
45{
46 if (!(readb(U8500_UART_CR) & 0x1))
47 return;
48 while (readb(U8500_UART_FR) & (1 << 3))
49 barrier();
50}
51
52static inline void arch_decomp_setup(void)
53{
54}
55
56#define arch_decomp_wdog() /* nothing to do here */
57
58#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
new file mode 100644
index 000000000000..86cdbbce1842
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#define VMALLOC_END 0xf0000000
diff --git a/arch/arm/mach-ux500/localtimer.c b/arch/arm/mach-ux500/localtimer.c
new file mode 100644
index 000000000000..2288f6a7c518
--- /dev/null
+++ b/arch/arm/mach-ux500/localtimer.c
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2008-2009 ST-Ericsson
3 * Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
4 *
5 * This file is heavily based on relaview platform, almost a copy.
6 *
7 * Copyright (C) 2002 ARM Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/clockchips.h>
16
17#include <asm/irq.h>
18#include <asm/smp_twd.h>
19#include <asm/localtimer.h>
20
21/*
22 * Setup the local clock events for a CPU.
23 */
24void __cpuinit local_timer_setup(struct clock_event_device *evt)
25{
26 evt->irq = IRQ_LOCALTIMER;
27 twd_timer_setup(evt);
28}
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
new file mode 100644
index 000000000000..8dfe7ca245d8
--- /dev/null
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 *
7 * This file is based on arm realview platform
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/init.h>
14#include <linux/errno.h>
15#include <linux/delay.h>
16#include <linux/device.h>
17#include <linux/smp.h>
18#include <linux/io.h>
19
20#include <asm/cacheflush.h>
21#include <asm/localtimer.h>
22#include <asm/smp_scu.h>
23#include <mach/hardware.h>
24
25/*
26 * control for which core is the next to come out of the secondary
27 * boot "holding pen"
28 */
29volatile int __cpuinitdata pen_release = -1;
30
31static unsigned int __init get_core_count(void)
32{
33 return scu_get_core_count(__io_address(U8500_SCU_BASE));
34}
35
36static DEFINE_SPINLOCK(boot_lock);
37
38void __cpuinit platform_secondary_init(unsigned int cpu)
39{
40 trace_hardirqs_off();
41
42 /*
43 * if any interrupts are already enabled for the primary
44 * core (e.g. timer irq), then they will not have been enabled
45 * for us: do so
46 */
47 gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE));
48
49 /*
50 * let the primary processor know we're out of the
51 * pen, then head off into the C entry point
52 */
53 pen_release = -1;
54
55 /*
56 * Synchronise with the boot thread.
57 */
58 spin_lock(&boot_lock);
59 spin_unlock(&boot_lock);
60}
61
62int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
63{
64 unsigned long timeout;
65
66 /*
67 * set synchronisation state between this boot processor
68 * and the secondary one
69 */
70 spin_lock(&boot_lock);
71
72 /*
73 * The secondary processor is waiting to be released from
74 * the holding pen - release it, then wait for it to flag
75 * that it has been released by resetting pen_release.
76 */
77 pen_release = cpu;
78 flush_cache_all();
79
80 timeout = jiffies + (1 * HZ);
81 while (time_before(jiffies, timeout)) {
82 if (pen_release == -1)
83 break;
84 }
85
86 /*
87 * now the secondary core is starting up let it run its
88 * calibrations, then wait for it to finish
89 */
90 spin_unlock(&boot_lock);
91
92 return pen_release != -1 ? -ENOSYS : 0;
93}
94
95static void __init wakeup_secondary(void)
96{
97 /* nobody is to be released from the pen yet */
98 pen_release = -1;
99
100 /*
101 * write the address of secondary startup into the backup ram register
102 * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
103 * backup ram register at offset 0x1FF0, which is what boot rom code
104 * is waiting for. This would wake up the secondary core from WFE
105 */
106#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
107 __raw_writel(virt_to_phys(u8500_secondary_startup),
108 (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
109 U8500_CPU1_JUMPADDR_OFFSET);
110
111#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
112 __raw_writel(0xA1FEED01,
113 (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) +
114 U8500_CPU1_WAKEMAGIC_OFFSET);
115
116 /* make sure write buffer is drained */
117 mb();
118}
119
120/*
121 * Initialise the CPU possible map early - this describes the CPUs
122 * which may be present or become present in the system.
123 */
124void __init smp_init_cpus(void)
125{
126 unsigned int i, ncores = get_core_count();
127
128 for (i = 0; i < ncores; i++)
129 set_cpu_possible(i, true);
130}
131
132void __init smp_prepare_cpus(unsigned int max_cpus)
133{
134 unsigned int ncores = get_core_count();
135 unsigned int cpu = smp_processor_id();
136 int i;
137
138 /* sanity check */
139 if (ncores == 0) {
140 printk(KERN_ERR
141 "U8500: strange CM count of 0? Default to 1\n");
142 ncores = 1;
143 }
144
145 if (ncores > num_possible_cpus()) {
146 printk(KERN_WARNING
147 "U8500: no. of cores (%d) greater than configured "
148 "maximum of %d - clipping\n",
149 ncores, num_possible_cpus());
150 ncores = num_possible_cpus();
151 }
152
153 smp_store_cpu_info(cpu);
154
155 /*
156 * are we trying to boot more cores than exist?
157 */
158 if (max_cpus > ncores)
159 max_cpus = ncores;
160
161 /*
162 * Initialise the present map, which describes the set of CPUs
163 * actually populated at the present time.
164 */
165 for (i = 0; i < max_cpus; i++)
166 set_cpu_present(i, true);
167
168 if (max_cpus > 1) {
169 /*
170 * Enable the local timer or broadcast device for the
171 * boot CPU, but only if we have more than one CPU.
172 */
173 percpu_timer_setup();
174 scu_enable(__io_address(U8500_SCU_BASE));
175 wakeup_secondary();
176 }
177}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 00:26:59 -0500