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-rw-r--r--arch/arm/mach-ux500/Kconfig25
-rw-r--r--arch/arm/mach-ux500/Makefile5
-rw-r--r--arch/arm/mach-ux500/board-u5500-sdi.c74
-rw-r--r--arch/arm/mach-ux500/board-u5500.c162
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c4
-rw-r--r--arch/arm/mach-ux500/clock.c12
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c247
-rw-r--r--arch/arm/mach-ux500/cpu.c8
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h99
-rw-r--r--arch/arm/mach-ux500/dma-db5500.c137
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h143
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h113
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox-db5500.h88
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-ux500/mbox-db5500.c565
-rw-r--r--arch/arm/mach-ux500/modem-irq-db5500.c143
-rw-r--r--arch/arm/mach-ux500/pins-db5500.h620
-rw-r--r--arch/arm/mach-ux500/platsmp.c8
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db5500.h135
-rw-r--r--arch/arm/mach-ux500/timer.c13
26 files changed, 11 insertions, 2635 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index ef7099eea0f2..0e8470a3fbeb 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -10,10 +10,6 @@ config UX500_SOC_COMMON
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369
11 select CACHE_L2X0 11 select CACHE_L2X0
12 12
13config UX500_SOC_DB5500
14 bool
15 select MFD_DB5500_PRCMU
16
17config UX500_SOC_DB8500 13config UX500_SOC_DB8500
18 bool 14 bool
19 select MFD_DB8500_PRCMU 15 select MFD_DB8500_PRCMU
@@ -45,15 +41,8 @@ config MACH_SNOWBALL
45 help 41 help
46 Include support for the snowball development platform. 42 Include support for the snowball development platform.
47 43
48config MACH_U5500
49 bool "U5500 Development platform"
50 select UX500_SOC_DB5500
51 help
52 Include support for the U5500 development platform.
53
54config UX500_AUTO_PLATFORM 44config UX500_AUTO_PLATFORM
55 def_bool y 45 def_bool y
56 depends on !MACH_U5500
57 select MACH_MOP500 46 select MACH_MOP500
58 help 47 help
59 At least one platform needs to be selected in order to build 48 At least one platform needs to be selected in order to build
@@ -74,18 +63,4 @@ config UX500_DEBUG_UART
74 Choose the UART on which kernel low-level debug messages should be 63 Choose the UART on which kernel low-level debug messages should be
75 output. 64 output.
76 65
77config U5500_MODEM_IRQ
78 bool "Modem IRQ support"
79 depends on UX500_SOC_DB5500
80 default y
81 help
82 Add support for handling IRQ:s from modem side
83
84config U5500_MBOX
85 bool "Mailbox support"
86 depends on U5500_MODEM_IRQ
87 default y
88 help
89 Add support for U5500 mailbox communication with modem side
90
91endif 66endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 465b9ec9510a..fc7db5df970b 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,16 +5,11 @@
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o usb.o timer.o 6 id.o usb.o timer.o
7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
8obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
9obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
10obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ 9obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
11 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
12 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
13 board-mop500-u8500uib.o \ 12 board-mop500-u8500uib.o \
14 board-mop500-pins.o 13 board-mop500-pins.o
15obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o
16obj-$(CONFIG_SMP) += platsmp.o headsmp.o 14obj-$(CONFIG_SMP) += platsmp.o headsmp.o
17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 15obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
20
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
deleted file mode 100644
index 836112eedde7..000000000000
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/amba/mmci.h>
9#include <linux/mmc/host.h>
10
11#include <plat/pincfg.h>
12#include <plat/gpio-nomadik.h>
13#include <mach/db5500-regs.h>
14#include <plat/ste_dma40.h>
15
16#include "pins-db5500.h"
17#include "devices-db5500.h"
18#include "ste-dma40-db5500.h"
19
20static pin_cfg_t u5500_sdi_pins[] = {
21 /* SDI0 (POP eMMC) */
22 GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP,
23 GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP,
24 GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP,
25 GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP,
26 GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP,
27 GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP,
28 GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP,
29 GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP,
30 GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP,
31 GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW,
32};
33
34#ifdef CONFIG_STE_DMA40
35struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM,
38 .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42};
43
44static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
48 .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51};
52#endif
53
54static struct mmci_platform_data u5500_sdi0_data = {
55 .ocr_mask = MMC_VDD_165_195,
56 .f_max = 50000000,
57 .capabilities = MMC_CAP_4_BIT_DATA |
58 MMC_CAP_8_BIT_DATA |
59 MMC_CAP_MMC_HIGHSPEED,
60 .gpio_cd = -1,
61 .gpio_wp = -1,
62#ifdef CONFIG_STE_DMA40
63 .dma_filter = stedma40_filter,
64 .dma_rx_param = &u5500_sdi0_dma_cfg_rx,
65 .dma_tx_param = &u5500_sdi0_dma_cfg_tx,
66#endif
67};
68
69void __init u5500_sdi_init(struct device *parent)
70{
71 nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
72
73 db5500_add_sdi0(parent, &u5500_sdi0_data);
74}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
deleted file mode 100644
index 0ff4be72a809..000000000000
--- a/arch/arm/mach-ux500/board-u5500.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/amba/bus.h>
11#include <linux/irq.h>
12#include <linux/i2c.h>
13#include <linux/mfd/abx500/ab5500.h>
14
15#include <asm/hardware/gic.h>
16#include <asm/mach/arch.h>
17#include <asm/mach-types.h>
18
19#include <plat/pincfg.h>
20#include <plat/i2c.h>
21#include <plat/gpio-nomadik.h>
22
23#include <mach/hardware.h>
24#include <mach/devices.h>
25#include <mach/setup.h>
26
27#include "pins-db5500.h"
28#include "devices-db5500.h"
29#include <linux/led-lm3530.h>
30
31/*
32 * GPIO
33 */
34
35static pin_cfg_t u5500_pins[] = {
36 /* I2C */
37 GPIO218_I2C2_SCL | PIN_INPUT_PULLUP,
38 GPIO219_I2C2_SDA | PIN_INPUT_PULLUP,
39
40 /* DISPLAY_ENABLE */
41 GPIO226_GPIO | PIN_OUTPUT_LOW,
42
43 /* Backlight Enbale */
44 GPIO224_GPIO | PIN_OUTPUT_HIGH,
45};
46/*
47 * I2C
48 */
49
50#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
51static struct nmk_i2c_controller u5500_i2c##id##_data = { \
52 /* \
53 * slave data setup time, which is \
54 * 250 ns,100ns,10ns which is 14,6,2 \
55 * respectively for a 48 Mhz \
56 * i2c clock \
57 */ \
58 .slsu = _slsu, \
59 /* Tx FIFO threshold */ \
60 .tft = _tft, \
61 /* Rx FIFO threshold */ \
62 .rft = _rft, \
63 /* std. mode operation */ \
64 .clk_freq = clk, \
65 .sm = _sm, \
66}
67/*
68 * The board uses TODO <3> i2c controllers, initialize all of
69 * them with slave data setup time of 250 ns,
70 * Tx & Rx FIFO threshold values as 1 and standard
71 * mode of operation
72 */
73
74U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST);
75
76static struct lm3530_platform_data u5500_als_platform_data = {
77 .mode = LM3530_BL_MODE_MANUAL,
78 .als_input_mode = LM3530_INPUT_ALS1,
79 .max_current = LM3530_FS_CURR_26mA,
80 .pwm_pol_hi = true,
81 .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms,
82 .brt_ramp_law = 1, /* Linear */
83 .brt_ramp_fall = LM3530_RAMP_TIME_8s,
84 .brt_ramp_rise = LM3530_RAMP_TIME_8s,
85 .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm,
86 .als2_resistor_sel = LM3530_ALS_IMPD_Z,
87 .als_vmin = 730, /* mV */
88 .als_vmax = 1020, /* mV */
89 .brt_val = 0x7F, /* Max brightness */
90};
91
92static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
93 {
94 /* Backlight */
95 I2C_BOARD_INFO("lm3530-led", 0x36),
96 .platform_data = &u5500_als_platform_data,
97 },
98};
99
100static void __init u5500_i2c_init(struct device *parent)
101{
102 db5500_add_i2c2(parent, &u5500_i2c2_data);
103 i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
104}
105
106static struct ab5500_platform_data ab5500_plf_data = {
107 .irq = {
108 .base = 0,
109 .count = 0,
110 },
111 .init_settings = NULL,
112 .init_settings_sz = 0,
113 .pm_power_off = false,
114};
115
116static struct platform_device ab5500_device = {
117 .name = "ab5500-core",
118 .id = 0,
119 .dev = {
120 .platform_data = &ab5500_plf_data,
121 },
122 .num_resources = 0,
123};
124
125static struct platform_device *u5500_platform_devices[] __initdata = {
126 &ab5500_device,
127};
128
129static void __init u5500_uart_init(struct device *parent)
130{
131 db5500_add_uart0(parent, NULL);
132 db5500_add_uart1(parent, NULL);
133 db5500_add_uart2(parent, NULL);
134}
135
136static void __init u5500_init_machine(void)
137{
138 struct device *parent = NULL;
139 int i;
140
141 parent = u5500_init_devices();
142 nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
143
144 u5500_i2c_init(parent);
145 u5500_sdi_init(parent);
146 u5500_uart_init(parent);
147
148 for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
149 u5500_platform_devices[i]->dev.parent = parent;
150
151 platform_add_devices(u5500_platform_devices,
152 ARRAY_SIZE(u5500_platform_devices));
153}
154
155MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
156 .atag_offset = 0x100,
157 .map_io = u5500_map_io,
158 .init_irq = ux500_init_irq,
159 .timer = &ux500_timer,
160 .handle_irq = gic_handle_irq,
161 .init_machine = u5500_init_machine,
162MACHINE_END
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 77a75ed0df67..df91344aa2db 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -36,9 +36,7 @@ static int __init ux500_l2x0_unlock(void)
36 36
37static int __init ux500_l2x0_init(void) 37static int __init ux500_l2x0_init(void)
38{ 38{
39 if (cpu_is_u5500()) 39 if (cpu_is_u8500())
40 l2x0_base = __io_address(U5500_L2CC_BASE);
41 else if (cpu_is_u8500())
42 l2x0_base = __io_address(U8500_L2CC_BASE); 40 l2x0_base = __io_address(U8500_L2CC_BASE);
43 else 41 else
44 ux500_unknown_soc(); 42 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index ec35f0aa5665..9feb6bc7f20e 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
149 unsigned long mturate; 149 unsigned long mturate;
150 unsigned long retclk; 150 unsigned long retclk;
151 151
152 if (cpu_is_u5500()) 152 if (cpu_is_u8500())
153 addr = __io_address(U5500_PRCMU_BASE);
154 else if (cpu_is_u8500())
155 addr = __io_address(U8500_PRCMU_BASE); 153 addr = __io_address(U8500_PRCMU_BASE);
156 else 154 else
157 ux500_unknown_soc(); 155 ux500_unknown_soc();
@@ -705,14 +703,6 @@ late_initcall(clk_init_smp_twd_cpufreq);
705 703
706int __init clk_init(void) 704int __init clk_init(void)
707{ 705{
708 if (cpu_is_u5500()) {
709 /* Clock tree for U5500 not implemented yet */
710 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
711 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
712 clk_uartclk.rate = 36360000;
713 clk_sdmmcclk.rate = 99900000;
714 }
715
716 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); 706 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
717 clkdev_add(&clk_smp_twd_lookup); 707 clkdev_add(&clk_smp_twd_lookup);
718 708
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
deleted file mode 100644
index bca47f32082f..000000000000
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/amba/bus.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12
13#include <asm/mach/map.h>
14#include <asm/pmu.h>
15
16#include <plat/gpio-nomadik.h>
17
18#include <mach/hardware.h>
19#include <mach/devices.h>
20#include <mach/setup.h>
21#include <mach/irqs.h>
22#include <mach/usb.h>
23
24#include "devices-db5500.h"
25#include "ste-dma40-db5500.h"
26
27static struct map_desc u5500_uart_io_desc[] __initdata = {
28 __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
29 __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K),
30};
31
32static struct map_desc u5500_io_desc[] __initdata = {
33 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
34 __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K),
35 __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K),
36 __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K),
37 __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K),
38 __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K),
39
40 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
41 __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
42 __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
43 __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
44 __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
45 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
46 __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
47};
48
49static struct resource mbox0_resources[] = {
50 {
51 .name = "mbox_peer",
52 .start = U5500_MBOX0_PEER_START,
53 .end = U5500_MBOX0_PEER_END,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .name = "mbox_local",
58 .start = U5500_MBOX0_LOCAL_START,
59 .end = U5500_MBOX0_LOCAL_END,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "mbox_irq",
64 .start = MBOX_PAIR0_VIRT_IRQ,
65 .end = MBOX_PAIR0_VIRT_IRQ,
66 .flags = IORESOURCE_IRQ,
67 }
68};
69
70static struct resource mbox1_resources[] = {
71 {
72 .name = "mbox_peer",
73 .start = U5500_MBOX1_PEER_START,
74 .end = U5500_MBOX1_PEER_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .name = "mbox_local",
79 .start = U5500_MBOX1_LOCAL_START,
80 .end = U5500_MBOX1_LOCAL_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .name = "mbox_irq",
85 .start = MBOX_PAIR1_VIRT_IRQ,
86 .end = MBOX_PAIR1_VIRT_IRQ,
87 .flags = IORESOURCE_IRQ,
88 }
89};
90
91static struct resource mbox2_resources[] = {
92 {
93 .name = "mbox_peer",
94 .start = U5500_MBOX2_PEER_START,
95 .end = U5500_MBOX2_PEER_END,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .name = "mbox_local",
100 .start = U5500_MBOX2_LOCAL_START,
101 .end = U5500_MBOX2_LOCAL_END,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .name = "mbox_irq",
106 .start = MBOX_PAIR2_VIRT_IRQ,
107 .end = MBOX_PAIR2_VIRT_IRQ,
108 .flags = IORESOURCE_IRQ,
109 }
110};
111
112static struct platform_device mbox0_device = {
113 .id = 0,
114 .name = "mbox",
115 .resource = mbox0_resources,
116 .num_resources = ARRAY_SIZE(mbox0_resources),
117};
118
119static struct platform_device mbox1_device = {
120 .id = 1,
121 .name = "mbox",
122 .resource = mbox1_resources,
123 .num_resources = ARRAY_SIZE(mbox1_resources),
124};
125
126static struct platform_device mbox2_device = {
127 .id = 2,
128 .name = "mbox",
129 .resource = mbox2_resources,
130 .num_resources = ARRAY_SIZE(mbox2_resources),
131};
132
133static struct platform_device *db5500_platform_devs[] __initdata = {
134 &mbox0_device,
135 &mbox1_device,
136 &mbox2_device,
137};
138
139static resource_size_t __initdata db5500_gpio_base[] = {
140 U5500_GPIOBANK0_BASE,
141 U5500_GPIOBANK1_BASE,
142 U5500_GPIOBANK2_BASE,
143 U5500_GPIOBANK3_BASE,
144 U5500_GPIOBANK4_BASE,
145 U5500_GPIOBANK5_BASE,
146 U5500_GPIOBANK6_BASE,
147 U5500_GPIOBANK7_BASE,
148};
149
150static void __init db5500_add_gpios(struct device *parent)
151{
152 struct nmk_gpio_platform_data pdata = {
153 /* No custom data yet */
154 };
155
156 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
157 IRQ_DB5500_GPIO0, &pdata);
158}
159
160void __init u5500_map_io(void)
161{
162 /*
163 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
164 */
165 iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc));
166
167 ux500_map_io();
168
169 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
170
171 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
172}
173
174static void __init db5500_pmu_init(void)
175{
176 struct resource res[] = {
177 [0] = {
178 .start = IRQ_DB5500_PMU0,
179 .end = IRQ_DB5500_PMU0,
180 .flags = IORESOURCE_IRQ,
181 },
182 [1] = {
183 .start = IRQ_DB5500_PMU1,
184 .end = IRQ_DB5500_PMU1,
185 .flags = IORESOURCE_IRQ,
186 },
187 };
188
189 platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
190 res, ARRAY_SIZE(res));
191}
192
193static int usb_db5500_rx_dma_cfg[] = {
194 DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
195 DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
196 DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
197 DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
198 DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
199 DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
200 DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
201 DB5500_DMA_DEV38_USB_OTG_IEP_8
202};
203
204static int usb_db5500_tx_dma_cfg[] = {
205 DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
206 DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
207 DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
208 DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
209 DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
210 DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
211 DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
212 DB5500_DMA_DEV38_USB_OTG_OEP_8
213};
214
215static const char *db5500_read_soc_id(void)
216{
217 return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
218}
219
220static struct device * __init db5500_soc_device_init(void)
221{
222 const char *soc_id = db5500_read_soc_id();
223
224 return ux500_soc_device_init(soc_id);
225}
226
227struct device * __init u5500_init_devices(void)
228{
229 struct device *parent;
230 int i;
231
232 parent = db5500_soc_device_init();
233
234 db5500_add_gpios(parent);
235 db5500_pmu_init();
236 db5500_dma_init(parent);
237 db5500_add_rtc(parent);
238 db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
239
240 for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
241 db5500_platform_devs[i]->dev.parent = parent;
242
243 platform_add_devices(db5500_platform_devs,
244 ARRAY_SIZE(db5500_platform_devs));
245
246 return parent;
247}
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d11f3892a27d..4b4e59b30d81 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,7 +10,6 @@
10#include <linux/io.h> 10#include <linux/io.h>
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/mfd/db8500-prcmu.h> 12#include <linux/mfd/db8500-prcmu.h>
13#include <linux/mfd/db5500-prcmu.h>
14#include <linux/clksrc-dbx500-prcmu.h> 13#include <linux/clksrc-dbx500-prcmu.h>
15#include <linux/sys_soc.h> 14#include <linux/sys_soc.h>
16#include <linux/err.h> 15#include <linux/err.h>
@@ -40,10 +39,7 @@ void __init ux500_init_irq(void)
40 void __iomem *dist_base; 39 void __iomem *dist_base;
41 void __iomem *cpu_base; 40 void __iomem *cpu_base;
42 41
43 if (cpu_is_u5500()) { 42 if (cpu_is_u8500()) {
44 dist_base = __io_address(U5500_GIC_DIST_BASE);
45 cpu_base = __io_address(U5500_GIC_CPU_BASE);
46 } else if (cpu_is_u8500()) {
47 dist_base = __io_address(U8500_GIC_DIST_BASE); 43 dist_base = __io_address(U8500_GIC_DIST_BASE);
48 cpu_base = __io_address(U8500_GIC_CPU_BASE); 44 cpu_base = __io_address(U8500_GIC_CPU_BASE);
49 } else 45 } else
@@ -60,8 +56,6 @@ void __init ux500_init_irq(void)
60 * Init clocks here so that they are available for system timer 56 * Init clocks here so that they are available for system timer
61 * initialization. 57 * initialization.
62 */ 58 */
63 if (cpu_is_u5500())
64 db5500_prcmu_early_init();
65 if (cpu_is_u8500()) 59 if (cpu_is_u8500())
66 db8500_prcmu_early_init(); 60 db8500_prcmu_early_init();
67 clk_init(); 61 clk_init();
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
deleted file mode 100644
index e70955502c35..000000000000
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __DEVICES_DB5500_H
9#define __DEVICES_DB5500_H
10
11#include "devices-common.h"
12
13#define db5500_add_i2c1(parent, pdata) \
14 dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
15#define db5500_add_i2c2(parent, pdata) \
16 dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
17#define db5500_add_i2c3(parent, pdata) \
18 dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
19
20#define db5500_add_msp0_spi(parent, pdata) \
21 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
22 IRQ_DB5500_MSP0, pdata)
23#define db5500_add_msp1_spi(parent, pdata) \
24 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
25 IRQ_DB5500_MSP1, pdata)
26#define db5500_add_msp2_spi(parent, pdata) \
27 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
28 IRQ_DB5500_MSP2, pdata)
29
30#define db5500_add_msp0_spi(parent, pdata) \
31 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
32 IRQ_DB5500_MSP0, pdata)
33#define db5500_add_msp1_spi(parent, pdata) \
34 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
35 IRQ_DB5500_MSP1, pdata)
36#define db5500_add_msp2_spi(parent, pdata) \
37 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
38 IRQ_DB5500_MSP2, pdata)
39
40#define db5500_add_rtc(parent) \
41 dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC);
42
43#define db5500_add_usb(parent, rx_cfg, tx_cfg) \
44 ux500_add_usb(parent, U5500_USBOTG_BASE, \
45 IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
46
47#define db5500_add_sdi0(parent, pdata) \
48 dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \
49 IRQ_DB5500_SDMMC0, pdata, \
50 0x10480180)
51#define db5500_add_sdi1(parent, pdata) \
52 dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \
53 IRQ_DB5500_SDMMC1, pdata, \
54 0x10480180)
55#define db5500_add_sdi2(parent, pdata) \
56 dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \
57 IRQ_DB5500_SDMMC2, pdata \
58 0x10480180)
59#define db5500_add_sdi3(parent, pdata) \
60 dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \
61 IRQ_DB5500_SDMMC3, pdata \
62 0x10480180)
63#define db5500_add_sdi4(parent, pdata) \
64 dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \
65 IRQ_DB5500_SDMMC4, pdata \
66 0x10480180)
67
68/* This one has a bad peripheral ID in the U5500 silicon */
69#define db5500_add_spi0(parent, pdata) \
70 dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \
71 IRQ_DB5500_SPI0, pdata, \
72 0x10080023)
73#define db5500_add_spi1(parent, pdata) \
74 dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \
75 IRQ_DB5500_SPI1, pdata, \
76 0x10080023)
77#define db5500_add_spi2(parent, pdata) \
78 dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \
79 IRQ_DB5500_SPI2, pdata \
80 0x10080023)
81#define db5500_add_spi3(parent, pdata) \
82 dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \
83 IRQ_DB5500_SPI3, pdata \
84 0x10080023)
85
86#define db5500_add_uart0(parent, plat) \
87 dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \
88 IRQ_DB5500_UART0, plat)
89#define db5500_add_uart1(parent, plat) \
90 dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \
91 IRQ_DB5500_UART1, plat)
92#define db5500_add_uart2(parent, plat) \
93 dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \
94 IRQ_DB5500_UART2, plat)
95#define db5500_add_uart3(parent, plat) \
96 dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \
97 IRQ_DB5500_UART3, plat)
98
99#endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
deleted file mode 100644
index 41e9470fa0e6..000000000000
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
7 *
8 * License terms: GNU General Public License (GPL), version 2
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13
14#include <plat/ste_dma40.h>
15#include <mach/setup.h>
16#include <mach/hardware.h>
17
18#include "ste-dma40-db5500.h"
19
20static struct resource dma40_resources[] = {
21 [0] = {
22 .start = U5500_DMA_BASE,
23 .end = U5500_DMA_BASE + SZ_4K - 1,
24 .flags = IORESOURCE_MEM,
25 .name = "base",
26 },
27 [1] = {
28 .start = U5500_DMA_LCPA_BASE,
29 .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
30 .flags = IORESOURCE_MEM,
31 .name = "lcpa",
32 },
33 [2] = {
34 .start = IRQ_DB5500_DMA,
35 .end = IRQ_DB5500_DMA,
36 .flags = IORESOURCE_IRQ
37 }
38};
39
40/* Default configuration for physical memcpy */
41static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
42 .mode = STEDMA40_MODE_PHYSICAL,
43 .dir = STEDMA40_MEM_TO_MEM,
44
45 .src_info.data_width = STEDMA40_BYTE_WIDTH,
46 .src_info.psize = STEDMA40_PSIZE_PHY_1,
47 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
48
49 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
50 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
51 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
52};
53
54/* Default configuration for logical memcpy */
55static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
56 .dir = STEDMA40_MEM_TO_MEM,
57
58 .src_info.data_width = STEDMA40_BYTE_WIDTH,
59 .src_info.psize = STEDMA40_PSIZE_LOG_1,
60 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
61
62 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
63 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
64 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65};
66
67/*
68 * Mapping between soruce event lines and physical device address This was
69 * created assuming that the event line is tied to a device and therefore the
70 * address is constant, however this is not true for at least USB, and the
71 * values are just placeholders for USB. This table is preserved and used for
72 * now.
73 */
74static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
75 [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
76 [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
77 [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
78 [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
79 [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
80 [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
81 [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
82 [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
83 [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
84};
85
86/* Mapping between destination event lines and physical device address */
87static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
88 [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
89 [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
90 [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
91 [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
92 [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
93 [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
94 [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
95 [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
96 [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
97};
98
99static int dma40_memcpy_event[] = {
100 DB5500_DMA_MEMCPY_TX_1,
101 DB5500_DMA_MEMCPY_TX_2,
102 DB5500_DMA_MEMCPY_TX_3,
103 DB5500_DMA_MEMCPY_TX_4,
104 DB5500_DMA_MEMCPY_TX_5,
105};
106
107static struct stedma40_platform_data dma40_plat_data = {
108 .dev_len = ARRAY_SIZE(dma40_rx_map),
109 .dev_rx = dma40_rx_map,
110 .dev_tx = dma40_tx_map,
111 .memcpy = dma40_memcpy_event,
112 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
113 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
114 .memcpy_conf_log = &dma40_memcpy_conf_log,
115 .disabled_channels = {-1},
116};
117
118static struct platform_device dma40_device = {
119 .dev = {
120 .platform_data = &dma40_plat_data,
121 },
122 .name = "dma40",
123 .id = 0,
124 .num_resources = ARRAY_SIZE(dma40_resources),
125 .resource = dma40_resources
126};
127
128void __init db5500_dma_init(struct device *parent)
129{
130 int ret;
131
132 dma40_device.dev.parent = parent;
133 ret = platform_device_register(&dma40_device);
134 if (ret)
135 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
136
137}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
deleted file mode 100644
index 8e714bcb099f..000000000000
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
22#define U5500_MCDE_BASE 0xA0400000
23#define U5500_MODEM_BASE 0xB0000000
24#define U5500_L2CC_BASE 0xA0412000
25#define U5500_SCU_BASE 0xA0410000
26#define U5500_DSI1_BASE 0xA0401000
27#define U5500_DSI2_BASE 0xA0402000
28#define U5500_SIA_BASE 0xA0100000
29#define U5500_SVA_BASE 0x80200000
30#define U5500_HSEM_BASE 0xA0000000
31#define U5500_NAND0_BASE 0x60000000
32#define U5500_NAND1_BASE 0x70000000
33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
37
38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
40#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
41#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
42#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
43#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
44#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
45#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
46
47#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
48#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
49#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
50
51#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
52#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
53#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
54#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
55
56#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
57#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
58#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
59#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
60#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
61#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
62#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
63#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
64#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
65#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
66#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
67#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
68#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000)
69#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
70#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
71#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000)
72#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000)
73
74#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
75#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
76#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
77#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
78#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
79#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
80#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
81#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
82#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
83#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
84#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
85#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
86#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
87#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
88#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
89#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
90#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
91
92#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
93#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
94#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
95#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
96#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
97#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
98#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
99#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
100#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
101#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
102#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
103
104#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
105#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
106#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
107#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
108#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
109#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
110#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
111#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
112
113#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
114#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
115#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
116#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
117#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
118#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
119#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
120#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
121#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
122#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
123#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
124#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
125#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
126
127#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
128#define U5500_ACCCON_BASE (0xBFFF1000)
129#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
130#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
131#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4)
132
133#define U5500_ESRAM_BASE 0x40000000
134#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
135#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
136
137#define U5500_MCDE_SIZE 0x1000
138#define U5500_DSI_LINK_SIZE 0x1000
139#define U5500_DSI_LINK_COUNT 0x2
140#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
141#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
142
143#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8d74d927d4e2..67035223334a 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -20,10 +20,6 @@
20 * built, so that there's some hint during the build that something is wrong. 20 * built, so that there's some hint during the build that something is wrong.
21 */ 21 */
22 22
23#ifdef CONFIG_UX500_SOC_DB5500
24#define __UX500_UART(n) U5500_UART##n##_BASE
25#endif
26
27#ifdef CONFIG_UX500_SOC_DB8500 23#ifdef CONFIG_UX500_SOC_DB8500
28#define __UX500_UART(n) U8500_UART##n##_BASE 24#define __UX500_UART(n) U8500_UART##n##_BASE
29#endif 25#endif
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 5f6cb71fc62d..9b5eb69a0154 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -10,7 +10,6 @@
10struct platform_device; 10struct platform_device;
11struct amba_device; 11struct amba_device;
12 12
13extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[]; 13extern struct platform_device u8500_gpio_devs[];
15 14
16extern struct amba_device ux500_pl031_device; 15extern struct amba_device ux500_pl031_device;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index f84698936d36..cf6fac3d1eeb 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -28,7 +28,6 @@
28#define io_p2v(n) __io_address(n) 28#define io_p2v(n) __io_address(n)
29 29
30#include <mach/db8500-regs.h> 30#include <mach/db8500-regs.h>
31#include <mach/db5500-regs.h>
32 31
33#define MSP_TX_RX_REG_OFFSET 0 32#define MSP_TX_RX_REG_OFFSET 0
34 33
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
deleted file mode 100644
index 29d972c7717b..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
deleted file mode 100644
index 77239776a6f2..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
68#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
69#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
70#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
71#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
72#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
73#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
74#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
75#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
76#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
77#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
78#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
79#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
80#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
81#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
82#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
113#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index c23a6b5f0c4e..d06dcf6208fa 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -36,7 +36,6 @@
36/* This will be overridden by SoC-specific irq headers */ 36/* This will be overridden by SoC-specific irq headers */
37#define IRQ_SOC_END IRQ_SOC_START 37#define IRQ_SOC_END IRQ_SOC_START
38 38
39#include <mach/irqs-db5500.h>
40#include <mach/irqs-db8500.h> 39#include <mach/irqs-db8500.h>
41 40
42#define IRQ_BOARD_START IRQ_SOC_END 41#define IRQ_BOARD_START IRQ_SOC_END
@@ -47,10 +46,6 @@
47#include <mach/irqs-board-mop500.h> 46#include <mach/irqs-board-mop500.h>
48#endif 47#endif
49 48
50#ifdef CONFIG_MACH_U5500
51#include <mach/irqs-board-u5500.h>
52#endif
53
54#define NR_IRQS IRQ_BOARD_END 49#define NR_IRQS IRQ_BOARD_END
55 50
56#endif /* ASM_ARCH_IRQS_H */ 51#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
deleted file mode 100644
index 7f9da4d2fbda..000000000000
--- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 3dc00ffa7bfa..4e369f1645ec 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -15,18 +15,12 @@
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17void __init ux500_map_io(void); 17void __init ux500_map_io(void);
18extern void __init u5500_map_io(void);
19extern void __init u8500_map_io(void); 18extern void __init u8500_map_io(void);
20 19
21extern struct device * __init u5500_init_devices(void);
22extern struct device * __init u8500_init_devices(void); 20extern struct device * __init u8500_init_devices(void);
23 21
24extern void __init ux500_init_irq(void); 22extern void __init ux500_init_irq(void);
25 23
26extern void __init u5500_sdi_init(struct device *parent);
27
28extern void __init db5500_dma_init(struct device *parent);
29
30extern struct device *ux500_soc_device_init(const char *soc_id); 24extern struct device *ux500_soc_device_init(const char *soc_id);
31 25
32struct amba_device; 26struct amba_device;
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 6fb3c4b0105d..34775baadaea 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,11 +50,8 @@ static void flush(void)
50 50
51static inline void arch_decomp_setup(void) 51static inline void arch_decomp_setup(void)
52{ 52{
53 /* Check in run time if we run on an U8500 or U5500 */ 53 /* Use machine_is_foo() macro if you need to switch base someday */
54 if (machine_is_u5500()) 54 ux500_uart_base = U8500_UART2_BASE;
55 ux500_uart_base = U5500_UART0_BASE;
56 else
57 ux500_uart_base = U8500_UART2_BASE;
58} 55}
59 56
60#define arch_decomp_wdog() /* nothing to do here */ 57#define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
deleted file mode 100644
index 0127490218cd..000000000000
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ /dev/null
@@ -1,565 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8/*
9 * Mailbox nomenclature:
10 *
11 * APE MODEM
12 * mbox pairX
13 * ..........................
14 * . .
15 * . peer .
16 * . send ---- .
17 * . --> | | .
18 * . | | .
19 * . ---- .
20 * . .
21 * . local .
22 * . rec ---- .
23 * . | | <-- .
24 * . | | .
25 * . ---- .
26 * .........................
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/platform_device.h>
38#include <linux/debugfs.h>
39#include <linux/seq_file.h>
40#include <linux/completion.h>
41#include <mach/mbox-db5500.h>
42
43#define MBOX_NAME "mbox"
44
45#define MBOX_FIFO_DATA 0x000
46#define MBOX_FIFO_ADD 0x004
47#define MBOX_FIFO_REMOVE 0x008
48#define MBOX_FIFO_THRES_FREE 0x00C
49#define MBOX_FIFO_THRES_OCCUP 0x010
50#define MBOX_FIFO_STATUS 0x014
51
52#define MBOX_DISABLE_IRQ 0x4
53#define MBOX_ENABLE_IRQ 0x0
54#define MBOX_LATCH 1
55
56/* Global list of all mailboxes */
57static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
58
59static struct mbox *get_mbox_with_id(u8 id)
60{
61 u8 i;
62 struct list_head *pos = &mboxs;
63 for (i = 0; i <= id; i++)
64 pos = pos->next;
65
66 return (struct mbox *) list_entry(pos, struct mbox, list);
67}
68
69int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
70{
71 int res = 0;
72
73 spin_lock(&mbox->lock);
74
75 dev_dbg(&(mbox->pdev->dev),
76 "About to buffer 0x%X to mailbox 0x%X."
77 " ri = %d, wi = %d\n",
78 mbox_msg, (u32)mbox, mbox->read_index,
79 mbox->write_index);
80
81 /* Check if write buffer is full */
82 while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
83 if (!block) {
84 dev_dbg(&(mbox->pdev->dev),
85 "Buffer full in non-blocking call! "
86 "Returning -ENOMEM!\n");
87 res = -ENOMEM;
88 goto exit;
89 }
90 spin_unlock(&mbox->lock);
91 dev_dbg(&(mbox->pdev->dev),
92 "Buffer full in blocking call! Sleeping...\n");
93 mbox->client_blocked = 1;
94 wait_for_completion(&mbox->buffer_available);
95 dev_dbg(&(mbox->pdev->dev),
96 "Blocking send was woken up! Trying again...\n");
97 spin_lock(&mbox->lock);
98 }
99
100 mbox->buffer[mbox->write_index] = mbox_msg;
101 mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
102
103 /*
104 * Indicate that we want an IRQ as soon as there is a slot
105 * in the FIFO
106 */
107 writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
108
109exit:
110 spin_unlock(&mbox->lock);
111 return res;
112}
113EXPORT_SYMBOL(mbox_send);
114
115#if defined(CONFIG_DEBUG_FS)
116/*
117 * Expected input: <value> <nbr sends>
118 * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
119 */
120static ssize_t mbox_write_fifo(struct device *dev,
121 struct device_attribute *attr,
122 const char *buf,
123 size_t count)
124{
125 unsigned long mbox_mess;
126 unsigned long nbr_sends;
127 unsigned long i;
128 char int_buf[16];
129 char *token;
130 char *val;
131
132 struct mbox *mbox = (struct mbox *) dev->platform_data;
133
134 strncpy((char *) &int_buf, buf, sizeof(int_buf));
135 token = (char *) &int_buf;
136
137 /* Parse message */
138 val = strsep(&token, " ");
139 if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
140 mbox_mess = 0xDEADBEEF;
141
142 val = strsep(&token, " ");
143 if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
144 nbr_sends = 1;
145
146 dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
147 mbox_mess, nbr_sends, (u32) mbox);
148
149 for (i = 0; i < nbr_sends; i++)
150 mbox_send(mbox, mbox_mess, true);
151
152 return count;
153}
154
155static ssize_t mbox_read_fifo(struct device *dev,
156 struct device_attribute *attr,
157 char *buf)
158{
159 int mbox_value;
160 struct mbox *mbox = (struct mbox *) dev->platform_data;
161
162 if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
163 return sprintf(buf, "Mailbox is empty\n");
164
165 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
166 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
167
168 return sprintf(buf, "0x%X\n", mbox_value);
169}
170
171static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
172
173static int mbox_show(struct seq_file *s, void *data)
174{
175 struct list_head *pos;
176 u8 mbox_index = 0;
177
178 list_for_each(pos, &mboxs) {
179 struct mbox *m =
180 (struct mbox *) list_entry(pos, struct mbox, list);
181 if (m == NULL) {
182 seq_printf(s,
183 "Unable to retrieve mailbox %d\n",
184 mbox_index);
185 continue;
186 }
187
188 spin_lock(&m->lock);
189 if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
190 seq_printf(s, "MAILBOX %d not setup or corrupt\n",
191 mbox_index);
192 spin_unlock(&m->lock);
193 continue;
194 }
195
196 seq_printf(s,
197 "===========================\n"
198 " MAILBOX %d\n"
199 " PEER MAILBOX DUMP\n"
200 "---------------------------\n"
201 "FIFO: 0x%X (%d)\n"
202 "Free Threshold: 0x%.2X (%d)\n"
203 "Occupied Threshold: 0x%.2X (%d)\n"
204 "Status: 0x%.2X (%d)\n"
205 " Free spaces (ot): %d (%d)\n"
206 " Occup spaces (ot): %d (%d)\n"
207 "===========================\n"
208 " LOCAL MAILBOX DUMP\n"
209 "---------------------------\n"
210 "FIFO: 0x%.X (%d)\n"
211 "Free Threshold: 0x%.2X (%d)\n"
212 "Occupied Threshold: 0x%.2X (%d)\n"
213 "Status: 0x%.2X (%d)\n"
214 " Free spaces (ot): %d (%d)\n"
215 " Occup spaces (ot): %d (%d)\n"
216 "===========================\n"
217 "write_index: %d\n"
218 "read_index : %d\n"
219 "===========================\n"
220 "\n",
221 mbox_index,
222 readl(m->virtbase_peer + MBOX_FIFO_DATA),
223 readl(m->virtbase_peer + MBOX_FIFO_DATA),
224 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
225 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
226 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
227 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
228 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
229 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
230 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
231 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
232 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
233 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
234 readl(m->virtbase_local + MBOX_FIFO_DATA),
235 readl(m->virtbase_local + MBOX_FIFO_DATA),
236 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
237 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
238 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
239 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
240 readl(m->virtbase_local + MBOX_FIFO_STATUS),
241 readl(m->virtbase_local + MBOX_FIFO_STATUS),
242 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
243 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
244 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
245 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
246 m->write_index, m->read_index);
247 mbox_index++;
248 spin_unlock(&m->lock);
249 }
250
251 return 0;
252}
253
254static int mbox_open(struct inode *inode, struct file *file)
255{
256 return single_open(file, mbox_show, NULL);
257}
258
259static const struct file_operations mbox_operations = {
260 .owner = THIS_MODULE,
261 .open = mbox_open,
262 .read = seq_read,
263 .llseek = seq_lseek,
264 .release = single_release,
265};
266#endif
267
268static irqreturn_t mbox_irq(int irq, void *arg)
269{
270 u32 mbox_value;
271 int nbr_occup;
272 int nbr_free;
273 struct mbox *mbox = (struct mbox *) arg;
274
275 spin_lock(&mbox->lock);
276
277 dev_dbg(&(mbox->pdev->dev),
278 "mbox IRQ [%d] received. ri = %d, wi = %d\n",
279 irq, mbox->read_index, mbox->write_index);
280
281 /*
282 * Check if we have any outgoing messages, and if there is space for
283 * them in the FIFO.
284 */
285 if (mbox->read_index != mbox->write_index) {
286 /*
287 * Check by reading FREE for LOCAL since that indicates
288 * OCCUP for PEER
289 */
290 nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
291 >> 4) & 0x7;
292 dev_dbg(&(mbox->pdev->dev),
293 "Status indicates %d empty spaces in the FIFO!\n",
294 nbr_free);
295
296 while ((nbr_free > 0) &&
297 (mbox->read_index != mbox->write_index)) {
298 /* Write the message and latch it into the FIFO */
299 writel(mbox->buffer[mbox->read_index],
300 (mbox->virtbase_peer + MBOX_FIFO_DATA));
301 writel(MBOX_LATCH,
302 (mbox->virtbase_peer + MBOX_FIFO_ADD));
303 dev_dbg(&(mbox->pdev->dev),
304 "Wrote message 0x%X to addr 0x%X\n",
305 mbox->buffer[mbox->read_index],
306 (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
307
308 nbr_free--;
309 mbox->read_index =
310 (mbox->read_index + 1) % MBOX_BUF_SIZE;
311 }
312
313 /*
314 * Check if we still want IRQ:s when there is free
315 * space to send
316 */
317 if (mbox->read_index != mbox->write_index) {
318 dev_dbg(&(mbox->pdev->dev),
319 "Still have messages to send, but FIFO full. "
320 "Request IRQ again!\n");
321 writel(MBOX_ENABLE_IRQ,
322 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
323 } else {
324 dev_dbg(&(mbox->pdev->dev),
325 "No more messages to send. "
326 "Do not request IRQ again!\n");
327 writel(MBOX_DISABLE_IRQ,
328 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
329 }
330
331 /*
332 * Check if we can signal any blocked clients that it is OK to
333 * start buffering again
334 */
335 if (mbox->client_blocked &&
336 (((mbox->write_index + 1) % MBOX_BUF_SIZE)
337 != mbox->read_index)) {
338 dev_dbg(&(mbox->pdev->dev),
339 "Waking up blocked client\n");
340 complete(&mbox->buffer_available);
341 mbox->client_blocked = 0;
342 }
343 }
344
345 /* Check if we have any incoming messages */
346 nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
347 if (nbr_occup == 0)
348 goto exit;
349
350 if (mbox->cb == NULL) {
351 dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
352 "leaving %d incoming messages in fifo!\n", nbr_occup);
353 goto exit;
354 }
355
356 /* Read and acknowledge the message */
357 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
358 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
359
360 /* Notify consumer of new mailbox message */
361 dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
362 mbox_value);
363 mbox->cb(mbox_value, mbox->client_data);
364
365exit:
366 dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
367 mbox->read_index, mbox->write_index);
368 spin_unlock(&mbox->lock);
369
370 return IRQ_HANDLED;
371}
372
373/* Setup is executed once for each mbox pair */
374struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
375{
376 struct resource *resource;
377 int irq;
378 int res;
379 struct mbox *mbox;
380
381 mbox = get_mbox_with_id(mbox_id);
382 if (mbox == NULL) {
383 dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
384 mbox_id);
385 goto exit;
386 }
387
388 /*
389 * Check if mailbox has been allocated to someone else,
390 * otherwise allocate it
391 */
392 if (mbox->allocated) {
393 dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
394 mbox_id);
395 mbox = NULL;
396 goto exit;
397 }
398 mbox->allocated = true;
399
400 dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
401 mbox_id, (u32)mbox);
402
403 mbox->client_data = priv;
404 mbox->cb = mbox_cb;
405
406 /* Get addr for peer mailbox and ioremap it */
407 resource = platform_get_resource_byname(mbox->pdev,
408 IORESOURCE_MEM,
409 "mbox_peer");
410 if (resource == NULL) {
411 dev_err(&(mbox->pdev->dev),
412 "Unable to retrieve mbox peer resource\n");
413 mbox = NULL;
414 goto exit;
415 }
416 dev_dbg(&(mbox->pdev->dev),
417 "Resource name: %s start: 0x%X, end: 0x%X\n",
418 resource->name, resource->start, resource->end);
419 mbox->virtbase_peer = ioremap(resource->start, resource_size(resource));
420 if (!mbox->virtbase_peer) {
421 dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
422 mbox = NULL;
423 goto exit;
424 }
425 dev_dbg(&(mbox->pdev->dev),
426 "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
427 resource->start, resource->end, (u32) mbox->virtbase_peer);
428
429 /* Get addr for local mailbox and ioremap it */
430 resource = platform_get_resource_byname(mbox->pdev,
431 IORESOURCE_MEM,
432 "mbox_local");
433 if (resource == NULL) {
434 dev_err(&(mbox->pdev->dev),
435 "Unable to retrieve mbox local resource\n");
436 mbox = NULL;
437 goto exit;
438 }
439 dev_dbg(&(mbox->pdev->dev),
440 "Resource name: %s start: 0x%X, end: 0x%X\n",
441 resource->name, resource->start, resource->end);
442 mbox->virtbase_local = ioremap(resource->start, resource_size(resource));
443 if (!mbox->virtbase_local) {
444 dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
445 mbox = NULL;
446 goto exit;
447 }
448 dev_dbg(&(mbox->pdev->dev),
449 "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
450 resource->start, resource->end, (u32) mbox->virtbase_peer);
451
452 init_completion(&mbox->buffer_available);
453 mbox->client_blocked = 0;
454
455 /* Get IRQ for mailbox and allocate it */
456 irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
457 if (irq < 0) {
458 dev_err(&(mbox->pdev->dev),
459 "Unable to retrieve mbox irq resource\n");
460 mbox = NULL;
461 goto exit;
462 }
463
464 dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
465 res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
466 if (res < 0) {
467 dev_err(&(mbox->pdev->dev),
468 "Unable to allocate mbox irq %d\n", irq);
469 mbox = NULL;
470 goto exit;
471 }
472
473 /* Set up mailbox to not launch IRQ on free space in mailbox */
474 writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
475
476 /*
477 * Set up mailbox to launch IRQ on new message if we have
478 * a callback set. If not, do not raise IRQ, but keep message
479 * in FIFO for manual retrieval
480 */
481 if (mbox_cb != NULL)
482 writel(MBOX_ENABLE_IRQ,
483 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
484 else
485 writel(MBOX_DISABLE_IRQ,
486 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
487
488#if defined(CONFIG_DEBUG_FS)
489 res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
490 if (res != 0)
491 dev_warn(&(mbox->pdev->dev),
492 "Unable to create mbox sysfs entry");
493
494 (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
495 NULL, &mbox_operations);
496#endif
497
498 dev_info(&(mbox->pdev->dev),
499 "Mailbox driver with index %d initiated!\n", mbox_id);
500
501exit:
502 return mbox;
503}
504EXPORT_SYMBOL(mbox_setup);
505
506
507int __init mbox_probe(struct platform_device *pdev)
508{
509 struct mbox local_mbox;
510 struct mbox *mbox;
511 int res = 0;
512 dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
513
514 memset(&local_mbox, 0x0, sizeof(struct mbox));
515
516 /* Associate our mbox data with the platform device */
517 res = platform_device_add_data(pdev,
518 (void *) &local_mbox,
519 sizeof(struct mbox));
520 if (res != 0) {
521 dev_err(&(pdev->dev),
522 "Unable to allocate driver platform data!\n");
523 goto exit;
524 }
525
526 mbox = (struct mbox *) pdev->dev.platform_data;
527 mbox->pdev = pdev;
528 mbox->write_index = 0;
529 mbox->read_index = 0;
530
531 INIT_LIST_HEAD(&(mbox->list));
532 list_add_tail(&(mbox->list), &mboxs);
533
534 sprintf(mbox->name, "%s", MBOX_NAME);
535 spin_lock_init(&mbox->lock);
536
537 dev_info(&(pdev->dev), "Mailbox driver loaded\n");
538
539exit:
540 return res;
541}
542
543static struct platform_driver mbox_driver = {
544 .driver = {
545 .name = MBOX_NAME,
546 .owner = THIS_MODULE,
547 },
548};
549
550static int __init mbox_init(void)
551{
552 return platform_driver_probe(&mbox_driver, mbox_probe);
553}
554
555module_init(mbox_init);
556
557void __exit mbox_exit(void)
558{
559 platform_driver_unregister(&mbox_driver);
560}
561
562module_exit(mbox_exit);
563
564MODULE_LICENSE("GPL");
565MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
deleted file mode 100644
index 6b86416c94c9..000000000000
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14
15#include <mach/id.h>
16
17#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
18#define MODEM_INTCON_SIZE 0xFFF
19
20#define DEST_IRQ41_OFFSET 0x2A4
21#define DEST_IRQ43_OFFSET 0x2AC
22#define DEST_IRQ45_OFFSET 0x2B4
23
24#define PRIO_IRQ41_OFFSET 0x6A4
25#define PRIO_IRQ43_OFFSET 0x6AC
26#define PRIO_IRQ45_OFFSET 0x6B4
27
28#define ALLOW_IRQ_OFFSET 0x104
29
30#define MODEM_INTCON_CPU_NBR 0x1
31#define MODEM_INTCON_PRIO_HIGH 0x0
32
33#define MODEM_INTCON_ALLOW_IRQ41 0x0200
34#define MODEM_INTCON_ALLOW_IRQ43 0x0800
35#define MODEM_INTCON_ALLOW_IRQ45 0x2000
36
37#define MODEM_IRQ_REG_OFFSET 0x4
38
39struct modem_irq {
40 void __iomem *modem_intcon_base;
41};
42
43
44static void setup_modem_intcon(void __iomem *modem_intcon_base)
45{
46 /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
47 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
48 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
49 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
50
51 /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
52 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
53 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
54 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
55
56 /* IC_ALLOW_ARRAY - IRQ enable */
57 writel(MODEM_INTCON_ALLOW_IRQ41 |
58 MODEM_INTCON_ALLOW_IRQ43 |
59 MODEM_INTCON_ALLOW_IRQ45,
60 modem_intcon_base + ALLOW_IRQ_OFFSET);
61}
62
63static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
64{
65 int real_irq;
66 int virt_irq;
67 struct modem_irq *mi = (struct modem_irq *)data;
68
69 /* Read modem side IRQ number from modem IRQ controller */
70 real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
71 virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
72
73 pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
74 "which will be 0x%X (%d) which translates to "
75 "virtual IRQ 0x%X (%d)!\n",
76 (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
77 real_irq,
78 real_irq & 0xFF,
79 real_irq & 0xFF,
80 virt_irq,
81 virt_irq);
82
83 if (virt_irq != 0)
84 generic_handle_irq(virt_irq);
85
86 pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
87
88 return IRQ_HANDLED;
89}
90
91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92{
93 irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
94 set_irq_flags(irq, IRQF_VALID);
95
96 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
97}
98
99static int modem_irq_init(void)
100{
101 int err;
102 static struct irq_chip modem_irq_chip;
103 struct modem_irq *mi;
104
105 if (!cpu_is_u5500())
106 return -ENODEV;
107
108 pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
109 IRQ_DB5500_MODEM);
110
111 mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
112 if (!mi) {
113 pr_err("modem_irq: Could not allocate device\n");
114 return -ENOMEM;
115 }
116
117 mi->modem_intcon_base =
118 ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
119 pr_debug("modem_irq: ioremapped modem_intcon_base from "
120 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
121 (u32)mi->modem_intcon_base);
122
123 setup_modem_intcon(mi->modem_intcon_base);
124
125 modem_irq_chip = dummy_irq_chip;
126 modem_irq_chip.name = "modem_irq";
127
128 /* Create the virtual IRQ:s needed */
129 create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
130 create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
131 create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
132
133 err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
134 modem_cpu_irq_handler, IRQF_ONESHOT,
135 "modem_irq", mi);
136 if (err)
137 pr_err("modem_irq: Could not register IRQ %d\n",
138 IRQ_DB5500_MODEM);
139
140 return 0;
141}
142
143arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
deleted file mode 100644
index bf50c21fe69d..000000000000
--- a/arch/arm/mach-ux500/pins-db5500.h
+++ /dev/null
@@ -1,620 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_DB5500_PINS_H
9#define __MACH_DB5500_PINS_H
10
11#define GPIO0_GPIO PIN_CFG(0, GPIO)
12#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A)
13
14#define GPIO1_GPIO PIN_CFG(1, GPIO)
15#define GPIO1_SM_A3 PIN_CFG(1, ALT_A)
16
17#define GPIO2_GPIO PIN_CFG(2, GPIO)
18#define GPIO2_SM_A4 PIN_CFG(2, ALT_A)
19#define GPIO2_SM_AVD PIN_CFG(2, ALT_B)
20
21#define GPIO3_GPIO PIN_CFG(3, GPIO)
22#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A)
23
24#define GPIO4_GPIO PIN_CFG(4, GPIO)
25#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A)
26
27#define GPIO5_GPIO PIN_CFG(5, GPIO)
28#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A)
29#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B)
30
31#define GPIO6_GPIO PIN_CFG(6, GPIO)
32#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A)
33#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B)
34
35#define GPIO7_GPIO PIN_CFG(7, GPIO)
36#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A)
37#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B)
38
39#define GPIO8_GPIO PIN_CFG(8, GPIO)
40#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A)
41#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B)
42
43#define GPIO9_GPIO PIN_CFG(9, GPIO)
44#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A)
45#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B)
46
47#define GPIO10_GPIO PIN_CFG(10, GPIO)
48#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A)
49#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B)
50
51#define GPIO11_GPIO PIN_CFG(11, GPIO)
52#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A)
53#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B)
54
55#define GPIO12_GPIO PIN_CFG(12, GPIO)
56#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A)
57#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B)
58
59#define GPIO13_GPIO PIN_CFG(13, GPIO)
60#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A)
61#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B)
62#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C)
63
64#define GPIO14_GPIO PIN_CFG(14, GPIO)
65#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A)
66#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B)
67#define GPIO14_SM_CKO PIN_CFG(14, ALT_C)
68
69#define GPIO15_GPIO PIN_CFG(15, GPIO)
70#define GPIO15_SM_A5 PIN_CFG(15, ALT_A)
71#define GPIO15_SM_CLE PIN_CFG(15, ALT_B)
72
73#define GPIO16_GPIO PIN_CFG(16, GPIO)
74#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A)
75#define GPIO16_SM_OEn PIN_CFG(16, ALT_B)
76
77#define GPIO17_GPIO PIN_CFG(17, GPIO)
78#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A)
79#define GPIO17_SM_WEn PIN_CFG(17, ALT_B)
80
81#define GPIO18_GPIO PIN_CFG(18, GPIO)
82#define GPIO18_SM_A6 PIN_CFG(18, ALT_A)
83#define GPIO18_SM_ALE PIN_CFG(18, ALT_B)
84#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C)
85
86#define GPIO19_GPIO PIN_CFG(19, GPIO)
87#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A)
88#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B)
89
90#define GPIO20_GPIO PIN_CFG(20, GPIO)
91#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A)
92#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B)
93
94#define GPIO21_GPIO PIN_CFG(21, GPIO)
95#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A)
96#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B)
97
98#define GPIO22_GPIO PIN_CFG(22, GPIO)
99#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A)
100#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B)
101
102#define GPIO23_GPIO PIN_CFG(23, GPIO)
103#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A)
104#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B)
105#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C)
106
107#define GPIO24_GPIO PIN_CFG(24, GPIO)
108#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A)
109#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B)
110#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C)
111
112#define GPIO25_GPIO PIN_CFG(25, GPIO)
113#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A)
114#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B)
115#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C)
116
117#define GPIO26_GPIO PIN_CFG(26, GPIO)
118#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A)
119#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B)
120
121#define GPIO27_GPIO PIN_CFG(27, GPIO)
122#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A)
123#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B)
124
125#define GPIO28_GPIO PIN_CFG(28, GPIO)
126#define GPIO28_U0_TXD PIN_CFG(28, ALT_A)
127#define GPIO28_SM_A0 PIN_CFG(28, ALT_B)
128
129#define GPIO29_GPIO PIN_CFG(29, GPIO)
130#define GPIO29_U0_RXD PIN_CFG(29, ALT_A)
131#define GPIO29_SM_A1 PIN_CFG(29, ALT_B)
132#define GPIO29_PWM_0 PIN_CFG(29, ALT_C)
133
134#define GPIO30_GPIO PIN_CFG(30, GPIO)
135#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
136#define GPIO30_SM_A2 PIN_CFG(30, ALT_B)
137#define GPIO30_PWM_1 PIN_CFG(30, ALT_C)
138
139#define GPIO31_GPIO PIN_CFG(31, GPIO)
140#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A)
141#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B)
142#define GPIO31_PWM_2 PIN_CFG(31, ALT_C)
143
144#define GPIO32_GPIO PIN_CFG(32, GPIO)
145#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A)
146#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B)
147
148#define GPIO33_GPIO PIN_CFG(33, GPIO)
149#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A)
150#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B)
151
152#define GPIO34_GPIO PIN_CFG(34, GPIO)
153#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A)
154#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B)
155
156#define GPIO35_GPIO PIN_CFG(35, GPIO)
157#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A)
158#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B)
159
160#define GPIO64_GPIO PIN_CFG(64, GPIO)
161#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A)
162#define GPIO64_U0_TXD PIN_CFG(64, ALT_B)
163
164#define GPIO65_GPIO PIN_CFG(65, GPIO)
165#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A)
166#define GPIO65_U0_RXD PIN_CFG(65, ALT_B)
167
168#define GPIO66_GPIO PIN_CFG(66, GPIO)
169#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A)
170
171#define GPIO67_GPIO PIN_CFG(67, GPIO)
172#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A)
173
174#define GPIO68_GPIO PIN_CFG(68, GPIO)
175#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A)
176
177#define GPIO69_GPIO PIN_CFG(69, GPIO)
178#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A)
179
180#define GPIO70_GPIO PIN_CFG(70, GPIO)
181#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A)
182
183#define GPIO71_GPIO PIN_CFG(71, GPIO)
184#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A)
185
186#define GPIO72_GPIO PIN_CFG(72, GPIO)
187#define GPIO72_USB_STP PIN_CFG(72, ALT_A)
188
189#define GPIO73_GPIO PIN_CFG(73, GPIO)
190#define GPIO73_USB_DIR PIN_CFG(73, ALT_A)
191
192#define GPIO74_GPIO PIN_CFG(74, GPIO)
193#define GPIO74_USB_NXT PIN_CFG(74, ALT_A)
194
195#define GPIO75_GPIO PIN_CFG(75, GPIO)
196#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A)
197
198#define GPIO76_GPIO PIN_CFG(76, GPIO)
199
200#define GPIO77_GPIO PIN_CFG(77, GPIO)
201#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A)
202
203#define GPIO78_GPIO PIN_CFG(78, GPIO)
204#define GPIO78_IRQn PIN_CFG(78, ALT_A)
205
206#define GPIO79_GPIO PIN_CFG(79, GPIO)
207#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A)
208
209#define GPIO80_GPIO PIN_CFG(80, GPIO)
210#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A)
211
212#define GPIO81_GPIO PIN_CFG(81, GPIO)
213#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A)
214
215#define GPIO82_GPIO PIN_CFG(82, GPIO)
216#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A)
217
218#define GPIO96_GPIO PIN_CFG(96, GPIO)
219#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A)
220#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B)
221#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C)
222
223#define GPIO97_GPIO PIN_CFG(97, GPIO)
224#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A)
225#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B)
226#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C)
227
228#define GPIO98_GPIO PIN_CFG(98, GPIO)
229#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A)
230#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B)
231#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C)
232
233#define GPIO99_GPIO PIN_CFG(99, GPIO)
234#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A)
235#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B)
236#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C)
237
238#define GPIO100_GPIO PIN_CFG(100, GPIO)
239#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A)
240
241#define GPIO101_GPIO PIN_CFG(101, GPIO)
242#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A)
243
244#define GPIO128_GPIO PIN_CFG(128, GPIO)
245#define GPIO128_KP_I0 PIN_CFG(128, ALT_A)
246#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B)
247
248#define GPIO129_GPIO PIN_CFG(129, GPIO)
249#define GPIO129_KP_O0 PIN_CFG(129, ALT_A)
250#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B)
251
252#define GPIO130_GPIO PIN_CFG(130, GPIO)
253#define GPIO130_KP_I1 PIN_CFG(130, ALT_A)
254#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B)
255
256#define GPIO131_GPIO PIN_CFG(131, GPIO)
257#define GPIO131_KP_O1 PIN_CFG(131, ALT_A)
258#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B)
259
260#define GPIO132_GPIO PIN_CFG(132, GPIO)
261#define GPIO132_KP_I2 PIN_CFG(132, ALT_A)
262#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B)
263#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C)
264
265#define GPIO133_GPIO PIN_CFG(133, GPIO)
266#define GPIO133_KP_O2 PIN_CFG(133, ALT_A)
267#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B)
268#define GPIO133_U0_RXD PIN_CFG(133, ALT_C)
269
270#define GPIO134_GPIO PIN_CFG(134, GPIO)
271#define GPIO134_KP_I3 PIN_CFG(134, ALT_A)
272#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B)
273#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C)
274
275#define GPIO135_GPIO PIN_CFG(135, GPIO)
276#define GPIO135_KP_O3 PIN_CFG(135, ALT_A)
277#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B)
278#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C)
279
280#define GPIO136_GPIO PIN_CFG(136, GPIO)
281#define GPIO136_KP_I4 PIN_CFG(136, ALT_A)
282#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B)
283#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C)
284
285#define GPIO137_GPIO PIN_CFG(137, GPIO)
286#define GPIO137_KP_O4 PIN_CFG(137, ALT_A)
287#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B)
288#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C)
289
290#define GPIO138_GPIO PIN_CFG(138, GPIO)
291#define GPIO138_KP_I5 PIN_CFG(138, ALT_A)
292#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B)
293#define GPIO138_U0_TXD PIN_CFG(138, ALT_C)
294
295#define GPIO139_GPIO PIN_CFG(139, GPIO)
296#define GPIO139_KP_O5 PIN_CFG(139, ALT_A)
297#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B)
298#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C)
299
300#define GPIO140_GPIO PIN_CFG(140, GPIO)
301#define GPIO140_KP_I6 PIN_CFG(140, ALT_A)
302#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B)
303#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C)
304
305#define GPIO141_GPIO PIN_CFG(141, GPIO)
306#define GPIO141_KP_O6 PIN_CFG(141, ALT_A)
307#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B)
308#define GPIO141_U0_RXD PIN_CFG(141, ALT_C)
309
310#define GPIO142_GPIO PIN_CFG(142, GPIO)
311#define GPIO142_KP_I7 PIN_CFG(142, ALT_A)
312#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B)
313#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C)
314
315#define GPIO143_GPIO PIN_CFG(143, GPIO)
316#define GPIO143_KP_O7 PIN_CFG(143, ALT_A)
317#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B)
318#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C)
319
320#define GPIO144_GPIO PIN_CFG(144, GPIO)
321#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A)
322#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B)
323#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C)
324
325#define GPIO145_GPIO PIN_CFG(145, GPIO)
326#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A)
327#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B)
328#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C)
329
330#define GPIO146_GPIO PIN_CFG(146, GPIO)
331#define GPIO146_PWM_0 PIN_CFG(146, ALT_A)
332#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B)
333
334#define GPIO147_GPIO PIN_CFG(147, GPIO)
335#define GPIO147_PWM_1 PIN_CFG(147, ALT_A)
336#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B)
337
338#define GPIO148_GPIO PIN_CFG(148, GPIO)
339#define GPIO148_PWM_2 PIN_CFG(148, ALT_A)
340#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B)
341
342#define GPIO160_GPIO PIN_CFG(160, GPIO)
343#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A)
344
345#define GPIO161_GPIO PIN_CFG(161, GPIO)
346#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A)
347
348#define GPIO162_GPIO PIN_CFG(162, GPIO)
349#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A)
350
351#define GPIO163_GPIO PIN_CFG(163, GPIO)
352
353#define GPIO164_GPIO PIN_CFG(164, GPIO)
354#define GPIO164_GPS_START PIN_CFG(164, ALT_A)
355
356#define GPIO165_GPIO PIN_CFG(165, GPIO)
357#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A)
358#define GPIO165_U3_RXD PIN_CFG(165, ALT_B)
359#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C)
360
361#define GPIO166_GPIO PIN_CFG(166, GPIO)
362#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A)
363#define GPIO166_U3_TXD PIN_CFG(166, ALT_B)
364#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C)
365
366#define GPIO167_GPIO PIN_CFG(167, GPIO)
367#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A)
368#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B)
369#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C)
370
371#define GPIO168_GPIO PIN_CFG(168, GPIO)
372#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A)
373#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B)
374#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C)
375
376#define GPIO169_GPIO PIN_CFG(169, GPIO)
377#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A)
378#define GPIO169_DDR_RC PIN_CFG(169, ALT_B)
379#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C)
380
381#define GPIO170_GPIO PIN_CFG(170, GPIO)
382#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A)
383
384#define GPIO171_GPIO PIN_CFG(171, GPIO)
385#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A)
386#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B)
387#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C)
388
389#define GPIO172_GPIO PIN_CFG(172, GPIO)
390#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A)
391#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B)
392#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C)
393
394#define GPIO173_GPIO PIN_CFG(173, GPIO)
395#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A)
396#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B)
397#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C)
398
399#define GPIO174_GPIO PIN_CFG(174, GPIO)
400#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A)
401#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B)
402#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C)
403
404#define GPIO175_GPIO PIN_CFG(175, GPIO)
405#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A)
406#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B)
407#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C)
408
409#define GPIO176_GPIO PIN_CFG(176, GPIO)
410#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A)
411#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B)
412
413#define GPIO177_GPIO PIN_CFG(177, GPIO)
414#define GPIO177_U2_RXD PIN_CFG(177, ALT_A)
415#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B)
416#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C)
417
418#define GPIO178_GPIO PIN_CFG(178, GPIO)
419#define GPIO178_U2_TXD PIN_CFG(178, ALT_A)
420#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B)
421#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C)
422
423#define GPIO179_GPIO PIN_CFG(179, GPIO)
424#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A)
425#define GPIO179_U3_RXD PIN_CFG(179, ALT_B)
426#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C)
427
428#define GPIO180_GPIO PIN_CFG(180, GPIO)
429#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A)
430#define GPIO180_U3_TXD PIN_CFG(180, ALT_B)
431#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C)
432
433#define GPIO185_GPIO PIN_CFG(185, GPIO)
434#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A)
435#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B)
436
437#define GPIO186_GPIO PIN_CFG(186, GPIO)
438#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A)
439#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B)
440
441#define GPIO187_GPIO PIN_CFG(187, GPIO)
442#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A)
443#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B)
444
445#define GPIO188_GPIO PIN_CFG(188, GPIO)
446#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A)
447#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B)
448
449#define GPIO189_GPIO PIN_CFG(189, GPIO)
450#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A)
451#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B)
452
453#define GPIO190_GPIO PIN_CFG(190, GPIO)
454#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A)
455#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B)
456
457#define GPIO191_GPIO PIN_CFG(191, GPIO)
458#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A)
459#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B)
460#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C)
461
462#define GPIO192_GPIO PIN_CFG(192, GPIO)
463#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A)
464#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B)
465#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C)
466
467#define GPIO193_GPIO PIN_CFG(193, GPIO)
468#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A)
469#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B)
470#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C)
471
472#define GPIO194_GPIO PIN_CFG(194, GPIO)
473#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A)
474#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B)
475#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C)
476
477#define GPIO195_GPIO PIN_CFG(195, GPIO)
478#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A)
479#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B)
480#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C)
481
482#define GPIO196_GPIO PIN_CFG(196, GPIO)
483#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A)
484#define GPIO196_U0_RXD PIN_CFG(196, ALT_B)
485#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C)
486
487#define GPIO197_GPIO PIN_CFG(197, GPIO)
488#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A)
489#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B)
490
491#define GPIO198_GPIO PIN_CFG(198, GPIO)
492#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A)
493
494#define GPIO199_GPIO PIN_CFG(199, GPIO)
495#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A)
496#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B)
497
498#define GPIO200_GPIO PIN_CFG(200, GPIO)
499#define GPIO200_U1_TXD PIN_CFG(200, ALT_A)
500#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B)
501
502#define GPIO201_GPIO PIN_CFG(201, GPIO)
503#define GPIO201_U1_RXD PIN_CFG(201, ALT_A)
504#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B)
505
506#define GPIO202_GPIO PIN_CFG(202, GPIO)
507#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A)
508#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B)
509
510#define GPIO203_GPIO PIN_CFG(203, GPIO)
511#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A)
512#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B)
513
514#define GPIO204_GPIO PIN_CFG(204, GPIO)
515#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A)
516#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B)
517#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C)
518
519#define GPIO205_GPIO PIN_CFG(205, GPIO)
520#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A)
521#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B)
522#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C)
523
524#define GPIO206_GPIO PIN_CFG(206, GPIO)
525#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A)
526#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B)
527#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C)
528
529#define GPIO207_GPIO PIN_CFG(207, GPIO)
530#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A)
531#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B)
532#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C)
533
534#define GPIO208_GPIO PIN_CFG(208, GPIO)
535#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A)
536#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B)
537#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C)
538
539#define GPIO209_GPIO PIN_CFG(209, GPIO)
540#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A)
541#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B)
542#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C)
543
544#define GPIO210_GPIO PIN_CFG(210, GPIO)
545#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A)
546#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B)
547
548#define GPIO211_GPIO PIN_CFG(211, GPIO)
549#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A)
550#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B)
551
552#define GPIO212_GPIO PIN_CFG(212, GPIO)
553#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A)
554#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B)
555
556#define GPIO213_GPIO PIN_CFG(213, GPIO)
557#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A)
558#define GPIO213_LCD_DE PIN_CFG(213, ALT_B)
559#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C)
560
561#define GPIO214_GPIO PIN_CFG(214, GPIO)
562#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A)
563#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B)
564#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C)
565
566#define GPIO215_GPIO PIN_CFG(215, GPIO)
567#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A)
568#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B)
569#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C)
570
571#define GPIO216_GPIO PIN_CFG(216, GPIO)
572#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A)
573#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B)
574
575#define GPIO217_GPIO PIN_CFG(217, GPIO)
576#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A)
577#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B)
578#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C)
579
580#define GPIO218_GPIO PIN_CFG(218, GPIO)
581#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A)
582#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B)
583
584#define GPIO219_GPIO PIN_CFG(219, GPIO)
585#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A)
586#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B)
587
588#define GPIO220_GPIO PIN_CFG(220, GPIO)
589#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A)
590#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B)
591
592#define GPIO221_GPIO PIN_CFG(221, GPIO)
593#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A)
594#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B)
595
596#define GPIO222_GPIO PIN_CFG(222, GPIO)
597#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A)
598#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B)
599
600#define GPIO223_GPIO PIN_CFG(223, GPIO)
601#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A)
602#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B)
603
604#define GPIO224_GPIO PIN_CFG(224, GPIO)
605#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A)
606#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B)
607
608#define GPIO225_GPIO PIN_CFG(225, GPIO)
609#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A)
610#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B)
611
612#define GPIO226_GPIO PIN_CFG(226, GPIO)
613#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A)
614#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B)
615
616#define GPIO227_GPIO PIN_CFG(227, GPIO)
617#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A)
618#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B)
619
620#endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index eff5842f6232..e8cd51aa61e4 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,9 +48,7 @@ static void write_pen_release(int val)
48 48
49static void __iomem *scu_base_addr(void) 49static void __iomem *scu_base_addr(void)
50{ 50{
51 if (cpu_is_u5500()) 51 if (cpu_is_u8500())
52 return __io_address(U5500_SCU_BASE);
53 else if (cpu_is_u8500())
54 return __io_address(U8500_SCU_BASE); 52 return __io_address(U8500_SCU_BASE);
55 else 53 else
56 ux500_unknown_soc(); 54 ux500_unknown_soc();
@@ -120,9 +118,7 @@ static void __init wakeup_secondary(void)
120{ 118{
121 void __iomem *backupram; 119 void __iomem *backupram;
122 120
123 if (cpu_is_u5500()) 121 if (cpu_is_u8500())
124 backupram = __io_address(U5500_BACKUPRAM0_BASE);
125 else if (cpu_is_u8500())
126 backupram = __io_address(U8500_BACKUPRAM0_BASE); 122 backupram = __io_address(U8500_BACKUPRAM0_BASE);
127 else 123 else
128 ux500_unknown_soc(); 124 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
deleted file mode 100644
index cb2110c32858..000000000000
--- a/arch/arm/mach-ux500/ste-dma40-db5500.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * DB5500-SoC-specific configuration for DMA40
8 */
9
10#ifndef STE_DMA40_DB5500_H
11#define STE_DMA40_DB5500_H
12
13#define DB5500_DMA_NR_DEV 64
14
15enum dma_src_dev_type {
16 DB5500_DMA_DEV0_SPI0_RX = 0,
17 DB5500_DMA_DEV1_SPI1_RX = 1,
18 DB5500_DMA_DEV2_SPI2_RX = 2,
19 DB5500_DMA_DEV3_SPI3_RX = 3,
20 DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
21 DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
22 DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
23 DB5500_DMA_DEV7_IRDA_RFS = 7,
24 DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
25 DB5500_DMA_DEV9_MSP0_RX = 9,
26 DB5500_DMA_DEV10_MSP1_RX = 10,
27 DB5500_DMA_DEV11_MSP2_RX = 11,
28 DB5500_DMA_DEV12_UART0_RX = 12,
29 DB5500_DMA_DEV13_UART1_RX = 13,
30 DB5500_DMA_DEV14_UART2_RX = 14,
31 DB5500_DMA_DEV15_UART3_RX = 15,
32 DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
33 DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
34 DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
35 DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
36 DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
37 DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
38 DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
39 DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
40 DB5500_DMA_DEV24_SDMMC0_RX = 24,
41 DB5500_DMA_DEV25_SDMMC1_RX = 25,
42 DB5500_DMA_DEV26_SDMMC2_RX = 26,
43 DB5500_DMA_DEV27_SDMMC3_RX = 27,
44 DB5500_DMA_DEV28_SDMMC4_RX = 28,
45 /* 29 - 32 not used */
46 DB5500_DMA_DEV33_SDMMC0_RX = 33,
47 DB5500_DMA_DEV34_SDMMC1_RX = 34,
48 DB5500_DMA_DEV35_SDMMC2_RX = 35,
49 DB5500_DMA_DEV36_SDMMC3_RX = 36,
50 DB5500_DMA_DEV37_SDMMC4_RX = 37,
51 DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
52 DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
53 DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
54 DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
55 DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
56 DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
57 DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
58 DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
59 /* 46 not used */
60 DB5500_DMA_DEV47_MCDE_RX = 47,
61 DB5500_DMA_DEV48_CRYPTO1_RX = 48,
62 /* 49, 50 not used */
63 DB5500_DMA_DEV49_I2C1_RX = 51,
64 DB5500_DMA_DEV50_I2C3_RX = 52,
65 DB5500_DMA_DEV51_I2C2_RX = 53,
66 /* 54 - 60 not used */
67 DB5500_DMA_DEV61_CRYPTO0_RX = 61,
68 /* 62, 63 not used */
69};
70
71enum dma_dest_dev_type {
72 DB5500_DMA_DEV0_SPI0_TX = 0,
73 DB5500_DMA_DEV1_SPI1_TX = 1,
74 DB5500_DMA_DEV2_SPI2_TX = 2,
75 DB5500_DMA_DEV3_SPI3_TX = 3,
76 DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
77 DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
78 DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
79 DB5500_DMA_DEV7_IRRC_TX = 7,
80 DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
81 DB5500_DMA_DEV9_MSP0_TX = 9,
82 DB5500_DMA_DEV10_MSP1_TX = 10,
83 DB5500_DMA_DEV11_MSP2_TX = 11,
84 DB5500_DMA_DEV12_UART0_TX = 12,
85 DB5500_DMA_DEV13_UART1_TX = 13,
86 DB5500_DMA_DEV14_UART2_TX = 14,
87 DB5500_DMA_DEV15_UART3_TX = 15,
88 DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
89 DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
90 DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
91 DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
92 DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
93 DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
94 DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
95 DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
96 DB5500_DMA_DEV24_SDMMC0_TX = 24,
97 DB5500_DMA_DEV25_SDMMC1_TX = 25,
98 DB5500_DMA_DEV26_SDMMC2_TX = 26,
99 DB5500_DMA_DEV27_SDMMC3_TX = 27,
100 DB5500_DMA_DEV28_SDMMC4_TX = 28,
101 /* 29 - 31 not used */
102 DB5500_DMA_DEV32_FSMC_TX = 32,
103 DB5500_DMA_DEV33_SDMMC0_TX = 33,
104 DB5500_DMA_DEV34_SDMMC1_TX = 34,
105 DB5500_DMA_DEV35_SDMMC2_TX = 35,
106 DB5500_DMA_DEV36_SDMMC3_TX = 36,
107 DB5500_DMA_DEV37_SDMMC4_TX = 37,
108 DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
109 DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
110 DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
111 DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
112 DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
113 DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
114 DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
115 DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
116 /* 46 not used */
117 DB5500_DMA_DEV47_STM_TX = 47,
118 DB5500_DMA_DEV48_CRYPTO1_TX = 48,
119 DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
120 DB5500_DMA_DEV50_HASH1_TX = 50,
121 DB5500_DMA_DEV51_I2C1_TX = 51,
122 DB5500_DMA_DEV52_I2C3_TX = 52,
123 DB5500_DMA_DEV53_I2C2_TX = 53,
124 /* 54, 55 not used */
125 DB5500_DMA_MEMCPY_TX_1 = 56,
126 DB5500_DMA_MEMCPY_TX_2 = 57,
127 DB5500_DMA_MEMCPY_TX_3 = 58,
128 DB5500_DMA_MEMCPY_TX_4 = 59,
129 DB5500_DMA_MEMCPY_TX_5 = 60,
130 DB5500_DMA_DEV61_CRYPTO0_TX = 61,
131 DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
132 DB5500_DMA_DEV63_HASH0_TX = 63,
133};
134
135#endif
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index d37df98b5c32..52e55337aa9b 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -18,8 +18,6 @@
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20#ifdef CONFIG_HAVE_ARM_TWD 20#ifdef CONFIG_HAVE_ARM_TWD
21static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
22 U5500_TWD_BASE, IRQ_LOCALTIMER);
23static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, 21static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
24 U8500_TWD_BASE, IRQ_LOCALTIMER); 22 U8500_TWD_BASE, IRQ_LOCALTIMER);
25 23
@@ -28,8 +26,8 @@ static void __init ux500_twd_init(void)
28 struct twd_local_timer *twd_local_timer; 26 struct twd_local_timer *twd_local_timer;
29 int err; 27 int err;
30 28
31 twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer : 29 /* Use this to switch local timer base if changed in new ASICs */
32 &u8500_twd_local_timer; 30 twd_local_timer = &u8500_twd_local_timer;
33 31
34 if (of_have_populated_dt()) 32 if (of_have_populated_dt())
35 twd_local_timer_of_register(); 33 twd_local_timer_of_register();
@@ -48,10 +46,7 @@ static void __init ux500_timer_init(void)
48 void __iomem *mtu_timer_base; 46 void __iomem *mtu_timer_base;
49 void __iomem *prcmu_timer_base; 47 void __iomem *prcmu_timer_base;
50 48
51 if (cpu_is_u5500()) { 49 if (cpu_is_u8500()) {
52 mtu_timer_base = __io_address(U5500_MTU0_BASE);
53 prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
54 } else if (cpu_is_u8500()) {
55 mtu_timer_base = __io_address(U8500_MTU0_BASE); 50 mtu_timer_base = __io_address(U8500_MTU0_BASE);
56 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); 51 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
57 } else { 52 } else {
@@ -70,7 +65,7 @@ static void __init ux500_timer_init(void)
70 * depending on delay which is not yet calibrated. RTC-RTT is in the 65 * depending on delay which is not yet calibrated. RTC-RTT is in the
71 * always-on powerdomain and is used as clockevent instead of twd when 66 * always-on powerdomain and is used as clockevent instead of twd when
72 * sleeping. 67 * sleeping.
73 * The PRCMU timer 4(3 for DB5500) register a clocksource and 68 * The PRCMU timer 4 register a clocksource and
74 * sched_clock with higher rating then MTU since is always-on. 69 * sched_clock with higher rating then MTU since is always-on.
75 * 70 *
76 */ 71 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 12:48:51 -0500