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-rw-r--r--arch/arm/mach-ux500/Kconfig41
-rw-r--r--arch/arm/mach-ux500/Makefile6
-rw-r--r--arch/arm/mach-ux500/board-mop500.c134
-rw-r--r--arch/arm/mach-ux500/board-u5500.c41
-rw-r--r--arch/arm/mach-ux500/clock.c501
-rw-r--r--arch/arm/mach-ux500/clock.h125
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c50
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c (renamed from arch/arm/mach-ux500/cpu-u8500.c)55
-rw-r--r--arch/arm/mach-ux500/cpu.c99
-rw-r--r--arch/arm/mach-ux500/devices-db5500.c46
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c107
-rw-r--r--arch/arm/mach-ux500/devices.c88
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h103
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h135
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h29
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S2
-rw-r--r--arch/arm/mach-ux500/include/mach/gpio.h50
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h197
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h9
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h24
-rw-r--r--arch/arm/mach-ux500/platsmp.c13
22 files changed, 1575 insertions, 292 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 03625d744857..6625e5bbf4d6 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -1,15 +1,42 @@
1menu "ST-Ericsson platform type" 1if ARCH_U8500
2 depends on ARCH_U8500
3 2
4comment "ST-Ericsson Multicore Mobile Platforms" 3config UX500_SOC_COMMON
5 4 bool
6config MACH_U8500_MOP
7 bool "U8500 Early Development platform"
8 default y 5 default y
9 select ARM_GIC 6 select ARM_GIC
10 select HAS_MTU 7 select HAS_MTU
8 select NOMADIK_GPIO
9
10config UX500_SOC_DB8500
11 bool
12
13config UX500_SOC_DB5500
14 bool
15
16choice
17 prompt "Ux500 target platform"
18 default MACH_U8500_MOP
19
20config MACH_U8500_MOP
21 bool "U8500 Development platform"
22 select UX500_SOC_DB8500
11 help 23 help
12 Include support for mop500 development platform 24 Include support for mop500 development platform
13 based on U8500 architecture. The platform is based 25 based on U8500 architecture. The platform is based
14 on early drop silicon version of 8500. 26 on early drop silicon version of 8500.
15endmenu 27
28config MACH_U5500
29 bool "U5500 Development platform"
30 select UX500_SOC_DB5500
31 help
32 Include support for the U5500 development platform.
33endchoice
34
35config UX500_DEBUG_UART
36 int "Ux500 UART to use for low-level debug"
37 default 2
38 help
39 Choose the UART on which kernel low-level debug messages should be
40 output.
41
42endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 95e6e24c0042..c7bc4199e3a8 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,7 +2,9 @@
2# Makefile for the linux kernel, U8500 machine. 2# Makefile for the linux kernel, U8500 machine.
3# 3#
4 4
5obj-y := clock.o 5obj-y := clock.o cpu.o devices.o
6obj-$(CONFIG_ARCH_U8500) += cpu-u8500.o 6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
7obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o 8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o
9obj-$(CONFIG_MACH_U5500) += board-u5500.o
8obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o 10obj-$(CONFIG_SMP) += platsmp.o headsmp.o localtimer.o
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 803aec1d6728..072196c57263 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,37 +17,14 @@
17#include <linux/amba/pl022.h> 17#include <linux/amba/pl022.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19 19
20#include <asm/localtimer.h>
21#include <asm/mach-types.h> 20#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
23 22
24#include <plat/mtu.h>
25#include <plat/i2c.h> 23#include <plat/i2c.h>
26 24
27#include <mach/hardware.h> 25#include <mach/hardware.h>
28#include <mach/setup.h> 26#include <mach/setup.h>
29 27#include <mach/devices.h>
30#define __MEM_4K_RESOURCE(x) \
31 .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
32
33/* These are active devices on this board */
34static struct amba_device uart0_device = {
35 .dev = { .init_name = "uart0" },
36 __MEM_4K_RESOURCE(U8500_UART0_BASE),
37 .irq = {IRQ_UART0, NO_IRQ},
38};
39
40static struct amba_device uart1_device = {
41 .dev = { .init_name = "uart1" },
42 __MEM_4K_RESOURCE(U8500_UART1_BASE),
43 .irq = {IRQ_UART1, NO_IRQ},
44};
45
46static struct amba_device uart2_device = {
47 .dev = { .init_name = "uart2" },
48 __MEM_4K_RESOURCE(U8500_UART2_BASE),
49 .irq = {IRQ_UART2, NO_IRQ},
50};
51 28
52static void ab4500_spi_cs_control(u32 command) 29static void ab4500_spi_cs_control(u32 command)
53{ 30{
@@ -93,55 +70,8 @@ static struct pl022_ssp_controller ssp0_platform_data = {
93 .num_chipselect = 5, 70 .num_chipselect = 5,
94}; 71};
95 72
96static struct amba_device pl022_device = {
97 .dev = {
98 .coherent_dma_mask = ~0,
99 .init_name = "pl022",
100 .platform_data = &ssp0_platform_data,
101 },
102 .res = {
103 .start = U8500_SSP0_BASE,
104 .end = U8500_SSP0_BASE + SZ_4K - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 .irq = {IRQ_SSP0, NO_IRQ },
108 /* ST-Ericsson modified id */
109 .periphid = SSP_PER_ID,
110};
111
112static struct amba_device pl031_device = {
113 .dev = {
114 .init_name = "pl031",
115 },
116 .res = {
117 .start = U8500_RTC_BASE,
118 .end = U8500_RTC_BASE + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 },
121 .irq = {IRQ_RTC_RTT, NO_IRQ},
122};
123
124#define U8500_I2C_RESOURCES(id, size) \
125static struct resource u8500_i2c_resources_##id[] = { \
126 [0] = { \
127 .start = U8500_I2C##id##_BASE, \
128 .end = U8500_I2C##id##_BASE + size - 1, \
129 .flags = IORESOURCE_MEM, \
130 }, \
131 [1] = { \
132 .start = IRQ_I2C##id, \
133 .end = IRQ_I2C##id, \
134 .flags = IORESOURCE_IRQ \
135 } \
136}
137
138U8500_I2C_RESOURCES(0, SZ_4K);
139U8500_I2C_RESOURCES(1, SZ_4K);
140U8500_I2C_RESOURCES(2, SZ_4K);
141U8500_I2C_RESOURCES(3, SZ_4K);
142
143#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \ 73#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
144static struct nmk_i2c_controller u8500_i2c_##id = { \ 74static struct nmk_i2c_controller u8500_i2c##id##_data = { \
145 /* \ 75 /* \
146 * slave data setup time, which is \ 76 * slave data setup time, which is \
147 * 250 ns,100ns,10ns which is 14,6,2 \ 77 * 250 ns,100ns,10ns which is 14,6,2 \
@@ -169,58 +99,32 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
169U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); 99U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
170U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD); 100U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
171 101
172#define U8500_I2C_PDEVICE(cid) \
173static struct platform_device i2c_controller##cid = { \
174 .name = "nmk-i2c", \
175 .id = cid, \
176 .num_resources = 2, \
177 .resource = u8500_i2c_resources_##cid, \
178 .dev = { \
179 .platform_data = &u8500_i2c_##cid \
180 } \
181}
182
183U8500_I2C_PDEVICE(0);
184U8500_I2C_PDEVICE(1);
185U8500_I2C_PDEVICE(2);
186U8500_I2C_PDEVICE(3);
187
188static struct amba_device *amba_devs[] __initdata = { 102static struct amba_device *amba_devs[] __initdata = {
189 &uart0_device, 103 &ux500_uart0_device,
190 &uart1_device, 104 &ux500_uart1_device,
191 &uart2_device, 105 &ux500_uart2_device,
192 &pl022_device, 106 &u8500_ssp0_device,
193 &pl031_device,
194}; 107};
195 108
196/* add any platform devices here - TODO */ 109/* add any platform devices here - TODO */
197static struct platform_device *platform_devs[] __initdata = { 110static struct platform_device *platform_devs[] __initdata = {
198 &i2c_controller0, 111 &u8500_i2c0_device,
199 &i2c_controller1, 112 &ux500_i2c1_device,
200 &i2c_controller2, 113 &ux500_i2c2_device,
201 &i2c_controller3, 114 &ux500_i2c3_device,
202};
203
204static void __init u8500_timer_init(void)
205{
206#ifdef CONFIG_LOCAL_TIMERS
207 /* Setup the local timer base */
208 twd_base = __io_address(U8500_TWD_BASE);
209#endif
210 /* Setup the MTU base */
211 mtu_base = __io_address(U8500_MTU0_BASE);
212
213 nmdk_timer_init();
214}
215
216static struct sys_timer u8500_timer = {
217 .init = u8500_timer_init,
218}; 115};
219 116
220static void __init u8500_init_machine(void) 117static void __init u8500_init_machine(void)
221{ 118{
222 int i; 119 int i;
223 120
121 u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
122 ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
123 ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
124 ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data;
125
126 u8500_ssp0_device.dev.platform_data = &ssp0_platform_data;
127
224 /* Register the active AMBA devices on this board */ 128 /* Register the active AMBA devices on this board */
225 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) 129 for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
226 amba_device_register(amba_devs[i], &iomem_resource); 130 amba_device_register(amba_devs[i], &iomem_resource);
@@ -239,8 +143,8 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
239 .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc, 143 .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
240 .boot_params = 0x100, 144 .boot_params = 0x100,
241 .map_io = u8500_map_io, 145 .map_io = u8500_map_io,
242 .init_irq = u8500_init_irq, 146 .init_irq = ux500_init_irq,
243 /* we re-use nomadik timer here */ 147 /* we re-use nomadik timer here */
244 .timer = &u8500_timer, 148 .timer = &ux500_timer,
245 .init_machine = u8500_init_machine, 149 .init_machine = u8500_init_machine,
246MACHINE_END 150MACHINE_END
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
new file mode 100644
index 000000000000..4430e69cf538
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/amba/bus.h>
11#include <linux/gpio.h>
12
13#include <asm/mach/arch.h>
14#include <asm/mach-types.h>
15
16#include <mach/hardware.h>
17#include <mach/devices.h>
18#include <mach/setup.h>
19
20static struct amba_device *amba_board_devs[] __initdata = {
21 &ux500_uart0_device,
22 &ux500_uart1_device,
23 &ux500_uart2_device,
24};
25
26static void __init u5500_init_machine(void)
27{
28 u5500_init_devices();
29
30 amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs));
31}
32
33MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
34 .phys_io = UX500_UART0_BASE,
35 .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc,
36 .boot_params = 0x00000100,
37 .map_io = u5500_map_io,
38 .init_irq = ux500_init_irq,
39 .timer = &ux500_timer,
40 .init_machine = u5500_init_machine,
41MACHINE_END
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 8359a73d0041..1b2c9890e8b4 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 ST-Ericsson 2 * Copyright (C) 2009 ST-Ericsson
3 * heavily based on realview platform 3 * Copyright (C) 2009 STMicroelectronics
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -12,33 +12,130 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/mutex.h> 15#include <linux/io.h>
16 16
17#include <asm/clkdev.h> 17#include <asm/clkdev.h>
18 18
19/* currently the clk structure 19#include <mach/hardware.h>
20 * just supports rate. This would 20#include "clock.h"
21 * be extended as and when new devices are 21
22 * added - TODO 22#define PRCC_PCKEN 0x00
23 */ 23#define PRCC_PCKDIS 0x04
24struct clk { 24#define PRCC_KCKEN 0x08
25 unsigned long rate; 25#define PRCC_KCKDIS 0x0C
26}; 26
27#define PRCM_YYCLKEN0_MGT_SET 0x510
28#define PRCM_YYCLKEN1_MGT_SET 0x514
29#define PRCM_YYCLKEN0_MGT_CLR 0x518
30#define PRCM_YYCLKEN1_MGT_CLR 0x51C
31#define PRCM_YYCLKEN0_MGT_VAL 0x520
32#define PRCM_YYCLKEN1_MGT_VAL 0x524
33
34#define PRCM_SVAMMDSPCLK_MGT 0x008
35#define PRCM_SIAMMDSPCLK_MGT 0x00C
36#define PRCM_SGACLK_MGT 0x014
37#define PRCM_UARTCLK_MGT 0x018
38#define PRCM_MSP02CLK_MGT 0x01C
39#define PRCM_MSP1CLK_MGT 0x288
40#define PRCM_I2CCLK_MGT 0x020
41#define PRCM_SDMMCCLK_MGT 0x024
42#define PRCM_SLIMCLK_MGT 0x028
43#define PRCM_PER1CLK_MGT 0x02C
44#define PRCM_PER2CLK_MGT 0x030
45#define PRCM_PER3CLK_MGT 0x034
46#define PRCM_PER5CLK_MGT 0x038
47#define PRCM_PER6CLK_MGT 0x03C
48#define PRCM_PER7CLK_MGT 0x040
49#define PRCM_LCDCLK_MGT 0x044
50#define PRCM_BMLCLK_MGT 0x04C
51#define PRCM_HSITXCLK_MGT 0x050
52#define PRCM_HSIRXCLK_MGT 0x054
53#define PRCM_HDMICLK_MGT 0x058
54#define PRCM_APEATCLK_MGT 0x05C
55#define PRCM_APETRACECLK_MGT 0x060
56#define PRCM_MCDECLK_MGT 0x064
57#define PRCM_IPI2CCLK_MGT 0x068
58#define PRCM_DSIALTCLK_MGT 0x06C
59#define PRCM_DMACLK_MGT 0x074
60#define PRCM_B2R2CLK_MGT 0x078
61#define PRCM_TVCLK_MGT 0x07C
62#define PRCM_UNIPROCLK_MGT 0x278
63#define PRCM_SSPCLK_MGT 0x280
64#define PRCM_RNGCLK_MGT 0x284
65#define PRCM_UICCCLK_MGT 0x27C
66
67#define PRCM_MGT_ENABLE (1 << 8)
68
69static DEFINE_SPINLOCK(clocks_lock);
70
71static void __clk_enable(struct clk *clk)
72{
73 if (clk->enabled++ == 0) {
74 if (clk->parent_cluster)
75 __clk_enable(clk->parent_cluster);
76
77 if (clk->parent_periph)
78 __clk_enable(clk->parent_periph);
79
80 if (clk->ops && clk->ops->enable)
81 clk->ops->enable(clk);
82 }
83}
27 84
28int clk_enable(struct clk *clk) 85int clk_enable(struct clk *clk)
29{ 86{
87 unsigned long flags;
88
89 spin_lock_irqsave(&clocks_lock, flags);
90 __clk_enable(clk);
91 spin_unlock_irqrestore(&clocks_lock, flags);
92
30 return 0; 93 return 0;
31} 94}
32EXPORT_SYMBOL(clk_enable); 95EXPORT_SYMBOL(clk_enable);
33 96
97static void __clk_disable(struct clk *clk)
98{
99 if (--clk->enabled == 0) {
100 if (clk->ops && clk->ops->disable)
101 clk->ops->disable(clk);
102
103 if (clk->parent_periph)
104 __clk_disable(clk->parent_periph);
105
106 if (clk->parent_cluster)
107 __clk_disable(clk->parent_cluster);
108 }
109}
110
34void clk_disable(struct clk *clk) 111void clk_disable(struct clk *clk)
35{ 112{
113 unsigned long flags;
114
115 WARN_ON(!clk->enabled);
116
117 spin_lock_irqsave(&clocks_lock, flags);
118 __clk_disable(clk);
119 spin_unlock_irqrestore(&clocks_lock, flags);
36} 120}
37EXPORT_SYMBOL(clk_disable); 121EXPORT_SYMBOL(clk_disable);
38 122
39unsigned long clk_get_rate(struct clk *clk) 123unsigned long clk_get_rate(struct clk *clk)
40{ 124{
41 return clk->rate; 125 unsigned long rate;
126
127 if (clk->ops && clk->ops->get_rate)
128 return clk->ops->get_rate(clk);
129
130 rate = clk->rate;
131 if (!rate) {
132 if (clk->parent_periph)
133 rate = clk_get_rate(clk->parent_periph);
134 else if (clk->parent_cluster)
135 rate = clk_get_rate(clk->parent_cluster);
136 }
137
138 return rate;
42} 139}
43EXPORT_SYMBOL(clk_get_rate); 140EXPORT_SYMBOL(clk_get_rate);
44 141
@@ -56,37 +153,373 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
56} 153}
57EXPORT_SYMBOL(clk_set_rate); 154EXPORT_SYMBOL(clk_set_rate);
58 155
59/* ssp clock */ 156static void clk_prcmu_enable(struct clk *clk)
60static struct clk ssp_clk = { 157{
61 .rate = 48000000, 158 void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
159 + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
160
161 writel(1 << clk->prcmu_cg_bit, cg_set_reg);
162}
163
164static void clk_prcmu_disable(struct clk *clk)
165{
166 void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
167 + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
168
169 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
170}
171
172/* ED doesn't have the combined set/clr registers */
173static void clk_prcmu_ed_enable(struct clk *clk)
174{
175 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
176 + clk->prcmu_cg_mgt;
177
178 writel(readl(addr) | PRCM_MGT_ENABLE, addr);
179}
180
181static void clk_prcmu_ed_disable(struct clk *clk)
182{
183 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
184 + clk->prcmu_cg_mgt;
185
186 writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
187}
188
189static struct clkops clk_prcmu_ops = {
190 .enable = clk_prcmu_enable,
191 .disable = clk_prcmu_disable,
62}; 192};
63 193
64/* fixed clock */ 194static unsigned int clkrst_base[] = {
65static struct clk f38_clk = { 195 [1] = U8500_CLKRST1_BASE,
66 .rate = 38400000, 196 [2] = U8500_CLKRST2_BASE,
197 [3] = U8500_CLKRST3_BASE,
198 [5] = U8500_CLKRST5_BASE,
199 [6] = U8500_CLKRST6_BASE,
200 [7] = U8500_CLKRST7_BASE_ED,
67}; 201};
68 202
69static struct clk_lookup lookups[] = { 203static void clk_prcc_enable(struct clk *clk)
70 { 204{
71 /* UART0 */ 205 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
72 .dev_id = "uart0", 206
73 .clk = &f38_clk, 207 if (clk->prcc_kernel != -1)
74 }, { /* UART1 */ 208 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
75 .dev_id = "uart1", 209
76 .clk = &f38_clk, 210 if (clk->prcc_bus != -1)
77 }, { /* UART2 */ 211 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
78 .dev_id = "uart2", 212}
79 .clk = &f38_clk, 213
80 }, { /* SSP */ 214static void clk_prcc_disable(struct clk *clk)
81 .dev_id = "pl022", 215{
82 .clk = &ssp_clk, 216 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
83 } 217
218 if (clk->prcc_bus != -1)
219 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
220
221 if (clk->prcc_kernel != -1)
222 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
223}
224
225static struct clkops clk_prcc_ops = {
226 .enable = clk_prcc_enable,
227 .disable = clk_prcc_disable,
228};
229
230static struct clk clk_32khz = {
231 .rate = 32000,
232};
233
234/*
235 * PRCMU level clock gating
236 */
237
238/* Bank 0 */
239static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
240static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
241static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
242static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
243static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
244static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
245static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
246static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000);
247static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
248static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
249static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
250static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
251static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
252static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
253static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
254static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
255static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
256static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
257static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
258static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
259static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
260static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
261static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
262static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
263static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
264static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
265static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
266static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
267static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
268static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
269
270/* Bank 1 */
271static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
272static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
273
274/*
275 * PRCC level clock gating
276 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
277 */
278
279/* Peripheral Cluster #1 */
280static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
281static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
282static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
283static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
284static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
285static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
286static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
287static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
288static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
289static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
290static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
291static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
292static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
293
294/* Peripheral Cluster #2 */
295
296static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
297static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
298static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
299static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
300static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
301static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
302static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
303static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
304static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
305static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
306static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
307static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
308
309static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
310static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
311static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
312static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
313static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
314static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
315static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
316static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
317static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
318static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
319static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
320static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
321
322/* Peripheral Cluster #3 */
323static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
324static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
325static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
326static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
327static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
328static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
329static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
330static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
331static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
332static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
333static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
334
335/* Peripheral Cluster #4 is in the always on domain */
336
337/* Peripheral Cluster #5 */
338static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
339static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
340static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
341
342/* Peripheral Cluster #6 */
343
344static DEFINE_PRCC_CLK(6, mtu1_v1, 8, -1, NULL);
345static DEFINE_PRCC_CLK(6, mtu0_v1, 7, -1, NULL);
346static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
347static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
348static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
349static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
350static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
351static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
352static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
353static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
354static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
355static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
356
357/* Peripheral Cluster #7 */
358
359static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
360static DEFINE_PRCC_CLK(7, mtu1_ed, 3, -1, NULL);
361static DEFINE_PRCC_CLK(7, mtu0_ed, 2, -1, NULL);
362static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
363static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
364
365static struct clk_lookup u8500_common_clks[] = {
366 /* Peripheral Cluster #1 */
367 CLK(gpio0, "gpio.0", NULL),
368 CLK(gpio0, "gpio.1", NULL),
369 CLK(slimbus0, "slimbus0", NULL),
370 CLK(i2c2, "nmk-i2c.2", NULL),
371 CLK(sdi0, "sdi0", NULL),
372 CLK(msp0, "msp0", NULL),
373 CLK(i2c1, "nmk-i2c.1", NULL),
374 CLK(uart1, "uart1", NULL),
375 CLK(uart0, "uart0", NULL),
376
377 /* Peripheral Cluster #3 */
378 CLK(gpio2, "gpio.2", NULL),
379 CLK(gpio2, "gpio.3", NULL),
380 CLK(gpio2, "gpio.4", NULL),
381 CLK(gpio2, "gpio.5", NULL),
382 CLK(sdi5, "sdi5", NULL),
383 CLK(uart2, "uart2", NULL),
384 CLK(ske, "ske", NULL),
385 CLK(sdi2, "sdi2", NULL),
386 CLK(i2c0, "nmk-i2c.0", NULL),
387 CLK(fsmc, "fsmc", NULL),
388
389 /* Peripheral Cluster #5 */
390 CLK(gpio3, "gpio.8", NULL),
391
392 /* Peripheral Cluster #6 */
393 CLK(hash1, "hash1", NULL),
394 CLK(pka, "pka", NULL),
395 CLK(hash0, "hash0", NULL),
396 CLK(cryp0, "cryp0", NULL),
397
398 /* PRCMU level clock gating */
399
400 /* Bank 0 */
401 CLK(svaclk, "sva", NULL),
402 CLK(siaclk, "sia", NULL),
403 CLK(sgaclk, "sga", NULL),
404 CLK(slimclk, "slim", NULL),
405 CLK(lcdclk, "lcd", NULL),
406 CLK(bmlclk, "bml", NULL),
407 CLK(hsitxclk, "stm-hsi.0", NULL),
408 CLK(hsirxclk, "stm-hsi.1", NULL),
409 CLK(hdmiclk, "hdmi", NULL),
410 CLK(apeatclk, "apeat", NULL),
411 CLK(apetraceclk, "apetrace", NULL),
412 CLK(mcdeclk, "mcde", NULL),
413 CLK(ipi2clk, "ipi2", NULL),
414 CLK(dmaclk, "dma40", NULL),
415 CLK(b2r2clk, "b2r2", NULL),
416 CLK(tvclk, "tv", NULL),
417};
418
419static struct clk_lookup u8500_ed_clks[] = {
420 /* Peripheral Cluster #1 */
421 CLK(spi3_ed, "spi3", NULL),
422 CLK(msp1_ed, "msp1", NULL),
423
424 /* Peripheral Cluster #2 */
425 CLK(gpio1_ed, "gpio.6", NULL),
426 CLK(gpio1_ed, "gpio.7", NULL),
427 CLK(ssitx_ed, "ssitx", NULL),
428 CLK(ssirx_ed, "ssirx", NULL),
429 CLK(spi0_ed, "spi0", NULL),
430 CLK(sdi3_ed, "sdi3", NULL),
431 CLK(sdi1_ed, "sdi1", NULL),
432 CLK(msp2_ed, "msp2", NULL),
433 CLK(sdi4_ed, "sdi4", NULL),
434 CLK(pwl_ed, "pwl", NULL),
435 CLK(spi1_ed, "spi1", NULL),
436 CLK(spi2_ed, "spi2", NULL),
437 CLK(i2c3_ed, "nmk-i2c.3", NULL),
438
439 /* Peripheral Cluster #3 */
440 CLK(ssp1_ed, "ssp1", NULL),
441 CLK(ssp0_ed, "ssp0", NULL),
442
443 /* Peripheral Cluster #5 */
444 CLK(usb_ed, "musb_hdrc.0", "usb"),
445
446 /* Peripheral Cluster #6 */
447 CLK(dmc_ed, "dmc", NULL),
448 CLK(cryp1_ed, "cryp1", NULL),
449 CLK(rng_ed, "rng", NULL),
450
451 /* Peripheral Cluster #7 */
452 CLK(tzpc0_ed, "tzpc0", NULL),
453 CLK(mtu1_ed, "mtu1", NULL),
454 CLK(mtu0_ed, "mtu0", NULL),
455 CLK(wdg_ed, "wdg", NULL),
456 CLK(cfgreg_ed, "cfgreg", NULL),
457};
458
459static struct clk_lookup u8500_v1_clks[] = {
460 /* Peripheral Cluster #1 */
461 CLK(i2c4, "nmk-i2c.4", NULL),
462 CLK(spi3_v1, "spi3", NULL),
463 CLK(msp1_v1, "msp1", NULL),
464
465 /* Peripheral Cluster #2 */
466 CLK(gpio1_v1, "gpio.6", NULL),
467 CLK(gpio1_v1, "gpio.7", NULL),
468 CLK(ssitx_v1, "ssitx", NULL),
469 CLK(ssirx_v1, "ssirx", NULL),
470 CLK(spi0_v1, "spi0", NULL),
471 CLK(sdi3_v1, "sdi3", NULL),
472 CLK(sdi1_v1, "sdi1", NULL),
473 CLK(msp2_v1, "msp2", NULL),
474 CLK(sdi4_v1, "sdi4", NULL),
475 CLK(pwl_v1, "pwl", NULL),
476 CLK(spi1_v1, "spi1", NULL),
477 CLK(spi2_v1, "spi2", NULL),
478 CLK(i2c3_v1, "nmk-i2c.3", NULL),
479
480 /* Peripheral Cluster #3 */
481 CLK(ssp1_v1, "ssp1", NULL),
482 CLK(ssp0_v1, "ssp0", NULL),
483
484 /* Peripheral Cluster #5 */
485 CLK(usb_v1, "musb_hdrc.0", "usb"),
486
487 /* Peripheral Cluster #6 */
488 CLK(mtu1_v1, "mtu1", NULL),
489 CLK(mtu0_v1, "mtu0", NULL),
490 CLK(cfgreg_v1, "cfgreg", NULL),
491 CLK(hash1, "hash1", NULL),
492 CLK(unipro_v1, "unipro", NULL),
493 CLK(rng_v1, "rng", NULL),
494
495 /* PRCMU level clock gating */
496
497 /* Bank 0 */
498 CLK(uniproclk, "uniproclk", NULL),
499 CLK(dsialtclk, "dsialt", NULL),
500
501 /* Bank 1 */
502 CLK(rngclk, "rng", NULL),
503 CLK(uiccclk, "uicc", NULL),
84}; 504};
85 505
86static int __init clk_init(void) 506static int __init clk_init(void)
87{ 507{
88 /* register the clock lookups */ 508 if (cpu_is_u8500ed()) {
89 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 509 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
510 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
511 } else if (cpu_is_u5500()) {
512 /* Clock tree for U5500 not implemented yet */
513 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
514 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
515 }
516
517 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
518 if (cpu_is_u8500ed())
519 clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
520 else
521 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
522
90 return 0; 523 return 0;
91} 524}
92arch_initcall(clk_init); 525arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
new file mode 100644
index 000000000000..e4f99b65026f
--- /dev/null
+++ b/arch/arm/mach-ux500/clock.h
@@ -0,0 +1,125 @@
1/*
2 * Copyright (C) 2010 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10/**
11 * struct clkops - ux500 clock operations
12 * @enable: function to enable the clock
13 * @disable: function to disable the clock
14 * @get_rate: function to get the current clock rate
15 *
16 * This structure contains function pointers to functions that will be used to
17 * control the clock. All of these functions are optional. If get_rate is
18 * NULL, the rate in the struct clk will be used.
19 */
20struct clkops {
21 void (*enable) (struct clk *);
22 void (*disable) (struct clk *);
23 unsigned long (*get_rate) (struct clk *);
24};
25
26/**
27 * struct clk - ux500 clock structure
28 * @ops: pointer to clkops struct used to control this clock
29 * @name: name, for debugging
30 * @enabled: refcount. positive if enabled, zero if disabled
31 * @rate: fixed rate for clocks which don't implement
32 * ops->getrate
33 * @prcmu_cg_off: address offset of the combined enable/disable register
34 * (used on u8500v1)
35 * @prcmu_cg_bit: bit in the combined enable/disable register (used on
36 * u8500v1)
37 * @prcmu_cg_mgt: address of the enable/disable register (used on
38 * u8500ed)
39 * @cluster: peripheral cluster number
40 * @prcc_bus: bit for the bus clock in the peripheral's CLKRST
41 * @prcc_kernel: bit for the kernel clock in the peripheral's CLKRST.
42 * -1 if no kernel clock exists.
43 * @parent_cluster: pointer to parent's cluster clk struct
44 * @parent_periph: pointer to parent's peripheral clk struct
45 *
46 * Peripherals are organised into clusters, and each cluster has an associated
47 * bus clock. Some peripherals also have a parent peripheral clock.
48 *
49 * In order to enable a clock for a peripheral, we need to enable:
50 * (1) the parent cluster (bus) clock at the PRCMU level
51 * (2) the parent peripheral clock (if any) at the PRCMU level
52 * (3) the peripheral's bus & kernel clock at the PRCC level
53 *
54 * (1) and (2) are handled by defining clk structs (DEFINE_PRCMU_CLK) for each
55 * of the cluster and peripheral clocks, and hooking these as the parents of
56 * the individual peripheral clocks.
57 *
58 * (3) is handled by specifying the bits in the PRCC control registers required
59 * to enable these clocks and modifying them in the ->enable and
60 * ->disable callbacks of the peripheral clocks (DEFINE_PRCC_CLK).
61 *
62 * This structure describes both the PRCMU-level clocks and PRCC-level clocks.
63 * The prcmu_* fields are only used for the PRCMU clocks, and the cluster,
64 * prcc, and parent pointers are only used for the PRCC-level clocks.
65 */
66struct clk {
67 const struct clkops *ops;
68 const char *name;
69 unsigned int enabled;
70
71 unsigned long rate;
72 struct list_head list;
73
74 /* These three are only for PRCMU clks */
75
76 unsigned int prcmu_cg_off;
77 unsigned int prcmu_cg_bit;
78 unsigned int prcmu_cg_mgt;
79
80 /* The rest are only for PRCC clks */
81
82 int cluster;
83 unsigned int prcc_bus;
84 unsigned int prcc_kernel;
85
86 struct clk *parent_cluster;
87 struct clk *parent_periph;
88};
89
90#define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg) \
91struct clk clk_##_name = { \
92 .name = #_name, \
93 .ops = &clk_prcmu_ops, \
94 .prcmu_cg_off = _cg_off, \
95 .prcmu_cg_bit = _cg_bit, \
96 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
97 }
98
99#define DEFINE_PRCMU_CLK_RATE(_name, _cg_off, _cg_bit, _reg, _rate) \
100struct clk clk_##_name = { \
101 .name = #_name, \
102 .ops = &clk_prcmu_ops, \
103 .prcmu_cg_off = _cg_off, \
104 .prcmu_cg_bit = _cg_bit, \
105 .rate = _rate, \
106 .prcmu_cg_mgt = PRCM_##_reg##_MGT \
107 }
108
109#define DEFINE_PRCC_CLK(_pclust, _name, _bus_en, _kernel_en, _kernclk) \
110struct clk clk_##_name = { \
111 .name = #_name, \
112 .ops = &clk_prcc_ops, \
113 .cluster = _pclust, \
114 .prcc_bus = _bus_en, \
115 .prcc_kernel = _kernel_en, \
116 .parent_cluster = &clk_per##_pclust##clk, \
117 .parent_periph = _kernclk \
118 }
119
120#define CLK(_clk, _devname, _conname) \
121 { \
122 .clk = &clk_##_clk, \
123 .dev_id = _devname, \
124 .con_id = _conname, \
125 }
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
new file mode 100644
index 000000000000..6a3ac4539f16
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/amba/bus.h>
10#include <linux/io.h>
11
12#include <asm/mach/map.h>
13
14#include <mach/hardware.h>
15#include <mach/devices.h>
16#include <mach/setup.h>
17
18static struct map_desc u5500_io_desc[] __initdata = {
19 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
20 __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
21 __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
22 __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
23 __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
24};
25
26static struct platform_device *u5500_platform_devs[] __initdata = {
27 &u5500_gpio_devs[0],
28 &u5500_gpio_devs[1],
29 &u5500_gpio_devs[2],
30 &u5500_gpio_devs[3],
31 &u5500_gpio_devs[4],
32 &u5500_gpio_devs[5],
33 &u5500_gpio_devs[6],
34 &u5500_gpio_devs[7],
35};
36
37void __init u5500_map_io(void)
38{
39 ux500_map_io();
40
41 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
42}
43
44void __init u5500_init_devices(void)
45{
46 ux500_init_devices();
47
48 platform_add_devices(u5500_platform_devs,
49 ARRAY_SIZE(u5500_platform_devs));
50}
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 397bc1f9ed94..d04299f3b6b5 100644
--- a/arch/arm/mach-ux500/cpu-u8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -13,44 +13,55 @@
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/gpio.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/io.h>
17 19
18#include <asm/hardware/gic.h>
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
20#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/setup.h>
23#include <mach/devices.h>
21 24
22/* add any platform devices here - TODO */
23static struct platform_device *platform_devs[] __initdata = { 25static struct platform_device *platform_devs[] __initdata = {
24 /* yet to be added, add i2c0, gpio.. */ 26 &u8500_gpio_devs[0],
27 &u8500_gpio_devs[1],
28 &u8500_gpio_devs[2],
29 &u8500_gpio_devs[3],
30 &u8500_gpio_devs[4],
31 &u8500_gpio_devs[5],
32 &u8500_gpio_devs[6],
33 &u8500_gpio_devs[7],
34 &u8500_gpio_devs[8],
25}; 35};
26 36
27#define __IO_DEV_DESC(x, sz) { \
28 .virtual = IO_ADDRESS(x), \
29 .pfn = __phys_to_pfn(x), \
30 .length = sz, \
31 .type = MT_DEVICE, \
32}
33
34/* minimum static i/o mapping required to boot U8500 platforms */ 37/* minimum static i/o mapping required to boot U8500 platforms */
35static struct map_desc u8500_io_desc[] __initdata = { 38static struct map_desc u8500_io_desc[] __initdata = {
36 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K), 39 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
37 __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
38 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K), 41 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
42 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
43 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
44};
45
46static struct map_desc u8500ed_io_desc[] __initdata = {
47 __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
48 __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
49};
50
51static struct map_desc u8500v1_io_desc[] __initdata = {
39 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 52 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
40 __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
42 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
43}; 53};
44 54
45void __init u8500_map_io(void) 55void __init u8500_map_io(void)
46{ 56{
57 ux500_map_io();
58
47 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc)); 59 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
48}
49 60
50void __init u8500_init_irq(void) 61 if (cpu_is_u8500ed())
51{ 62 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
52 gic_dist_init(0, __io_address(U8500_GIC_DIST_BASE), 29); 63 else
53 gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE)); 64 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
54} 65}
55 66
56/* 67/*
@@ -58,6 +69,8 @@ void __init u8500_init_irq(void)
58 */ 69 */
59void __init u8500_init_devices(void) 70void __init u8500_init_devices(void)
60{ 71{
72 ux500_init_devices();
73
61 /* Register the platform devices */ 74 /* Register the platform devices */
62 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 75 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
63 76
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
new file mode 100644
index 000000000000..d81ad023963c
--- /dev/null
+++ b/arch/arm/mach-ux500/cpu.c
@@ -0,0 +1,99 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/amba/bus.h>
10#include <linux/io.h>
11#include <linux/clk.h>
12
13#include <asm/hardware/cache-l2x0.h>
14#include <asm/hardware/gic.h>
15#include <asm/mach/map.h>
16#include <asm/localtimer.h>
17
18#include <plat/mtu.h>
19#include <mach/hardware.h>
20#include <mach/setup.h>
21#include <mach/devices.h>
22
23#include "clock.h"
24
25static struct map_desc ux500_io_desc[] __initdata = {
26 __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
27 __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
28
29 __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
30 __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
31 __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
32 __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
33 __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
34
35 __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
36 __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
37 __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
38 __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
39 __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
40
41 __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
42 __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
43
44 __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
45};
46
47static struct amba_device *ux500_amba_devs[] __initdata = {
48 &ux500_pl031_device,
49};
50
51void __init ux500_map_io(void)
52{
53 iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
54}
55
56void __init ux500_init_devices(void)
57{
58 amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
59}
60
61void __init ux500_init_irq(void)
62{
63 gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
64 gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
65}
66
67#ifdef CONFIG_CACHE_L2X0
68static int ux500_l2x0_init(void)
69{
70 void __iomem *l2x0_base;
71
72 l2x0_base = __io_address(UX500_L2CC_BASE);
73
74 /* 64KB way size, 8 way associativity, force WA */
75 l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
76
77 return 0;
78}
79early_initcall(ux500_l2x0_init);
80#endif
81
82static void __init ux500_timer_init(void)
83{
84#ifdef CONFIG_LOCAL_TIMERS
85 /* Setup the local timer base */
86 twd_base = __io_address(UX500_TWD_BASE);
87#endif
88 /* Setup the MTU base */
89 if (cpu_is_u8500ed())
90 mtu_base = __io_address(U8500_MTU0_BASE_ED);
91 else
92 mtu_base = __io_address(UX500_MTU0_BASE);
93
94 nmdk_timer_init();
95}
96
97struct sys_timer ux500_timer = {
98 .init = ux500_timer_init,
99};
diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c
new file mode 100644
index 000000000000..33e5b56bebb6
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db5500.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/interrupt.h>
10#include <linux/gpio.h>
11
12#include <mach/hardware.h>
13#include <mach/devices.h>
14
15static struct nmk_gpio_platform_data u5500_gpio_data[] = {
16 GPIO_DATA("GPIO-0-31", 0),
17 GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */
18 GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */
19 GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */
20 GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */
21 GPIO_DATA("GPIO-160-191", 160),
22 GPIO_DATA("GPIO-192-223", 192),
23 GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */
24};
25
26static struct resource u5500_gpio_resources[] = {
27 GPIO_RESOURCE(0),
28 GPIO_RESOURCE(1),
29 GPIO_RESOURCE(2),
30 GPIO_RESOURCE(3),
31 GPIO_RESOURCE(4),
32 GPIO_RESOURCE(5),
33 GPIO_RESOURCE(6),
34 GPIO_RESOURCE(7),
35};
36
37struct platform_device u5500_gpio_devs[] = {
38 GPIO_DEVICE(0),
39 GPIO_DEVICE(1),
40 GPIO_DEVICE(2),
41 GPIO_DEVICE(3),
42 GPIO_DEVICE(4),
43 GPIO_DEVICE(5),
44 GPIO_DEVICE(6),
45 GPIO_DEVICE(7),
46};
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
new file mode 100644
index 000000000000..20334236afce
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/gpio.h>
13#include <linux/amba/bus.h>
14
15#include <mach/hardware.h>
16#include <mach/setup.h>
17
18static struct nmk_gpio_platform_data u8500_gpio_data[] = {
19 GPIO_DATA("GPIO-0-31", 0),
20 GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */
21 GPIO_DATA("GPIO-64-95", 64),
22 GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */
23 GPIO_DATA("GPIO-128-159", 128),
24 GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */
25 GPIO_DATA("GPIO-192-223", 192),
26 GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */
27 GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */
28};
29
30static struct resource u8500_gpio_resources[] = {
31 GPIO_RESOURCE(0),
32 GPIO_RESOURCE(1),
33 GPIO_RESOURCE(2),
34 GPIO_RESOURCE(3),
35 GPIO_RESOURCE(4),
36 GPIO_RESOURCE(5),
37 GPIO_RESOURCE(6),
38 GPIO_RESOURCE(7),
39 GPIO_RESOURCE(8),
40};
41
42struct platform_device u8500_gpio_devs[] = {
43 GPIO_DEVICE(0),
44 GPIO_DEVICE(1),
45 GPIO_DEVICE(2),
46 GPIO_DEVICE(3),
47 GPIO_DEVICE(4),
48 GPIO_DEVICE(5),
49 GPIO_DEVICE(6),
50 GPIO_DEVICE(7),
51 GPIO_DEVICE(8),
52};
53
54struct amba_device u8500_ssp0_device = {
55 .dev = {
56 .coherent_dma_mask = ~0,
57 .init_name = "ssp0",
58 },
59 .res = {
60 .start = U8500_SSP0_BASE,
61 .end = U8500_SSP0_BASE + SZ_4K - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 .irq = {IRQ_SSP0, NO_IRQ },
65 /* ST-Ericsson modified id */
66 .periphid = SSP_PER_ID,
67};
68
69static struct resource u8500_i2c0_resources[] = {
70 [0] = {
71 .start = U8500_I2C0_BASE,
72 .end = U8500_I2C0_BASE + SZ_4K - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 [1] = {
76 .start = IRQ_I2C0,
77 .end = IRQ_I2C0,
78 .flags = IORESOURCE_IRQ,
79 }
80};
81
82struct platform_device u8500_i2c0_device = {
83 .name = "nmk-i2c",
84 .id = 0,
85 .resource = u8500_i2c0_resources,
86 .num_resources = ARRAY_SIZE(u8500_i2c0_resources),
87};
88
89static struct resource u8500_i2c4_resources[] = {
90 [0] = {
91 .start = U8500_I2C4_BASE,
92 .end = U8500_I2C4_BASE + SZ_4K - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = IRQ_I2C4,
97 .end = IRQ_I2C4,
98 .flags = IORESOURCE_IRQ,
99 }
100};
101
102struct platform_device u8500_i2c4_device = {
103 .name = "nmk-i2c",
104 .id = 4,
105 .resource = u8500_i2c4_resources,
106 .num_resources = ARRAY_SIZE(u8500_i2c4_resources),
107};
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
new file mode 100644
index 000000000000..8a268893cb7f
--- /dev/null
+++ b/arch/arm/mach-ux500/devices.c
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/amba/bus.h>
13
14#include <mach/hardware.h>
15#include <mach/setup.h>
16
17#define __MEM_4K_RESOURCE(x) \
18 .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
19
20struct amba_device ux500_pl031_device = {
21 .dev = {
22 .init_name = "pl031",
23 },
24 .res = {
25 .start = UX500_RTC_BASE,
26 .end = UX500_RTC_BASE + SZ_4K - 1,
27 .flags = IORESOURCE_MEM,
28 },
29 .irq = {IRQ_RTC_RTT, NO_IRQ},
30};
31
32struct amba_device ux500_uart0_device = {
33 .dev = { .init_name = "uart0" },
34 __MEM_4K_RESOURCE(UX500_UART0_BASE),
35 .irq = {IRQ_UART0, NO_IRQ},
36};
37
38struct amba_device ux500_uart1_device = {
39 .dev = { .init_name = "uart1" },
40 __MEM_4K_RESOURCE(UX500_UART1_BASE),
41 .irq = {IRQ_UART1, NO_IRQ},
42};
43
44struct amba_device ux500_uart2_device = {
45 .dev = { .init_name = "uart2" },
46 __MEM_4K_RESOURCE(UX500_UART2_BASE),
47 .irq = {IRQ_UART2, NO_IRQ},
48};
49
50#define UX500_I2C_RESOURCES(id, size) \
51static struct resource ux500_i2c##id##_resources[] = { \
52 [0] = { \
53 .start = UX500_I2C##id##_BASE, \
54 .end = UX500_I2C##id##_BASE + size - 1, \
55 .flags = IORESOURCE_MEM, \
56 }, \
57 [1] = { \
58 .start = IRQ_I2C##id, \
59 .end = IRQ_I2C##id, \
60 .flags = IORESOURCE_IRQ \
61 } \
62}
63
64UX500_I2C_RESOURCES(1, SZ_4K);
65UX500_I2C_RESOURCES(2, SZ_4K);
66UX500_I2C_RESOURCES(3, SZ_4K);
67
68#define UX500_I2C_PDEVICE(cid) \
69struct platform_device ux500_i2c##cid##_device = { \
70 .name = "nmk-i2c", \
71 .id = cid, \
72 .num_resources = 2, \
73 .resource = ux500_i2c##cid##_resources, \
74}
75
76UX500_I2C_PDEVICE(1);
77UX500_I2C_PDEVICE(2);
78UX500_I2C_PDEVICE(3);
79
80void __init amba_add_devices(struct amba_device *devs[], int num)
81{
82 int i;
83
84 for (i = 0; i < num; i++) {
85 struct amba_device *d = devs[i];
86 amba_device_register(d, &iomem_resource);
87 }
88}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
new file mode 100644
index 000000000000..545c80fc8024
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_MCDE_BASE 0xA0400000
21#define U5500_MODEM_BASE 0xB0000000
22#define U5500_L2CC_BASE 0xA0412000
23#define U5500_SCU_BASE 0xA0410000
24#define U5500_DSI1_BASE 0xA0401000
25#define U5500_DSI2_BASE 0xA0402000
26#define U5500_SIA_BASE 0xA0100000
27#define U5500_SVA_BASE 0x80200000
28#define U5500_HSEM_BASE 0xA0000000
29#define U5500_NAND0_BASE 0x60000000
30#define U5500_NAND1_BASE 0x70000000
31#define U5500_TWD_BASE 0xa0410600
32#define U5500_B2R2_BASE 0xa0200000
33
34#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
35#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
36#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
37#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
38#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
39#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
40#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
41#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
42
43#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
44#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
45#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
46
47#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
48#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
49#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
50#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
51
52#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
53#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
54#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
55#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
56#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
57#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
58#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
59#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
60#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
61#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
62#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
63
64#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
65#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
66#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
67#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
68#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
69#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
70#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
71#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
72#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
73#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
74#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
75#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
76#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
77#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
78#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
79#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
80#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
81
82#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
83#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
84#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
85#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
86#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
87#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
88#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
89#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
90#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
91#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
92#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
93
94#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
95#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
96#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
97#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
98#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
99#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
102
103#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
new file mode 100644
index 000000000000..9169e1e382a3
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB8500_REGS_H
8#define __MACH_DB8500_REGS_H
9
10#define U8500_PER3_BASE 0x80000000
11#define U8500_STM_BASE 0x80100000
12#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
13#define U8500_PER2_BASE 0x80110000
14#define U8500_PER1_BASE 0x80120000
15#define U8500_B2R2_BASE 0x80130000
16#define U8500_HSEM_BASE 0x80140000
17#define U8500_PER4_BASE 0x80150000
18#define U8500_ICN_BASE 0x81000000
19
20#define U8500_BOOT_ROM_BASE 0x90000000
21/* ASIC ID is at 0xff4 offset within this region */
22#define U8500_ASIC_ID_BASE 0x9001F000
23
24#define U8500_PER6_BASE 0xa03c0000
25#define U8500_PER5_BASE 0xa03e0000
26#define U8500_PER7_BASE_ED 0xa03d0000
27
28#define U8500_SVA_BASE 0xa0100000
29#define U8500_SIA_BASE 0xa0200000
30
31#define U8500_SGA_BASE 0xa0300000
32#define U8500_MCDE_BASE 0xa0350000
33#define U8500_DMA_BASE_ED 0xa0362000
34#define U8500_DMA_BASE 0x801C0000 /* v1 */
35
36#define U8500_SBAG_BASE 0xa0390000
37
38#define U8500_SCU_BASE 0xa0410000
39#define U8500_GIC_CPU_BASE 0xa0410100
40#define U8500_TWD_BASE 0xa0410600
41#define U8500_GIC_DIST_BASE 0xa0411000
42#define U8500_L2CC_BASE 0xa0412000
43
44#define U8500_MODEM_I2C 0xb7e02000
45
46#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
47#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
48#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
49#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
50
51/* per7 base addressess */
52#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
53#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
54#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
55#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
56#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
57
58#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
59#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
60
61/* per6 base addressess */
62#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
63#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
64#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
65#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
66#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
67#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
68#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
69#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
70#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
71
72/* per5 base addressess */
73#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
74#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
75
76/* per4 base addressess */
77#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
78#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
79#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
80#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
81#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
82#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
83#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
84#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
85#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
86
87/* per3 base addresses */
88#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
89#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
90#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
91#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
92#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
93#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
94#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
95#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
96#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
97
98/* per2 base addressess */
99#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
100#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
101#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
102#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
103#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
104#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
105#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
106#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
107#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
108#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
109#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
110#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
111
112/* per1 base addresses */
113#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
114#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
115#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
116#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
117#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
118#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
119#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
120#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
121#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
122
123#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
124
125#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
126#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
127#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
128#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
129#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
130#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
131#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
132#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
133#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
134
135#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 09cbfda8aee5..c5203b7ea552 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -10,11 +10,19 @@
10 */ 10 */
11#include <mach/hardware.h> 11#include <mach/hardware.h>
12 12
13#if CONFIG_UX500_DEBUG_UART > 2
14#error Invalid Ux500 debug UART
15#endif
16
17#define __UX500_UART(n) UX500_UART##n##_BASE
18#define UX500_UART(n) __UX500_UART(n)
19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART)
20
13 .macro addruart, rx, tmp 21 .macro addruart, rx, tmp
14 mrc p15, 0, \rx, c1, c0 22 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled? 23 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =U8500_UART2_BASE @ no, physical address 24 ldreq \rx, =UART_BASE @ no, physical address
17 ldrne \rx, =IO_ADDRESS(U8500_UART2_BASE) @ yes, virtual address 25 ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address
18 .endm 26 .endm
19 27
20#include <asm/hardware/debug-pl01x.S> 28#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
new file mode 100644
index 000000000000..0422af00a56e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __ASM_ARCH_DEVICES_H__
8#define __ASM_ARCH_DEVICES_H__
9
10struct platform_device;
11struct amba_device;
12
13extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[];
15
16extern struct amba_device ux500_pl031_device;
17extern struct amba_device u8500_ssp0_device;
18extern struct amba_device ux500_uart0_device;
19extern struct amba_device ux500_uart1_device;
20extern struct amba_device ux500_uart2_device;
21
22extern struct platform_device ux500_i2c1_device;
23extern struct platform_device ux500_i2c2_device;
24extern struct platform_device ux500_i2c3_device;
25
26extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device;
28
29#endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index eece3301fef7..60ea88db8283 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -17,7 +17,7 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE) 20 ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE)
21 .endm 21 .endm
22 22
23 .macro arch_ret_to_user, tmp1, tmp2 23 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100644
index 000000000000..d548a622e7d2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,50 @@
1#ifndef __ASM_ARCH_GPIO_H
2#define __ASM_ARCH_GPIO_H
3
4/*
5 * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough
6 * room for a couple of GPIO expanders.
7 */
8#define ARCH_NR_GPIOS 350
9
10#include <plat/gpio.h>
11
12#define __GPIO_RESOURCE(soc, block) \
13 { \
14 .start = soc##_GPIOBANK##block##_BASE, \
15 .end = soc##_GPIOBANK##block##_BASE + 127, \
16 .flags = IORESOURCE_MEM, \
17 }, \
18 { \
19 .start = IRQ_GPIO##block, \
20 .end = IRQ_GPIO##block, \
21 .flags = IORESOURCE_IRQ, \
22 }
23
24#define __GPIO_DEVICE(soc, block) \
25 { \
26 .name = "gpio", \
27 .id = block, \
28 .num_resources = 2, \
29 .resource = &soc##_gpio_resources[block * 2], \
30 .dev = { \
31 .platform_data = &soc##_gpio_data[block], \
32 }, \
33 }
34
35#define GPIO_DATA(_name, first) \
36 { \
37 .name = _name, \
38 .first_gpio = first, \
39 .first_irq = NOMADIK_GPIO_TO_IRQ(first), \
40 }
41
42#ifdef CONFIG_UX500_SOC_DB8500
43#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block)
44#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block)
45#elif defined(CONFIG_UX500_SOC_DB5500)
46#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block)
47#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block)
48#endif
49
50#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 04ea836969b3..8656379a8309 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,109 +23,106 @@
23 23
24/* typesafe io address */ 24/* typesafe io address */
25#define __io_address(n) __io(IO_ADDRESS(n)) 25#define __io_address(n) __io(IO_ADDRESS(n))
26/* used by some plat-nomadik code */
27#define io_p2v(n) __io_address(n)
26 28
27/* 29#include <mach/db8500-regs.h>
28 * Base address definitions for U8500 Onchip IPs. All the 30#include <mach/db5500-regs.h>
29 * peripherals are contained in a single 1 Mbyte region, with 31
30 * AHB peripherals at the bottom and APB peripherals at the 32#ifdef CONFIG_UX500_SOC_DB8500
31 * top of the region. PER stands for PERIPHERAL region which 33#define UX500(periph) U8500_##periph##_BASE
32 * itself divided into sub regions. 34#elif defined(CONFIG_UX500_SOC_DB5500)
33 */ 35#define UX500(periph) U5500_##periph##_BASE
34#define U8500_PER3_BASE 0x80000000 36#endif
35#define U8500_PER2_BASE 0x80110000 37
36#define U8500_PER1_BASE 0x80120000 38#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0)
37#define U8500_PER4_BASE 0x80150000 39#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1)
38 40#define UX500_B2R2_BASE UX500(B2R2)
39#define U8500_PER6_BASE 0xa03c0000 41
40#define U8500_PER5_BASE 0xa03e0000 42#define UX500_CLKRST1_BASE UX500(CLKRST1)
41#define U8500_PER7_BASE 0xa03d0000 43#define UX500_CLKRST2_BASE UX500(CLKRST2)
42 44#define UX500_CLKRST3_BASE UX500(CLKRST3)
43#define U8500_SVA_BASE 0xa0100000 45#define UX500_CLKRST5_BASE UX500(CLKRST5)
44#define U8500_SIA_BASE 0xa0200000 46#define UX500_CLKRST6_BASE UX500(CLKRST6)
45 47
46#define U8500_SGA_BASE 0xa0300000 48#define UX500_DMA_BASE UX500(DMA)
47#define U8500_MCDE_BASE 0xa0350000 49#define UX500_FSMC_BASE UX500(FSMC)
48#define U8500_DMA_BASE 0xa0362000 50
49 51#define UX500_GIC_CPU_BASE UX500(GIC_CPU)
50#define U8500_SCU_BASE 0xa0410000 52#define UX500_GIC_DIST_BASE UX500(GIC_DIST)
51#define U8500_GIC_CPU_BASE 0xa0410100 53
52#define U8500_TWD_BASE 0xa0410600 54#define UX500_I2C1_BASE UX500(I2C1)
53#define U8500_GIC_DIST_BASE 0xa0411000 55#define UX500_I2C2_BASE UX500(I2C2)
54#define U8500_L2CC_BASE 0xa0412000 56#define UX500_I2C3_BASE UX500(I2C3)
55 57
56#define U8500_TWD_SIZE 0x100 58#define UX500_L2CC_BASE UX500(L2CC)
57 59#define UX500_MCDE_BASE UX500(MCDE)
58/* per7 base addressess */ 60#define UX500_MTU0_BASE UX500(MTU0)
59#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000) 61#define UX500_MTU1_BASE UX500(MTU1)
60#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000) 62#define UX500_PRCMU_BASE UX500(PRCMU)
61#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000) 63
62#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000) 64#define UX500_RNG_BASE UX500(RNG)
63#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) 65#define UX500_RTC_BASE UX500(RTC)
64 66
65/* per6 base addressess */ 67#define UX500_SCU_BASE UX500(SCU)
66#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 68
67#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 69#define UX500_SDI0_BASE UX500(SDI0)
68#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 70#define UX500_SDI1_BASE UX500(SDI1)
69#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) 71#define UX500_SDI2_BASE UX500(SDI2)
70#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 72#define UX500_SDI3_BASE UX500(SDI3)
71#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 73#define UX500_SDI4_BASE UX500(SDI4)
72 74
73/* per5 base addressess */ 75#define UX500_SPI0_BASE UX500(SPI0)
74#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) 76#define UX500_SPI1_BASE UX500(SPI1)
75#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000) 77#define UX500_SPI2_BASE UX500(SPI2)
76#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) 78#define UX500_SPI3_BASE UX500(SPI3)
77 79
78/* per4 base addressess */ 80#define UX500_SIA_BASE UX500(SIA)
79#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000) 81#define UX500_SVA_BASE UX500(SVA)
80#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000) 82
81#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000) 83#define UX500_TWD_BASE UX500(TWD)
82#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000) 84
83#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000) 85#define UX500_UART0_BASE UX500(UART0)
84#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000) 86#define UX500_UART1_BASE UX500(UART1)
85#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000) 87#define UX500_UART2_BASE UX500(UART2)
86#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000) 88
87 89#define UX500_USBOTG_BASE UX500(USBOTG)
88/* per3 base addressess */
89#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
90#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
91#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
92#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
93#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
94#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
95#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
96#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
97#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
98#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
99
100/* per2 base addressess */
101#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
102#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
103#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
104#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
105#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
106#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
107#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
108#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
109#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
110#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
111#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
112#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
113#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
114
115/* per1 base addresses */
116#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
117#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
118#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
119#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
120#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
121#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
122#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
123#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
124#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
125#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
126#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
127 90
128/* ST-Ericsson modified pl022 id */ 91/* ST-Ericsson modified pl022 id */
129#define SSP_PER_ID 0x01080022 92#define SSP_PER_ID 0x01080022
130 93
94#ifndef __ASSEMBLY__
95
96#include <asm/cputype.h>
97
98static inline bool cpu_is_u8500(void)
99{
100#ifdef CONFIG_UX500_SOC_DB8500
101 return 1;
102#else
103 return 0;
104#endif
105}
106
107static inline bool cpu_is_u8500ed(void)
108{
109 return cpu_is_u8500() && (read_cpuid_id() & 15) == 0;
110}
111
112static inline bool cpu_is_u8500v1(void)
113{
114 return cpu_is_u8500() && (read_cpuid_id() & 15) == 1;
115}
116
117static inline bool cpu_is_u5500(void)
118{
119#ifdef CONFIG_UX500_SOC_DB5500
120 return 1;
121#else
122 return 0;
123#endif
124}
125
126#endif
127
131#endif /* __MACH_HARDWARE_H */ 128#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 394b5dd2200f..7970684b1d09 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -42,6 +42,7 @@
42#define IRQ_AB4500 (IRQ_SHPI_START + 40) 42#define IRQ_AB4500 (IRQ_SHPI_START + 40)
43#define IRQ_DISP (IRQ_SHPI_START + 48) 43#define IRQ_DISP (IRQ_SHPI_START + 48)
44#define IRQ_SiPI3 (IRQ_SHPI_START + 49) 44#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
45#define IRQ_I2C4 (IRQ_SHPI_START + 51)
45#define IRQ_SSP1 (IRQ_SHPI_START + 52) 46#define IRQ_SSP1 (IRQ_SHPI_START + 52)
46#define IRQ_I2C2 (IRQ_SHPI_START + 55) 47#define IRQ_I2C2 (IRQ_SHPI_START + 55)
47#define IRQ_SDMMC0 (IRQ_SHPI_START + 60) 48#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
@@ -66,6 +67,12 @@
66/* There are 128 shared peripheral interrupts assigned to 67/* There are 128 shared peripheral interrupts assigned to
67 * INTID[160:32]. The first 32 interrupts are reserved. 68 * INTID[160:32]. The first 32 interrupts are reserved.
68 */ 69 */
69#define NR_IRQS 161 70#define U8500_SOC_NR_IRQS 161
71
72/* After chip-specific IRQ numbers we have the GPIO ones */
73#define NOMADIK_NR_GPIO 288
74#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS)
75#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS)
76#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
70 77
71#endif /*ASM_ARCH_IRQS_H*/ 78#endif /*ASM_ARCH_IRQS_H*/
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index cf0ce1687f24..e978dbd9e210 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -14,10 +14,28 @@
14#include <asm/mach/time.h> 14#include <asm/mach/time.h>
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17extern void u8500_map_io(void); 17extern void __init ux500_map_io(void);
18extern void u8500_init_devices(void); 18extern void __init u5500_map_io(void);
19extern void u8500_init_irq(void); 19extern void __init u8500_map_io(void);
20
21extern void __init ux500_init_devices(void);
22extern void __init u5500_init_devices(void);
23extern void __init u8500_init_devices(void);
24
25extern void __init ux500_init_irq(void);
20/* We re-use nomadik_timer for this platform */ 26/* We re-use nomadik_timer for this platform */
21extern void nmdk_timer_init(void); 27extern void nmdk_timer_init(void);
22 28
29extern void __init amba_add_devices(struct amba_device *devs[], int num);
30
31struct sys_timer;
32extern struct sys_timer ux500_timer;
33
34#define __IO_DEV_DESC(x, sz) { \
35 .virtual = IO_ADDRESS(x), \
36 .pfn = __phys_to_pfn(x), \
37 .length = sz, \
38 .type = MT_DEVICE, \
39}
40
23#endif /* __ASM_ARCH_SETUP_H */ 41#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 8dfe7ca245d8..438ef16aec90 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -30,7 +30,7 @@ volatile int __cpuinitdata pen_release = -1;
30 30
31static unsigned int __init get_core_count(void) 31static unsigned int __init get_core_count(void)
32{ 32{
33 return scu_get_core_count(__io_address(U8500_SCU_BASE)); 33 return scu_get_core_count(__io_address(UX500_SCU_BASE));
34} 34}
35 35
36static DEFINE_SPINLOCK(boot_lock); 36static DEFINE_SPINLOCK(boot_lock);
@@ -44,7 +44,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
44 * core (e.g. timer irq), then they will not have been enabled 44 * core (e.g. timer irq), then they will not have been enabled
45 * for us: do so 45 * for us: do so
46 */ 46 */
47 gic_cpu_init(0, __io_address(U8500_GIC_CPU_BASE)); 47 gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
48 48
49 /* 49 /*
50 * let the primary processor know we're out of the 50 * let the primary processor know we're out of the
@@ -75,7 +75,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
75 * that it has been released by resetting pen_release. 75 * that it has been released by resetting pen_release.
76 */ 76 */
77 pen_release = cpu; 77 pen_release = cpu;
78 flush_cache_all(); 78 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
79 outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
79 80
80 timeout = jiffies + (1 * HZ); 81 timeout = jiffies + (1 * HZ);
81 while (time_before(jiffies, timeout)) { 82 while (time_before(jiffies, timeout)) {
@@ -105,12 +106,12 @@ static void __init wakeup_secondary(void)
105 */ 106 */
106#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4 107#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
107 __raw_writel(virt_to_phys(u8500_secondary_startup), 108 __raw_writel(virt_to_phys(u8500_secondary_startup),
108 (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) + 109 __io_address(UX500_BACKUPRAM0_BASE) +
109 U8500_CPU1_JUMPADDR_OFFSET); 110 U8500_CPU1_JUMPADDR_OFFSET);
110 111
111#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0 112#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
112 __raw_writel(0xA1FEED01, 113 __raw_writel(0xA1FEED01,
113 (void __iomem *)IO_ADDRESS(U8500_BACKUPRAM0_BASE) + 114 __io_address(UX500_BACKUPRAM0_BASE) +
114 U8500_CPU1_WAKEMAGIC_OFFSET); 115 U8500_CPU1_WAKEMAGIC_OFFSET);
115 116
116 /* make sure write buffer is drained */ 117 /* make sure write buffer is drained */
@@ -171,7 +172,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
171 * boot CPU, but only if we have more than one CPU. 172 * boot CPU, but only if we have more than one CPU.
172 */ 173 */
173 percpu_timer_setup(); 174 percpu_timer_setup();
174 scu_enable(__io_address(U8500_SCU_BASE)); 175 scu_enable(__io_address(UX500_SCU_BASE));
175 wakeup_secondary(); 176 wakeup_secondary();
176 } 177 }
177} 178}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 12:48:17 -0500