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-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h103
-rw-r--r--arch/arm/mach-ux500/include/mach/db8500-regs.h135
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h29
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S2
-rw-r--r--arch/arm/mach-ux500/include/mach/gpio.h50
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h197
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h9
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h24
9 files changed, 454 insertions, 107 deletions
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
new file mode 100644
index 000000000000..545c80fc8024
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_MCDE_BASE 0xA0400000
21#define U5500_MODEM_BASE 0xB0000000
22#define U5500_L2CC_BASE 0xA0412000
23#define U5500_SCU_BASE 0xA0410000
24#define U5500_DSI1_BASE 0xA0401000
25#define U5500_DSI2_BASE 0xA0402000
26#define U5500_SIA_BASE 0xA0100000
27#define U5500_SVA_BASE 0x80200000
28#define U5500_HSEM_BASE 0xA0000000
29#define U5500_NAND0_BASE 0x60000000
30#define U5500_NAND1_BASE 0x70000000
31#define U5500_TWD_BASE 0xa0410600
32#define U5500_B2R2_BASE 0xa0200000
33
34#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
35#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
36#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
37#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
38#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
39#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
40#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
41#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
42
43#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
44#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
45#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
46
47#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
48#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
49#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
50#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
51
52#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
53#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
54#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
55#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
56#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
57#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
58#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
59#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
60#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
61#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
62#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
63
64#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
65#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
66#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
67#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
68#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
69#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
70#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
71#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
72#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
73#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
74#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
75#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
76#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
77#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
78#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
79#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
80#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
81
82#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
83#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
84#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
85#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
86#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
87#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
88#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
89#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
90#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
91#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
92#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
93
94#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
95#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
96#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
97#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
98#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
99#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
102
103#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
new file mode 100644
index 000000000000..9169e1e382a3
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB8500_REGS_H
8#define __MACH_DB8500_REGS_H
9
10#define U8500_PER3_BASE 0x80000000
11#define U8500_STM_BASE 0x80100000
12#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
13#define U8500_PER2_BASE 0x80110000
14#define U8500_PER1_BASE 0x80120000
15#define U8500_B2R2_BASE 0x80130000
16#define U8500_HSEM_BASE 0x80140000
17#define U8500_PER4_BASE 0x80150000
18#define U8500_ICN_BASE 0x81000000
19
20#define U8500_BOOT_ROM_BASE 0x90000000
21/* ASIC ID is at 0xff4 offset within this region */
22#define U8500_ASIC_ID_BASE 0x9001F000
23
24#define U8500_PER6_BASE 0xa03c0000
25#define U8500_PER5_BASE 0xa03e0000
26#define U8500_PER7_BASE_ED 0xa03d0000
27
28#define U8500_SVA_BASE 0xa0100000
29#define U8500_SIA_BASE 0xa0200000
30
31#define U8500_SGA_BASE 0xa0300000
32#define U8500_MCDE_BASE 0xa0350000
33#define U8500_DMA_BASE_ED 0xa0362000
34#define U8500_DMA_BASE 0x801C0000 /* v1 */
35
36#define U8500_SBAG_BASE 0xa0390000
37
38#define U8500_SCU_BASE 0xa0410000
39#define U8500_GIC_CPU_BASE 0xa0410100
40#define U8500_TWD_BASE 0xa0410600
41#define U8500_GIC_DIST_BASE 0xa0411000
42#define U8500_L2CC_BASE 0xa0412000
43
44#define U8500_MODEM_I2C 0xb7e02000
45
46#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
47#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
48#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
49#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
50
51/* per7 base addressess */
52#define U8500_CR_BASE_ED (U8500_PER7_BASE_ED + 0x8000)
53#define U8500_MTU0_BASE_ED (U8500_PER7_BASE_ED + 0xa000)
54#define U8500_MTU1_BASE_ED (U8500_PER7_BASE_ED + 0xb000)
55#define U8500_TZPC0_BASE_ED (U8500_PER7_BASE_ED + 0xc000)
56#define U8500_CLKRST7_BASE_ED (U8500_PER7_BASE_ED + 0xf000)
57
58#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
59#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
60
61/* per6 base addressess */
62#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
63#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
64#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
65#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
66#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
67#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
68#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
69#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
70#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
71
72/* per5 base addressess */
73#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
74#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
75
76/* per4 base addressess */
77#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
78#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
79#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
80#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
81#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
82#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
83#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
84#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
85#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000)
86
87/* per3 base addresses */
88#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
89#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
90#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
91#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
92#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
93#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
94#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
95#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
96#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
97
98/* per2 base addressess */
99#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
100#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
101#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
102#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
103#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
104#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
105#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
106#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
107#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
108#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
109#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
110#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
111
112/* per1 base addresses */
113#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
114#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
115#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
116#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
117#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
118#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
119#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
120#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
121#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
122
123#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
124
125#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
126#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
127#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
128#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
129#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
130#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
131#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
132#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
133#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
134
135#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 09cbfda8aee5..c5203b7ea552 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -10,11 +10,19 @@
10 */ 10 */
11#include <mach/hardware.h> 11#include <mach/hardware.h>
12 12
13#if CONFIG_UX500_DEBUG_UART > 2
14#error Invalid Ux500 debug UART
15#endif
16
17#define __UX500_UART(n) UX500_UART##n##_BASE
18#define UX500_UART(n) __UX500_UART(n)
19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART)
20
13 .macro addruart, rx, tmp 21 .macro addruart, rx, tmp
14 mrc p15, 0, \rx, c1, c0 22 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled? 23 tst \rx, #1 @ MMU enabled?
16 ldreq \rx, =U8500_UART2_BASE @ no, physical address 24 ldreq \rx, =UART_BASE @ no, physical address
17 ldrne \rx, =IO_ADDRESS(U8500_UART2_BASE) @ yes, virtual address 25 ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address
18 .endm 26 .endm
19 27
20#include <asm/hardware/debug-pl01x.S> 28#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
new file mode 100644
index 000000000000..0422af00a56e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __ASM_ARCH_DEVICES_H__
8#define __ASM_ARCH_DEVICES_H__
9
10struct platform_device;
11struct amba_device;
12
13extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[];
15
16extern struct amba_device ux500_pl031_device;
17extern struct amba_device u8500_ssp0_device;
18extern struct amba_device ux500_uart0_device;
19extern struct amba_device ux500_uart1_device;
20extern struct amba_device ux500_uart2_device;
21
22extern struct platform_device ux500_i2c1_device;
23extern struct platform_device ux500_i2c2_device;
24extern struct platform_device ux500_i2c3_device;
25
26extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device;
28
29#endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index eece3301fef7..60ea88db8283 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -17,7 +17,7 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IO_ADDRESS(U8500_GIC_CPU_BASE) 20 ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE)
21 .endm 21 .endm
22 22
23 .macro arch_ret_to_user, tmp1, tmp2 23 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100644
index 000000000000..d548a622e7d2
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,50 @@
1#ifndef __ASM_ARCH_GPIO_H
2#define __ASM_ARCH_GPIO_H
3
4/*
5 * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough
6 * room for a couple of GPIO expanders.
7 */
8#define ARCH_NR_GPIOS 350
9
10#include <plat/gpio.h>
11
12#define __GPIO_RESOURCE(soc, block) \
13 { \
14 .start = soc##_GPIOBANK##block##_BASE, \
15 .end = soc##_GPIOBANK##block##_BASE + 127, \
16 .flags = IORESOURCE_MEM, \
17 }, \
18 { \
19 .start = IRQ_GPIO##block, \
20 .end = IRQ_GPIO##block, \
21 .flags = IORESOURCE_IRQ, \
22 }
23
24#define __GPIO_DEVICE(soc, block) \
25 { \
26 .name = "gpio", \
27 .id = block, \
28 .num_resources = 2, \
29 .resource = &soc##_gpio_resources[block * 2], \
30 .dev = { \
31 .platform_data = &soc##_gpio_data[block], \
32 }, \
33 }
34
35#define GPIO_DATA(_name, first) \
36 { \
37 .name = _name, \
38 .first_gpio = first, \
39 .first_irq = NOMADIK_GPIO_TO_IRQ(first), \
40 }
41
42#ifdef CONFIG_UX500_SOC_DB8500
43#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U8500, block)
44#define GPIO_DEVICE(block) __GPIO_DEVICE(u8500, block)
45#elif defined(CONFIG_UX500_SOC_DB5500)
46#define GPIO_RESOURCE(block) __GPIO_RESOURCE(U5500, block)
47#define GPIO_DEVICE(block) __GPIO_DEVICE(u5500, block)
48#endif
49
50#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 04ea836969b3..8656379a8309 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,109 +23,106 @@
23 23
24/* typesafe io address */ 24/* typesafe io address */
25#define __io_address(n) __io(IO_ADDRESS(n)) 25#define __io_address(n) __io(IO_ADDRESS(n))
26/* used by some plat-nomadik code */
27#define io_p2v(n) __io_address(n)
26 28
27/* 29#include <mach/db8500-regs.h>
28 * Base address definitions for U8500 Onchip IPs. All the 30#include <mach/db5500-regs.h>
29 * peripherals are contained in a single 1 Mbyte region, with 31
30 * AHB peripherals at the bottom and APB peripherals at the 32#ifdef CONFIG_UX500_SOC_DB8500
31 * top of the region. PER stands for PERIPHERAL region which 33#define UX500(periph) U8500_##periph##_BASE
32 * itself divided into sub regions. 34#elif defined(CONFIG_UX500_SOC_DB5500)
33 */ 35#define UX500(periph) U5500_##periph##_BASE
34#define U8500_PER3_BASE 0x80000000 36#endif
35#define U8500_PER2_BASE 0x80110000 37
36#define U8500_PER1_BASE 0x80120000 38#define UX500_BACKUPRAM0_BASE UX500(BACKUPRAM0)
37#define U8500_PER4_BASE 0x80150000 39#define UX500_BACKUPRAM1_BASE UX500(BACKUPRAM1)
38 40#define UX500_B2R2_BASE UX500(B2R2)
39#define U8500_PER6_BASE 0xa03c0000 41
40#define U8500_PER5_BASE 0xa03e0000 42#define UX500_CLKRST1_BASE UX500(CLKRST1)
41#define U8500_PER7_BASE 0xa03d0000 43#define UX500_CLKRST2_BASE UX500(CLKRST2)
42 44#define UX500_CLKRST3_BASE UX500(CLKRST3)
43#define U8500_SVA_BASE 0xa0100000 45#define UX500_CLKRST5_BASE UX500(CLKRST5)
44#define U8500_SIA_BASE 0xa0200000 46#define UX500_CLKRST6_BASE UX500(CLKRST6)
45 47
46#define U8500_SGA_BASE 0xa0300000 48#define UX500_DMA_BASE UX500(DMA)
47#define U8500_MCDE_BASE 0xa0350000 49#define UX500_FSMC_BASE UX500(FSMC)
48#define U8500_DMA_BASE 0xa0362000 50
49 51#define UX500_GIC_CPU_BASE UX500(GIC_CPU)
50#define U8500_SCU_BASE 0xa0410000 52#define UX500_GIC_DIST_BASE UX500(GIC_DIST)
51#define U8500_GIC_CPU_BASE 0xa0410100 53
52#define U8500_TWD_BASE 0xa0410600 54#define UX500_I2C1_BASE UX500(I2C1)
53#define U8500_GIC_DIST_BASE 0xa0411000 55#define UX500_I2C2_BASE UX500(I2C2)
54#define U8500_L2CC_BASE 0xa0412000 56#define UX500_I2C3_BASE UX500(I2C3)
55 57
56#define U8500_TWD_SIZE 0x100 58#define UX500_L2CC_BASE UX500(L2CC)
57 59#define UX500_MCDE_BASE UX500(MCDE)
58/* per7 base addressess */ 60#define UX500_MTU0_BASE UX500(MTU0)
59#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000) 61#define UX500_MTU1_BASE UX500(MTU1)
60#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000) 62#define UX500_PRCMU_BASE UX500(PRCMU)
61#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000) 63
62#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000) 64#define UX500_RNG_BASE UX500(RNG)
63#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) 65#define UX500_RTC_BASE UX500(RTC)
64 66
65/* per6 base addressess */ 67#define UX500_SCU_BASE UX500(SCU)
66#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000) 68
67#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000) 69#define UX500_SDI0_BASE UX500(SDI0)
68#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000) 70#define UX500_SDI1_BASE UX500(SDI1)
69#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000) 71#define UX500_SDI2_BASE UX500(SDI2)
70#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000) 72#define UX500_SDI3_BASE UX500(SDI3)
71#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) 73#define UX500_SDI4_BASE UX500(SDI4)
72 74
73/* per5 base addressess */ 75#define UX500_SPI0_BASE UX500(SPI0)
74#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000) 76#define UX500_SPI1_BASE UX500(SPI1)
75#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000) 77#define UX500_SPI2_BASE UX500(SPI2)
76#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) 78#define UX500_SPI3_BASE UX500(SPI3)
77 79
78/* per4 base addressess */ 80#define UX500_SIA_BASE UX500(SIA)
79#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000) 81#define UX500_SVA_BASE UX500(SVA)
80#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000) 82
81#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000) 83#define UX500_TWD_BASE UX500(TWD)
82#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000) 84
83#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000) 85#define UX500_UART0_BASE UX500(UART0)
84#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000) 86#define UX500_UART1_BASE UX500(UART1)
85#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000) 87#define UX500_UART2_BASE UX500(UART2)
86#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000) 88
87 89#define UX500_USBOTG_BASE UX500(USBOTG)
88/* per3 base addressess */
89#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
90#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
91#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
92#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
93#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
94#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
95#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
96#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
97#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
98#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
99
100/* per2 base addressess */
101#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
102#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
103#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
104#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
105#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
106#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
107#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
108#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
109#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
110#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
111#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
112#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
113#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
114
115/* per1 base addresses */
116#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
117#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
118#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
119#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
120#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
121#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
122#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
123#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
124#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
125#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
126#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
127 90
128/* ST-Ericsson modified pl022 id */ 91/* ST-Ericsson modified pl022 id */
129#define SSP_PER_ID 0x01080022 92#define SSP_PER_ID 0x01080022
130 93
94#ifndef __ASSEMBLY__
95
96#include <asm/cputype.h>
97
98static inline bool cpu_is_u8500(void)
99{
100#ifdef CONFIG_UX500_SOC_DB8500
101 return 1;
102#else
103 return 0;
104#endif
105}
106
107static inline bool cpu_is_u8500ed(void)
108{
109 return cpu_is_u8500() && (read_cpuid_id() & 15) == 0;
110}
111
112static inline bool cpu_is_u8500v1(void)
113{
114 return cpu_is_u8500() && (read_cpuid_id() & 15) == 1;
115}
116
117static inline bool cpu_is_u5500(void)
118{
119#ifdef CONFIG_UX500_SOC_DB5500
120 return 1;
121#else
122 return 0;
123#endif
124}
125
126#endif
127
131#endif /* __MACH_HARDWARE_H */ 128#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 394b5dd2200f..7970684b1d09 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -42,6 +42,7 @@
42#define IRQ_AB4500 (IRQ_SHPI_START + 40) 42#define IRQ_AB4500 (IRQ_SHPI_START + 40)
43#define IRQ_DISP (IRQ_SHPI_START + 48) 43#define IRQ_DISP (IRQ_SHPI_START + 48)
44#define IRQ_SiPI3 (IRQ_SHPI_START + 49) 44#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
45#define IRQ_I2C4 (IRQ_SHPI_START + 51)
45#define IRQ_SSP1 (IRQ_SHPI_START + 52) 46#define IRQ_SSP1 (IRQ_SHPI_START + 52)
46#define IRQ_I2C2 (IRQ_SHPI_START + 55) 47#define IRQ_I2C2 (IRQ_SHPI_START + 55)
47#define IRQ_SDMMC0 (IRQ_SHPI_START + 60) 48#define IRQ_SDMMC0 (IRQ_SHPI_START + 60)
@@ -66,6 +67,12 @@
66/* There are 128 shared peripheral interrupts assigned to 67/* There are 128 shared peripheral interrupts assigned to
67 * INTID[160:32]. The first 32 interrupts are reserved. 68 * INTID[160:32]. The first 32 interrupts are reserved.
68 */ 69 */
69#define NR_IRQS 161 70#define U8500_SOC_NR_IRQS 161
71
72/* After chip-specific IRQ numbers we have the GPIO ones */
73#define NOMADIK_NR_GPIO 288
74#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS)
75#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS)
76#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
70 77
71#endif /*ASM_ARCH_IRQS_H*/ 78#endif /*ASM_ARCH_IRQS_H*/
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index cf0ce1687f24..e978dbd9e210 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -14,10 +14,28 @@
14#include <asm/mach/time.h> 14#include <asm/mach/time.h>
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17extern void u8500_map_io(void); 17extern void __init ux500_map_io(void);
18extern void u8500_init_devices(void); 18extern void __init u5500_map_io(void);
19extern void u8500_init_irq(void); 19extern void __init u8500_map_io(void);
20
21extern void __init ux500_init_devices(void);
22extern void __init u5500_init_devices(void);
23extern void __init u8500_init_devices(void);
24
25extern void __init ux500_init_irq(void);
20/* We re-use nomadik_timer for this platform */ 26/* We re-use nomadik_timer for this platform */
21extern void nmdk_timer_init(void); 27extern void nmdk_timer_init(void);
22 28
29extern void __init amba_add_devices(struct amba_device *devs[], int num);
30
31struct sys_timer;
32extern struct sys_timer ux500_timer;
33
34#define __IO_DEV_DESC(x, sz) { \
35 .virtual = IO_ADDRESS(x), \
36 .pfn = __phys_to_pfn(x), \
37 .length = sz, \
38 .type = MT_DEVICE, \
39}
40
23#endif /* __ASM_ARCH_SETUP_H */ 41#endif /* __ASM_ARCH_SETUP_H */
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