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Diffstat (limited to 'arch/arm/mach-ux500/devices-db8500.c')
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c120
1 files changed, 60 insertions, 60 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index a30977b374ba..7989c564e47a 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -50,74 +50,74 @@ static struct resource dma40_resources[] = {
50 */ 50 */
51static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { 51static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
52 /* MUSB - these will be runtime-reconfigured */ 52 /* MUSB - these will be runtime-reconfigured */
53 [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1, 53 [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
54 [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1, 54 [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
55 [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1, 55 [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
56 [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1, 56 [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
57 [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1, 57 [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
58 [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1, 58 [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
59 [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1, 59 [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
60 [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1, 60 [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
61 /* PrimeCells - run-time configured */ 61 /* PrimeCells - run-time configured */
62 [DB8500_DMA_DEV0_SPI0_TX] = -1, 62 [DB8500_DMA_DEV0_SPI0] = -1,
63 [DB8500_DMA_DEV1_SD_MMC0_TX] = -1, 63 [DB8500_DMA_DEV1_SD_MMC0] = -1,
64 [DB8500_DMA_DEV2_SD_MMC1_TX] = -1, 64 [DB8500_DMA_DEV2_SD_MMC1] = -1,
65 [DB8500_DMA_DEV3_SD_MMC2_TX] = -1, 65 [DB8500_DMA_DEV3_SD_MMC2] = -1,
66 [DB8500_DMA_DEV8_SSP0_TX] = -1, 66 [DB8500_DMA_DEV8_SSP0] = -1,
67 [DB8500_DMA_DEV9_SSP1_TX] = -1, 67 [DB8500_DMA_DEV9_SSP1] = -1,
68 [DB8500_DMA_DEV11_UART2_TX] = -1, 68 [DB8500_DMA_DEV11_UART2] = -1,
69 [DB8500_DMA_DEV12_UART1_TX] = -1, 69 [DB8500_DMA_DEV12_UART1] = -1,
70 [DB8500_DMA_DEV13_UART0_TX] = -1, 70 [DB8500_DMA_DEV13_UART0] = -1,
71 [DB8500_DMA_DEV28_SD_MM2_TX] = -1, 71 [DB8500_DMA_DEV28_SD_MM2] = -1,
72 [DB8500_DMA_DEV29_SD_MM0_TX] = -1, 72 [DB8500_DMA_DEV29_SD_MM0] = -1,
73 [DB8500_DMA_DEV32_SD_MM1_TX] = -1, 73 [DB8500_DMA_DEV32_SD_MM1] = -1,
74 [DB8500_DMA_DEV33_SPI2_TX] = -1, 74 [DB8500_DMA_DEV33_SPI2] = -1,
75 [DB8500_DMA_DEV35_SPI1_TX] = -1, 75 [DB8500_DMA_DEV35_SPI1] = -1,
76 [DB8500_DMA_DEV40_SPI3_TX] = -1, 76 [DB8500_DMA_DEV40_SPI3] = -1,
77 [DB8500_DMA_DEV41_SD_MM3_TX] = -1, 77 [DB8500_DMA_DEV41_SD_MM3] = -1,
78 [DB8500_DMA_DEV42_SD_MM4_TX] = -1, 78 [DB8500_DMA_DEV42_SD_MM4] = -1,
79 [DB8500_DMA_DEV43_SD_MM5_TX] = -1, 79 [DB8500_DMA_DEV43_SD_MM5] = -1,
80 [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, 80 [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
81 [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, 81 [DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
82 [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, 82 [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
83 [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET, 83 [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
84 [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET, 84 [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
85}; 85};
86 86
87/* Mapping between source event lines and physical device address */ 87/* Mapping between source event lines and physical device address */
88static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { 88static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
89 /* MUSB - these will be runtime-reconfigured */ 89 /* MUSB - these will be runtime-reconfigured */
90 [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1, 90 [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
91 [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1, 91 [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
92 [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1, 92 [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
93 [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1, 93 [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
94 [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1, 94 [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
95 [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1, 95 [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
96 [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1, 96 [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
97 [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1, 97 [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
98 /* PrimeCells */ 98 /* PrimeCells */
99 [DB8500_DMA_DEV0_SPI0_RX] = -1, 99 [DB8500_DMA_DEV0_SPI0] = -1,
100 [DB8500_DMA_DEV1_SD_MMC0_RX] = -1, 100 [DB8500_DMA_DEV1_SD_MMC0] = -1,
101 [DB8500_DMA_DEV2_SD_MMC1_RX] = -1, 101 [DB8500_DMA_DEV2_SD_MMC1] = -1,
102 [DB8500_DMA_DEV3_SD_MMC2_RX] = -1, 102 [DB8500_DMA_DEV3_SD_MMC2] = -1,
103 [DB8500_DMA_DEV8_SSP0_RX] = -1, 103 [DB8500_DMA_DEV8_SSP0] = -1,
104 [DB8500_DMA_DEV9_SSP1_RX] = -1, 104 [DB8500_DMA_DEV9_SSP1] = -1,
105 [DB8500_DMA_DEV11_UART2_RX] = -1, 105 [DB8500_DMA_DEV11_UART2] = -1,
106 [DB8500_DMA_DEV12_UART1_RX] = -1, 106 [DB8500_DMA_DEV12_UART1] = -1,
107 [DB8500_DMA_DEV13_UART0_RX] = -1, 107 [DB8500_DMA_DEV13_UART0] = -1,
108 [DB8500_DMA_DEV28_SD_MM2_RX] = -1, 108 [DB8500_DMA_DEV28_SD_MM2] = -1,
109 [DB8500_DMA_DEV29_SD_MM0_RX] = -1, 109 [DB8500_DMA_DEV29_SD_MM0] = -1,
110 [DB8500_DMA_DEV32_SD_MM1_RX] = -1, 110 [DB8500_DMA_DEV32_SD_MM1] = -1,
111 [DB8500_DMA_DEV33_SPI2_RX] = -1, 111 [DB8500_DMA_DEV33_SPI2] = -1,
112 [DB8500_DMA_DEV35_SPI1_RX] = -1, 112 [DB8500_DMA_DEV35_SPI1] = -1,
113 [DB8500_DMA_DEV40_SPI3_RX] = -1, 113 [DB8500_DMA_DEV40_SPI3] = -1,
114 [DB8500_DMA_DEV41_SD_MM3_RX] = -1, 114 [DB8500_DMA_DEV41_SD_MM3] = -1,
115 [DB8500_DMA_DEV42_SD_MM4_RX] = -1, 115 [DB8500_DMA_DEV42_SD_MM4] = -1,
116 [DB8500_DMA_DEV43_SD_MM5_RX] = -1, 116 [DB8500_DMA_DEV43_SD_MM5] = -1,
117 [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, 117 [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
118 [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET, 118 [DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
119 [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, 119 [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
120 [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, 120 [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
121}; 121};
122 122
123static struct stedma40_platform_data dma40_plat_data = { 123static struct stedma40_platform_data dma40_plat_data = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 14:17:50 -0500