diff options
Diffstat (limited to 'arch/arm/mach-ux500/board-mop500.c')
-rw-r--r-- | arch/arm/mach-ux500/board-mop500.c | 63 |
1 files changed, 13 insertions, 50 deletions
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 78389de94dde..f59d52806afe 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
@@ -425,35 +425,20 @@ void mop500_snowball_ethernet_clock_enable(void) | |||
425 | static struct cryp_platform_data u8500_cryp1_platform_data = { | 425 | static struct cryp_platform_data u8500_cryp1_platform_data = { |
426 | .mem_to_engine = { | 426 | .mem_to_engine = { |
427 | .dir = STEDMA40_MEM_TO_PERIPH, | 427 | .dir = STEDMA40_MEM_TO_PERIPH, |
428 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 428 | .dev_type = DB8500_DMA_DEV48_CAC1, |
429 | .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX, | ||
430 | .src_info.data_width = STEDMA40_WORD_WIDTH, | ||
431 | .dst_info.data_width = STEDMA40_WORD_WIDTH, | ||
432 | .mode = STEDMA40_MODE_LOGICAL, | 429 | .mode = STEDMA40_MODE_LOGICAL, |
433 | .src_info.psize = STEDMA40_PSIZE_LOG_4, | ||
434 | .dst_info.psize = STEDMA40_PSIZE_LOG_4, | ||
435 | }, | 430 | }, |
436 | .engine_to_mem = { | 431 | .engine_to_mem = { |
437 | .dir = STEDMA40_PERIPH_TO_MEM, | 432 | .dir = STEDMA40_PERIPH_TO_MEM, |
438 | .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, | 433 | .dev_type = DB8500_DMA_DEV48_CAC1, |
439 | .dst_dev_type = STEDMA40_DEV_DST_MEMORY, | ||
440 | .src_info.data_width = STEDMA40_WORD_WIDTH, | ||
441 | .dst_info.data_width = STEDMA40_WORD_WIDTH, | ||
442 | .mode = STEDMA40_MODE_LOGICAL, | 434 | .mode = STEDMA40_MODE_LOGICAL, |
443 | .src_info.psize = STEDMA40_PSIZE_LOG_4, | ||
444 | .dst_info.psize = STEDMA40_PSIZE_LOG_4, | ||
445 | } | 435 | } |
446 | }; | 436 | }; |
447 | 437 | ||
448 | static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { | 438 | static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { |
449 | .dir = STEDMA40_MEM_TO_PERIPH, | 439 | .dir = STEDMA40_MEM_TO_PERIPH, |
450 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 440 | .dev_type = DB8500_DMA_DEV50_HAC1_TX, |
451 | .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX, | ||
452 | .src_info.data_width = STEDMA40_WORD_WIDTH, | ||
453 | .dst_info.data_width = STEDMA40_WORD_WIDTH, | ||
454 | .mode = STEDMA40_MODE_LOGICAL, | 441 | .mode = STEDMA40_MODE_LOGICAL, |
455 | .src_info.psize = STEDMA40_PSIZE_LOG_16, | ||
456 | .dst_info.psize = STEDMA40_PSIZE_LOG_16, | ||
457 | }; | 442 | }; |
458 | 443 | ||
459 | static struct hash_platform_data u8500_hash1_platform_data = { | 444 | static struct hash_platform_data u8500_hash1_platform_data = { |
@@ -471,19 +456,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = { | |||
471 | static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { | 456 | static struct stedma40_chan_cfg ssp0_dma_cfg_rx = { |
472 | .mode = STEDMA40_MODE_LOGICAL, | 457 | .mode = STEDMA40_MODE_LOGICAL, |
473 | .dir = STEDMA40_PERIPH_TO_MEM, | 458 | .dir = STEDMA40_PERIPH_TO_MEM, |
474 | .src_dev_type = DB8500_DMA_DEV8_SSP0_RX, | 459 | .dev_type = DB8500_DMA_DEV8_SSP0, |
475 | .dst_dev_type = STEDMA40_DEV_DST_MEMORY, | ||
476 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
477 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
478 | }; | 460 | }; |
479 | 461 | ||
480 | static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { | 462 | static struct stedma40_chan_cfg ssp0_dma_cfg_tx = { |
481 | .mode = STEDMA40_MODE_LOGICAL, | 463 | .mode = STEDMA40_MODE_LOGICAL, |
482 | .dir = STEDMA40_MEM_TO_PERIPH, | 464 | .dir = STEDMA40_MEM_TO_PERIPH, |
483 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 465 | .dev_type = DB8500_DMA_DEV8_SSP0, |
484 | .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX, | ||
485 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
486 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
487 | }; | 466 | }; |
488 | #endif | 467 | #endif |
489 | 468 | ||
@@ -512,55 +491,37 @@ static void __init mop500_spi_init(struct device *parent) | |||
512 | static struct stedma40_chan_cfg uart0_dma_cfg_rx = { | 491 | static struct stedma40_chan_cfg uart0_dma_cfg_rx = { |
513 | .mode = STEDMA40_MODE_LOGICAL, | 492 | .mode = STEDMA40_MODE_LOGICAL, |
514 | .dir = STEDMA40_PERIPH_TO_MEM, | 493 | .dir = STEDMA40_PERIPH_TO_MEM, |
515 | .src_dev_type = DB8500_DMA_DEV13_UART0_RX, | 494 | .dev_type = DB8500_DMA_DEV13_UART0, |
516 | .dst_dev_type = STEDMA40_DEV_DST_MEMORY, | ||
517 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
518 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
519 | }; | 495 | }; |
520 | 496 | ||
521 | static struct stedma40_chan_cfg uart0_dma_cfg_tx = { | 497 | static struct stedma40_chan_cfg uart0_dma_cfg_tx = { |
522 | .mode = STEDMA40_MODE_LOGICAL, | 498 | .mode = STEDMA40_MODE_LOGICAL, |
523 | .dir = STEDMA40_MEM_TO_PERIPH, | 499 | .dir = STEDMA40_MEM_TO_PERIPH, |
524 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 500 | .dev_type = DB8500_DMA_DEV13_UART0, |
525 | .dst_dev_type = DB8500_DMA_DEV13_UART0_TX, | ||
526 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
527 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
528 | }; | 501 | }; |
529 | 502 | ||
530 | static struct stedma40_chan_cfg uart1_dma_cfg_rx = { | 503 | static struct stedma40_chan_cfg uart1_dma_cfg_rx = { |
531 | .mode = STEDMA40_MODE_LOGICAL, | 504 | .mode = STEDMA40_MODE_LOGICAL, |
532 | .dir = STEDMA40_PERIPH_TO_MEM, | 505 | .dir = STEDMA40_PERIPH_TO_MEM, |
533 | .src_dev_type = DB8500_DMA_DEV12_UART1_RX, | 506 | .dev_type = DB8500_DMA_DEV12_UART1, |
534 | .dst_dev_type = STEDMA40_DEV_DST_MEMORY, | ||
535 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
536 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
537 | }; | 507 | }; |
538 | 508 | ||
539 | static struct stedma40_chan_cfg uart1_dma_cfg_tx = { | 509 | static struct stedma40_chan_cfg uart1_dma_cfg_tx = { |
540 | .mode = STEDMA40_MODE_LOGICAL, | 510 | .mode = STEDMA40_MODE_LOGICAL, |
541 | .dir = STEDMA40_MEM_TO_PERIPH, | 511 | .dir = STEDMA40_MEM_TO_PERIPH, |
542 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 512 | .dev_type = DB8500_DMA_DEV12_UART1, |
543 | .dst_dev_type = DB8500_DMA_DEV12_UART1_TX, | ||
544 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
545 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
546 | }; | 513 | }; |
547 | 514 | ||
548 | static struct stedma40_chan_cfg uart2_dma_cfg_rx = { | 515 | static struct stedma40_chan_cfg uart2_dma_cfg_rx = { |
549 | .mode = STEDMA40_MODE_LOGICAL, | 516 | .mode = STEDMA40_MODE_LOGICAL, |
550 | .dir = STEDMA40_PERIPH_TO_MEM, | 517 | .dir = STEDMA40_PERIPH_TO_MEM, |
551 | .src_dev_type = DB8500_DMA_DEV11_UART2_RX, | 518 | .dev_type = DB8500_DMA_DEV11_UART2, |
552 | .dst_dev_type = STEDMA40_DEV_DST_MEMORY, | ||
553 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
554 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
555 | }; | 519 | }; |
556 | 520 | ||
557 | static struct stedma40_chan_cfg uart2_dma_cfg_tx = { | 521 | static struct stedma40_chan_cfg uart2_dma_cfg_tx = { |
558 | .mode = STEDMA40_MODE_LOGICAL, | 522 | .mode = STEDMA40_MODE_LOGICAL, |
559 | .dir = STEDMA40_MEM_TO_PERIPH, | 523 | .dir = STEDMA40_MEM_TO_PERIPH, |
560 | .src_dev_type = STEDMA40_DEV_SRC_MEMORY, | 524 | .dev_type = DB8500_DMA_DEV11_UART2, |
561 | .dst_dev_type = DB8500_DMA_DEV11_UART2_TX, | ||
562 | .src_info.data_width = STEDMA40_BYTE_WIDTH, | ||
563 | .dst_info.data_width = STEDMA40_BYTE_WIDTH, | ||
564 | }; | 525 | }; |
565 | #endif | 526 | #endif |
566 | 527 | ||
@@ -676,6 +637,8 @@ static void __init snowball_init_machine(void) | |||
676 | 637 | ||
677 | mop500_snowball_ethernet_clock_enable(); | 638 | mop500_snowball_ethernet_clock_enable(); |
678 | 639 | ||
640 | u8500_cryp1_hash1_init(parent); | ||
641 | |||
679 | /* This board has full regulator constraints */ | 642 | /* This board has full regulator constraints */ |
680 | regulator_has_full_constraints(); | 643 | regulator_has_full_constraints(); |
681 | } | 644 | } |