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-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c184
1 files changed, 117 insertions, 67 deletions
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 4b996676594e..bf0b02414e5b 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -12,56 +12,14 @@
12#include <linux/mmc/host.h> 12#include <linux/mmc/host.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14 14
15#include <plat/pincfg.h> 15#include <asm/mach-types.h>
16#include <plat/ste_dma40.h>
16#include <mach/devices.h> 17#include <mach/devices.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18 19
19#include "devices-db8500.h" 20#include "devices-db8500.h"
20#include "pins-db8500.h"
21#include "board-mop500.h" 21#include "board-mop500.h"
22 22#include "ste-dma40-db8500.h"
23static pin_cfg_t mop500_sdi_pins[] = {
24 /* SDI0 (MicroSD slot) */
25 GPIO18_MC0_CMDDIR,
26 GPIO19_MC0_DAT0DIR,
27 GPIO20_MC0_DAT2DIR,
28 GPIO21_MC0_DAT31DIR,
29 GPIO22_MC0_FBCLK,
30 GPIO23_MC0_CLK,
31 GPIO24_MC0_CMD,
32 GPIO25_MC0_DAT0,
33 GPIO26_MC0_DAT1,
34 GPIO27_MC0_DAT2,
35 GPIO28_MC0_DAT3,
36
37 /* SDI4 (on-board eMMC) */
38 GPIO197_MC4_DAT3,
39 GPIO198_MC4_DAT2,
40 GPIO199_MC4_DAT1,
41 GPIO200_MC4_DAT0,
42 GPIO201_MC4_CMD,
43 GPIO202_MC4_FBCLK,
44 GPIO203_MC4_CLK,
45 GPIO204_MC4_DAT7,
46 GPIO205_MC4_DAT6,
47 GPIO206_MC4_DAT5,
48 GPIO207_MC4_DAT4,
49};
50
51static pin_cfg_t mop500_sdi2_pins[] = {
52 /* SDI2 (POP eMMC) */
53 GPIO128_MC2_CLK,
54 GPIO129_MC2_CMD,
55 GPIO130_MC2_FBCLK,
56 GPIO131_MC2_DAT0,
57 GPIO132_MC2_DAT1,
58 GPIO133_MC2_DAT2,
59 GPIO134_MC2_DAT3,
60 GPIO135_MC2_DAT4,
61 GPIO136_MC2_DAT5,
62 GPIO137_MC2_DAT6,
63 GPIO138_MC2_DAT7,
64};
65 23
66/* 24/*
67 * SDI 0 (MicroSD slot) 25 * SDI 0 (MicroSD slot)
@@ -86,48 +44,134 @@ static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
86 MCI_DATA2DIREN | MCI_DATA31DIREN; 44 MCI_DATA2DIREN | MCI_DATA31DIREN;
87} 45}
88 46
47#ifdef CONFIG_STE_DMA40
48struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
49 .mode = STEDMA40_MODE_LOGICAL,
50 .dir = STEDMA40_PERIPH_TO_MEM,
51 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
52 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
53 .src_info.data_width = STEDMA40_WORD_WIDTH,
54 .dst_info.data_width = STEDMA40_WORD_WIDTH,
55};
56
57static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
58 .mode = STEDMA40_MODE_LOGICAL,
59 .dir = STEDMA40_MEM_TO_PERIPH,
60 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
61 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
62 .src_info.data_width = STEDMA40_WORD_WIDTH,
63 .dst_info.data_width = STEDMA40_WORD_WIDTH,
64};
65#endif
66
89static struct mmci_platform_data mop500_sdi0_data = { 67static struct mmci_platform_data mop500_sdi0_data = {
90 .vdd_handler = mop500_sdi0_vdd_handler, 68 .vdd_handler = mop500_sdi0_vdd_handler,
91 .ocr_mask = MMC_VDD_29_30, 69 .ocr_mask = MMC_VDD_29_30,
92 .f_max = 100000000, 70 .f_max = 100000000,
93 .capabilities = MMC_CAP_4_BIT_DATA, 71 .capabilities = MMC_CAP_4_BIT_DATA,
94 .gpio_cd = GPIO_SDMMC_CD,
95 .gpio_wp = -1, 72 .gpio_wp = -1,
73#ifdef CONFIG_STE_DMA40
74 .dma_filter = stedma40_filter,
75 .dma_rx_param = &mop500_sdi0_dma_cfg_rx,
76 .dma_tx_param = &mop500_sdi0_dma_cfg_tx,
77#endif
96}; 78};
97 79
98void mop500_sdi_tc35892_init(void) 80/* GPIO pins used by the sdi0 level shifter */
81static int sdi0_en = -1;
82static int sdi0_vsel = -1;
83
84static void sdi0_configure(void)
99{ 85{
100 int ret; 86 int ret;
101 87
102 ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN"); 88 ret = gpio_request(sdi0_en, "level shifter enable");
103 if (!ret) 89 if (!ret)
104 ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL, 90 ret = gpio_request(sdi0_vsel,
105 "GPIO_SDMMC_1V8_3V_SEL"); 91 "level shifter 1v8-3v select");
106 if (ret) 92
93 if (ret) {
94 pr_warning("unable to config sdi0 gpios for level shifter.\n");
107 return; 95 return;
96 }
108 97
109 gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1); 98 /* Select the default 2.9V and enable level shifter */
110 gpio_direction_output(GPIO_SDMMC_EN, 0); 99 gpio_direction_output(sdi0_vsel, 0);
100 gpio_direction_output(sdi0_en, 1);
111 101
102 /* Add the device */
112 db8500_add_sdi0(&mop500_sdi0_data); 103 db8500_add_sdi0(&mop500_sdi0_data);
113} 104}
114 105
106void mop500_sdi_tc35892_init(void)
107{
108 mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
109 sdi0_en = GPIO_SDMMC_EN;
110 sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
111 sdi0_configure();
112}
113
115/* 114/*
116 * SDI 2 (POP eMMC, not on DB8500ed) 115 * SDI 2 (POP eMMC, not on DB8500ed)
117 */ 116 */
118 117
118#ifdef CONFIG_STE_DMA40
119struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
120 .mode = STEDMA40_MODE_LOGICAL,
121 .dir = STEDMA40_PERIPH_TO_MEM,
122 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
123 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
124 .src_info.data_width = STEDMA40_WORD_WIDTH,
125 .dst_info.data_width = STEDMA40_WORD_WIDTH,
126};
127
128static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
129 .mode = STEDMA40_MODE_LOGICAL,
130 .dir = STEDMA40_MEM_TO_PERIPH,
131 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
132 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
133 .src_info.data_width = STEDMA40_WORD_WIDTH,
134 .dst_info.data_width = STEDMA40_WORD_WIDTH,
135};
136#endif
137
119static struct mmci_platform_data mop500_sdi2_data = { 138static struct mmci_platform_data mop500_sdi2_data = {
120 .ocr_mask = MMC_VDD_165_195, 139 .ocr_mask = MMC_VDD_165_195,
121 .f_max = 100000000, 140 .f_max = 100000000,
122 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 141 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
123 .gpio_cd = -1, 142 .gpio_cd = -1,
124 .gpio_wp = -1, 143 .gpio_wp = -1,
144#ifdef CONFIG_STE_DMA40
145 .dma_filter = stedma40_filter,
146 .dma_rx_param = &mop500_sdi2_dma_cfg_rx,
147 .dma_tx_param = &mop500_sdi2_dma_cfg_tx,
148#endif
125}; 149};
126 150
127/* 151/*
128 * SDI 4 (on-board eMMC) 152 * SDI 4 (on-board eMMC)
129 */ 153 */
130 154
155#ifdef CONFIG_STE_DMA40
156struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
157 .mode = STEDMA40_MODE_LOGICAL,
158 .dir = STEDMA40_PERIPH_TO_MEM,
159 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
160 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
161 .src_info.data_width = STEDMA40_WORD_WIDTH,
162 .dst_info.data_width = STEDMA40_WORD_WIDTH,
163};
164
165static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
166 .mode = STEDMA40_MODE_LOGICAL,
167 .dir = STEDMA40_MEM_TO_PERIPH,
168 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
169 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
170 .src_info.data_width = STEDMA40_WORD_WIDTH,
171 .dst_info.data_width = STEDMA40_WORD_WIDTH,
172};
173#endif
174
131static struct mmci_platform_data mop500_sdi4_data = { 175static struct mmci_platform_data mop500_sdi4_data = {
132 .ocr_mask = MMC_VDD_29_30, 176 .ocr_mask = MMC_VDD_29_30,
133 .f_max = 100000000, 177 .f_max = 100000000,
@@ -135,26 +179,32 @@ static struct mmci_platform_data mop500_sdi4_data = {
135 MMC_CAP_MMC_HIGHSPEED, 179 MMC_CAP_MMC_HIGHSPEED,
136 .gpio_cd = -1, 180 .gpio_cd = -1,
137 .gpio_wp = -1, 181 .gpio_wp = -1,
182#ifdef CONFIG_STE_DMA40
183 .dma_filter = stedma40_filter,
184 .dma_rx_param = &mop500_sdi4_dma_cfg_rx,
185 .dma_tx_param = &mop500_sdi4_dma_cfg_tx,
186#endif
138}; 187};
139 188
140void __init mop500_sdi_init(void) 189void __init mop500_sdi_init(void)
141{ 190{
142 nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins)); 191 /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
192 if (!cpu_is_u8500v10())
193 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
194 db8500_add_sdi2(&mop500_sdi2_data);
195
196 /* On-board eMMC */
197 db8500_add_sdi4(&mop500_sdi4_data);
143 198
199 if (machine_is_hrefv60()) {
200 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
201 sdi0_en = HREFV60_SDMMC_EN_GPIO;
202 sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
203 sdi0_configure();
204 }
144 /* 205 /*
145 * sdi0 will finally be added when the TC35892 initializes and calls 206 * On boards with the TC35892 GPIO expander, sdi0 will finally
207 * be added when the TC35892 initializes and calls
146 * mop500_sdi_tc35892_init() above. 208 * mop500_sdi_tc35892_init() above.
147 */ 209 */
148
149 /* PoP:ed eMMC */
150 if (!cpu_is_u8500ed()) {
151 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
152 /* POP eMMC on v1.0 has problems with high speed */
153 if (!cpu_is_u8500v10())
154 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
155 db8500_add_sdi2(&mop500_sdi2_data);
156 }
157
158 /* On-board eMMC */
159 db8500_add_sdi4(&mop500_sdi4_data);
160} 210}