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-rw-r--r--arch/arm/mach-u300/core.c179
-rw-r--r--arch/arm/mach-u300/mmc.c12
-rw-r--r--arch/arm/mach-u300/spi.c21
3 files changed, 183 insertions, 29 deletions
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index aa53ee22438f..513d6abec1f5 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
3 * arch/arm/mach-u300/core.c 3 * arch/arm/mach-u300/core.c
4 * 4 *
5 * 5 *
6 * Copyright (C) 2007-2010 ST-Ericsson AB 6 * Copyright (C) 2007-2010 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions. 8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -16,7 +16,9 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18#include <linux/termios.h> 18#include <linux/termios.h>
19#include <linux/dmaengine.h>
19#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <linux/amba/serial.h>
20#include <linux/platform_device.h> 22#include <linux/platform_device.h>
21#include <linux/gpio.h> 23#include <linux/gpio.h>
22#include <linux/clk.h> 24#include <linux/clk.h>
@@ -96,10 +98,20 @@ void __init u300_map_io(void)
96 * Declaration of devices found on the U300 board and 98 * Declaration of devices found on the U300 board and
97 * their respective memory locations. 99 * their respective memory locations.
98 */ 100 */
101
102static struct amba_pl011_data uart0_plat_data = {
103#ifdef CONFIG_COH901318
104 .dma_filter = coh901318_filter_id,
105 .dma_rx_param = (void *) U300_DMA_UART0_RX,
106 .dma_tx_param = (void *) U300_DMA_UART0_TX,
107#endif
108};
109
99static struct amba_device uart0_device = { 110static struct amba_device uart0_device = {
100 .dev = { 111 .dev = {
112 .coherent_dma_mask = ~0,
101 .init_name = "uart0", /* Slow device at 0x3000 offset */ 113 .init_name = "uart0", /* Slow device at 0x3000 offset */
102 .platform_data = NULL, 114 .platform_data = &uart0_plat_data,
103 }, 115 },
104 .res = { 116 .res = {
105 .start = U300_UART0_BASE, 117 .start = U300_UART0_BASE,
@@ -111,10 +123,19 @@ static struct amba_device uart0_device = {
111 123
112/* The U335 have an additional UART1 on the APP CPU */ 124/* The U335 have an additional UART1 on the APP CPU */
113#ifdef CONFIG_MACH_U300_BS335 125#ifdef CONFIG_MACH_U300_BS335
126static struct amba_pl011_data uart1_plat_data = {
127#ifdef CONFIG_COH901318
128 .dma_filter = coh901318_filter_id,
129 .dma_rx_param = (void *) U300_DMA_UART1_RX,
130 .dma_tx_param = (void *) U300_DMA_UART1_TX,
131#endif
132};
133
114static struct amba_device uart1_device = { 134static struct amba_device uart1_device = {
115 .dev = { 135 .dev = {
136 .coherent_dma_mask = ~0,
116 .init_name = "uart1", /* Fast device at 0x7000 offset */ 137 .init_name = "uart1", /* Fast device at 0x7000 offset */
117 .platform_data = NULL, 138 .platform_data = &uart1_plat_data,
118 }, 139 },
119 .res = { 140 .res = {
120 .start = U300_UART1_BASE, 141 .start = U300_UART1_BASE,
@@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
960 .priority_high = 0, 981 .priority_high = 0,
961 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, 982 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
962 }, 983 },
984 /*
985 * Don't set up device address, burst count or size of src
986 * or dst bus for this peripheral - handled by PrimeCell
987 * DMA extension.
988 */
963 { 989 {
964 .number = U300_DMA_MMCSD_RX_TX, 990 .number = U300_DMA_MMCSD_RX_TX,
965 .name = "MMCSD RX TX", 991 .name = "MMCSD RX TX",
966 .priority_high = 0, 992 .priority_high = 0,
967 .dev_addr = U300_MMCSD_BASE + 0x080,
968 .param.config = COH901318_CX_CFG_CH_DISABLE | 993 .param.config = COH901318_CX_CFG_CH_DISABLE |
969 COH901318_CX_CFG_LCR_DISABLE | 994 COH901318_CX_CFG_LCR_DISABLE |
970 COH901318_CX_CFG_TC_IRQ_ENABLE | 995 COH901318_CX_CFG_TC_IRQ_ENABLE |
971 COH901318_CX_CFG_BE_IRQ_ENABLE, 996 COH901318_CX_CFG_BE_IRQ_ENABLE,
972 .param.ctrl_lli_chained = 0 | 997 .param.ctrl_lli_chained = 0 |
973 COH901318_CX_CTRL_TC_ENABLE | 998 COH901318_CX_CTRL_TC_ENABLE |
974 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
975 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
976 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
977 COH901318_CX_CTRL_MASTER_MODE_M1RW | 999 COH901318_CX_CTRL_MASTER_MODE_M1RW |
978 COH901318_CX_CTRL_TCP_ENABLE | 1000 COH901318_CX_CTRL_TCP_ENABLE |
979 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1001 COH901318_CX_CTRL_TC_IRQ_DISABLE |
980 COH901318_CX_CTRL_HSP_ENABLE | 1002 COH901318_CX_CTRL_HSP_ENABLE |
981 COH901318_CX_CTRL_HSS_DISABLE | 1003 COH901318_CX_CTRL_HSS_DISABLE |
982 COH901318_CX_CTRL_DDMA_LEGACY, 1004 COH901318_CX_CTRL_DDMA_LEGACY,
983 .param.ctrl_lli = 0 | 1005 .param.ctrl_lli = 0 |
984 COH901318_CX_CTRL_TC_ENABLE | 1006 COH901318_CX_CTRL_TC_ENABLE |
985 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
986 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
987 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1007 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_ENABLE | 1008 COH901318_CX_CTRL_TCP_ENABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1009 COH901318_CX_CTRL_TC_IRQ_DISABLE |
991 COH901318_CX_CTRL_HSP_ENABLE | 1010 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE | 1011 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY, 1012 COH901318_CX_CTRL_DDMA_LEGACY,
994 .param.ctrl_lli_last = 0 | 1013 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE | 1014 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
997 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
998 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
999 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1015 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1000 COH901318_CX_CTRL_TCP_DISABLE | 1016 COH901318_CX_CTRL_TCP_DISABLE |
1001 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1017 COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1014 .name = "MSPRO RX", 1030 .name = "MSPRO RX",
1015 .priority_high = 0, 1031 .priority_high = 0,
1016 }, 1032 },
1033 /*
1034 * Don't set up device address, burst count or size of src
1035 * or dst bus for this peripheral - handled by PrimeCell
1036 * DMA extension.
1037 */
1017 { 1038 {
1018 .number = U300_DMA_UART0_TX, 1039 .number = U300_DMA_UART0_TX,
1019 .name = "UART0 TX", 1040 .name = "UART0 TX",
1020 .priority_high = 0, 1041 .priority_high = 0,
1042 .param.config = COH901318_CX_CFG_CH_DISABLE |
1043 COH901318_CX_CFG_LCR_DISABLE |
1044 COH901318_CX_CFG_TC_IRQ_ENABLE |
1045 COH901318_CX_CFG_BE_IRQ_ENABLE,
1046 .param.ctrl_lli_chained = 0 |
1047 COH901318_CX_CTRL_TC_ENABLE |
1048 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1049 COH901318_CX_CTRL_TCP_ENABLE |
1050 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1051 COH901318_CX_CTRL_HSP_ENABLE |
1052 COH901318_CX_CTRL_HSS_DISABLE |
1053 COH901318_CX_CTRL_DDMA_LEGACY,
1054 .param.ctrl_lli = 0 |
1055 COH901318_CX_CTRL_TC_ENABLE |
1056 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1057 COH901318_CX_CTRL_TCP_ENABLE |
1058 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1059 COH901318_CX_CTRL_HSP_ENABLE |
1060 COH901318_CX_CTRL_HSS_DISABLE |
1061 COH901318_CX_CTRL_DDMA_LEGACY,
1062 .param.ctrl_lli_last = 0 |
1063 COH901318_CX_CTRL_TC_ENABLE |
1064 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1065 COH901318_CX_CTRL_TCP_ENABLE |
1066 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1067 COH901318_CX_CTRL_HSP_ENABLE |
1068 COH901318_CX_CTRL_HSS_DISABLE |
1069 COH901318_CX_CTRL_DDMA_LEGACY,
1021 }, 1070 },
1022 { 1071 {
1023 .number = U300_DMA_UART0_RX, 1072 .number = U300_DMA_UART0_RX,
1024 .name = "UART0 RX", 1073 .name = "UART0 RX",
1025 .priority_high = 0, 1074 .priority_high = 0,
1075 .param.config = COH901318_CX_CFG_CH_DISABLE |
1076 COH901318_CX_CFG_LCR_DISABLE |
1077 COH901318_CX_CFG_TC_IRQ_ENABLE |
1078 COH901318_CX_CFG_BE_IRQ_ENABLE,
1079 .param.ctrl_lli_chained = 0 |
1080 COH901318_CX_CTRL_TC_ENABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY,
1087 .param.ctrl_lli = 0 |
1088 COH901318_CX_CTRL_TC_ENABLE |
1089 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1090 COH901318_CX_CTRL_TCP_ENABLE |
1091 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1092 COH901318_CX_CTRL_HSP_ENABLE |
1093 COH901318_CX_CTRL_HSS_DISABLE |
1094 COH901318_CX_CTRL_DDMA_LEGACY,
1095 .param.ctrl_lli_last = 0 |
1096 COH901318_CX_CTRL_TC_ENABLE |
1097 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1098 COH901318_CX_CTRL_TCP_ENABLE |
1099 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1100 COH901318_CX_CTRL_HSP_ENABLE |
1101 COH901318_CX_CTRL_HSS_DISABLE |
1102 COH901318_CX_CTRL_DDMA_LEGACY,
1026 }, 1103 },
1027 { 1104 {
1028 .number = U300_DMA_APEX_TX, 1105 .number = U300_DMA_APEX_TX,
@@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1080 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | 1157 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW | 1158 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_ENABLE | 1159 COH901318_CX_CTRL_TCP_ENABLE |
1083 COH901318_CX_CTRL_TC_IRQ_ENABLE | 1160 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE | 1161 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE | 1162 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY | 1163 COH901318_CX_CTRL_DDMA_LEGACY |
@@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
1252 .name = "XGAM PDI", 1329 .name = "XGAM PDI",
1253 .priority_high = 0, 1330 .priority_high = 0,
1254 }, 1331 },
1332 /*
1333 * Don't set up device address, burst count or size of src
1334 * or dst bus for this peripheral - handled by PrimeCell
1335 * DMA extension.
1336 */
1255 { 1337 {
1256 .number = U300_DMA_SPI_TX, 1338 .number = U300_DMA_SPI_TX,
1257 .name = "SPI TX", 1339 .name = "SPI TX",
1258 .priority_high = 0, 1340 .priority_high = 0,
1341 .param.config = COH901318_CX_CFG_CH_DISABLE |
1342 COH901318_CX_CFG_LCR_DISABLE |
1343 COH901318_CX_CFG_TC_IRQ_ENABLE |
1344 COH901318_CX_CFG_BE_IRQ_ENABLE,
1345 .param.ctrl_lli_chained = 0 |
1346 COH901318_CX_CTRL_TC_ENABLE |
1347 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1348 COH901318_CX_CTRL_TCP_DISABLE |
1349 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1350 COH901318_CX_CTRL_HSP_ENABLE |
1351 COH901318_CX_CTRL_HSS_DISABLE |
1352 COH901318_CX_CTRL_DDMA_LEGACY,
1353 .param.ctrl_lli = 0 |
1354 COH901318_CX_CTRL_TC_ENABLE |
1355 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1356 COH901318_CX_CTRL_TCP_DISABLE |
1357 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1358 COH901318_CX_CTRL_HSP_ENABLE |
1359 COH901318_CX_CTRL_HSS_DISABLE |
1360 COH901318_CX_CTRL_DDMA_LEGACY,
1361 .param.ctrl_lli_last = 0 |
1362 COH901318_CX_CTRL_TC_ENABLE |
1363 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1364 COH901318_CX_CTRL_TCP_DISABLE |
1365 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1366 COH901318_CX_CTRL_HSP_ENABLE |
1367 COH901318_CX_CTRL_HSS_DISABLE |
1368 COH901318_CX_CTRL_DDMA_LEGACY,
1259 }, 1369 },
1260 { 1370 {
1261 .number = U300_DMA_SPI_RX, 1371 .number = U300_DMA_SPI_RX,
1262 .name = "SPI RX", 1372 .name = "SPI RX",
1263 .priority_high = 0, 1373 .priority_high = 0,
1374 .param.config = COH901318_CX_CFG_CH_DISABLE |
1375 COH901318_CX_CFG_LCR_DISABLE |
1376 COH901318_CX_CFG_TC_IRQ_ENABLE |
1377 COH901318_CX_CFG_BE_IRQ_ENABLE,
1378 .param.ctrl_lli_chained = 0 |
1379 COH901318_CX_CTRL_TC_ENABLE |
1380 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1381 COH901318_CX_CTRL_TCP_DISABLE |
1382 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1383 COH901318_CX_CTRL_HSP_ENABLE |
1384 COH901318_CX_CTRL_HSS_DISABLE |
1385 COH901318_CX_CTRL_DDMA_LEGACY,
1386 .param.ctrl_lli = 0 |
1387 COH901318_CX_CTRL_TC_ENABLE |
1388 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1389 COH901318_CX_CTRL_TCP_DISABLE |
1390 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1391 COH901318_CX_CTRL_HSP_ENABLE |
1392 COH901318_CX_CTRL_HSS_DISABLE |
1393 COH901318_CX_CTRL_DDMA_LEGACY,
1394 .param.ctrl_lli_last = 0 |
1395 COH901318_CX_CTRL_TC_ENABLE |
1396 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1397 COH901318_CX_CTRL_TCP_DISABLE |
1398 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1399 COH901318_CX_CTRL_HSP_ENABLE |
1400 COH901318_CX_CTRL_HSS_DISABLE |
1401 COH901318_CX_CTRL_DDMA_LEGACY,
1402
1264 }, 1403 },
1265 { 1404 {
1266 .number = U300_DMA_GENERAL_PURPOSE_0, 1405 .number = U300_DMA_GENERAL_PURPOSE_0,
@@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void)
1617#endif 1756#endif
1618#ifdef CONFIG_MACH_U300_BS335 1757#ifdef CONFIG_MACH_U300_BS335
1619 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { 1758 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1620 printk(KERN_ERR "Platform configured for BS365 " \ 1759 printk(KERN_ERR "Platform configured for BS335 " \
1621 " with DB3350 but %s detected, expect problems!", 1760 " with DB3350 but %s detected, expect problems!",
1622 chipname); 1761 chipname);
1623 } 1762 }
@@ -1692,12 +1831,12 @@ void __init u300_init_devices(void)
1692 /* Register subdevices on the I2C buses */ 1831 /* Register subdevices on the I2C buses */
1693 u300_i2c_register_board_devices(); 1832 u300_i2c_register_board_devices();
1694 1833
1695 /* Register subdevices on the SPI bus */
1696 u300_spi_register_board_devices();
1697
1698 /* Register the platform devices */ 1834 /* Register the platform devices */
1699 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 1835 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1700 1836
1837 /* Register subdevices on the SPI bus */
1838 u300_spi_register_board_devices();
1839
1701#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED 1840#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1702 /* 1841 /*
1703 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when 1842 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 8bb4ef42ab04..677ccef5cd32 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -3,19 +3,22 @@
3 * arch/arm/mach-u300/mmc.c 3 * arch/arm/mach-u300/mmc.c
4 * 4 *
5 * 5 *
6 * Copyright (C) 2009 ST-Ericsson AB 6 * Copyright (C) 2009 ST-Ericsson SA
7 * License terms: GNU General Public License (GPL) version 2 7 * License terms: GNU General Public License (GPL) version 2
8 * 8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Johan Lundin <johan.lundin@stericsson.com> 10 * Author: Johan Lundin
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */ 12 */
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/amba/bus.h> 14#include <linux/amba/bus.h>
15#include <linux/mmc/host.h> 15#include <linux/mmc/host.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/dmaengine.h>
17#include <linux/amba/mmci.h> 18#include <linux/amba/mmci.h>
18#include <linux/slab.h> 19#include <linux/slab.h>
20#include <mach/coh901318.h>
21#include <mach/dma_channels.h>
19 22
20#include "mmc.h" 23#include "mmc.h"
21#include "padmux.h" 24#include "padmux.h"
@@ -32,6 +35,11 @@ static struct mmci_platform_data mmc0_plat_data = {
32 .cd_invert = true, 35 .cd_invert = true,
33 .capabilities = MMC_CAP_MMC_HIGHSPEED | 36 .capabilities = MMC_CAP_MMC_HIGHSPEED |
34 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 37 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
38#ifdef CONFIG_COH901318
39 .dma_filter = coh901318_filter_id,
40 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
41 /* Don't specify a TX channel, this RX channel is bidirectional */
42#endif
35}; 43};
36 44
37int __devinit mmc_init(struct amba_device *adev) 45int __devinit mmc_init(struct amba_device *adev)
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 00869def5420..5767208f1c1d 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -11,6 +11,9 @@
11#include <linux/spi/spi.h> 11#include <linux/spi/spi.h>
12#include <linux/amba/pl022.h> 12#include <linux/amba/pl022.h>
13#include <linux/err.h> 13#include <linux/err.h>
14#include <mach/coh901318.h>
15#include <mach/dma_channels.h>
16
14#include "padmux.h" 17#include "padmux.h"
15 18
16/* 19/*
@@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect)
30} 33}
31 34
32struct pl022_config_chip dummy_chip_info = { 35struct pl022_config_chip dummy_chip_info = {
33 /* 36 /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
34 * available POLLING_TRANSFER and INTERRUPT_TRANSFER, 37 .com_mode = DMA_TRANSFER,
35 * DMA_TRANSFER does not work
36 */
37 .com_mode = INTERRUPT_TRANSFER,
38 .iface = SSP_INTERFACE_MOTOROLA_SPI, 38 .iface = SSP_INTERFACE_MOTOROLA_SPI,
39 /* We can only act as master but SSP_SLAVE is possible in theory */ 39 /* We can only act as master but SSP_SLAVE is possible in theory */
40 .hierarchy = SSP_MASTER, 40 .hierarchy = SSP_MASTER,
@@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = {
75static struct pl022_ssp_controller ssp_platform_data = { 75static struct pl022_ssp_controller ssp_platform_data = {
76 /* If you have several SPI buses this varies, we have only bus 0 */ 76 /* If you have several SPI buses this varies, we have only bus 0 */
77 .bus_id = 0, 77 .bus_id = 0,
78 /* Set this to 1 when we think we got DMA working */
79 .enable_dma = 0,
80 /* 78 /*
81 * On the APP CPU GPIO 4, 5 and 6 are connected as generic 79 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
82 * chip selects for SPI. (Same on U330, U335 and U365.) 80 * chip selects for SPI. (Same on U330, U335 and U365.)
@@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
84 * and do padmuxing accordingly too. 82 * and do padmuxing accordingly too.
85 */ 83 */
86 .num_chipselect = 3, 84 .num_chipselect = 3,
85#ifdef CONFIG_COH901318
86 .enable_dma = 1,
87 .dma_filter = coh901318_filter_id,
88 .dma_rx_param = (void *) U300_DMA_SPI_RX,
89 .dma_tx_param = (void *) U300_DMA_SPI_TX,
90#else
91 .enable_dma = 0,
92#endif
87}; 93};
88 94
89 95
@@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev)
109 } 115 }
110 116
111} 117}
118
112void __init u300_spi_register_board_devices(void) 119void __init u300_spi_register_board_devices(void)
113{ 120{
114 /* Register any SPI devices */ 121 /* Register any SPI devices */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 14:38:00 -0500