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-rw-r--r--arch/arm/mach-u300/Kconfig105
-rw-r--r--arch/arm/mach-u300/Makefile11
-rw-r--r--arch/arm/mach-u300/Makefile.boot15
-rw-r--r--arch/arm/mach-u300/clock.c1487
-rw-r--r--arch/arm/mach-u300/clock.h53
-rw-r--r--arch/arm/mach-u300/core.c649
-rw-r--r--arch/arm/mach-u300/gpio.c703
-rw-r--r--arch/arm/mach-u300/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-u300/include/mach/debug-macro.S22
-rw-r--r--arch/arm/mach-u300/include/mach/entry-macro.S40
-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h290
-rw-r--r--arch/arm/mach-u300/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-u300/include/mach/io.h20
-rw-r--r--arch/arm/mach-u300/include/mach/irqs.h114
-rw-r--r--arch/arm/mach-u300/include/mach/memory.h42
-rw-r--r--arch/arm/mach-u300/include/mach/platform.h19
-rw-r--r--arch/arm/mach-u300/include/mach/syscon.h644
-rw-r--r--arch/arm/mach-u300/include/mach/system.h42
-rw-r--r--arch/arm/mach-u300/include/mach/timex.h17
-rw-r--r--arch/arm/mach-u300/include/mach/u300-regs.h187
-rw-r--r--arch/arm/mach-u300/include/mach/uncompress.h46
-rw-r--r--arch/arm/mach-u300/include/mach/vmalloc.h12
-rw-r--r--arch/arm/mach-u300/mmc.c216
-rw-r--r--arch/arm/mach-u300/mmc.h18
-rw-r--r--arch/arm/mach-u300/padmux.c58
-rw-r--r--arch/arm/mach-u300/padmux.h19
-rw-r--r--arch/arm/mach-u300/timer.c422
-rw-r--r--arch/arm/mach-u300/u300.c55
28 files changed, 5318 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
new file mode 100644
index 000000000000..337b9aabce49
--- /dev/null
+++ b/arch/arm/mach-u300/Kconfig
@@ -0,0 +1,105 @@
1if ARCH_U300
2
3menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
4
5comment "ST-Ericsson Mobile Platform Products"
6
7config MACH_U300
8 bool "U300"
9
10comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
11
12choice
13 prompt "U300/U330/U335/U365 system type"
14 default MACH_U300_BS2X
15 ---help---
16 You need to select the target system, i.e. the
17 U300/U330/U335/U365 board that you want to compile your kernel
18 for.
19
20config MACH_U300_BS2X
21 bool "S26/S26/B25/B26 Test Products"
22 depends on MACH_U300
23 help
24 Select this if you're developing on the
25 S26/S25 test products. (Also works on
26 B26/B25 big boards.)
27
28config MACH_U300_BS330
29 bool "S330/B330 Test Products"
30 depends on MACH_U300
31 help
32 Select this if you're developing on the
33 S330/B330 test products.
34
35config MACH_U300_BS335
36 bool "S335/B335 Test Products"
37 depends on MACH_U300
38 help
39 Select this if you're developing on the
40 S335/B335 test products.
41
42config MACH_U300_BS365
43 bool "S365/B365 Test Products"
44 depends on MACH_U300
45 help
46 Select this if you're developing on the
47 S365/B365 test products.
48
49endchoice
50
51choice
52 prompt "Memory configuration"
53 default MACH_U300_SINGLE_RAM
54 ---help---
55 You have to config the kernel according to the physical memory
56 configuration.
57
58config MACH_U300_SINGLE_RAM
59 bool "Single RAM"
60 help
61 Select this if you want support for Single RAM phones.
62
63config MACH_U300_DUAL_RAM
64 bool "Dual RAM"
65 help
66 Select this if you want support for Dual RAM phones.
67 This is two RAM memorys on different EMIFs.
68endchoice
69
70config U300_DEBUG
71 bool "Debug support for U300"
72 depends on PM
73 help
74 Debug support for U300 in sysfs, procfs etc.
75
76config MACH_U300_SEMI_IS_SHARED
77 bool "The SEMI is used by both the access and application side"
78 depends on MACH_U300
79 help
80 This makes it possible to use the SEMI (Shared External
81 Memory Interface) from both from access and application
82 side.
83
84comment "All the settings below must match the bootloader's settings"
85
86config MACH_U300_ACCESS_MEM_SIZE
87 int "Access CPU memory allocation"
88 range 7 25
89 depends on MACH_U300_SINGLE_RAM
90 default 13
91 help
92 How much memory in MiB that the Access side CPU has allocated
93
94config MACH_U300_2MB_ALIGNMENT_FIX
95 bool "2MiB alignment fix"
96 depends on MACH_U300_SINGLE_RAM
97 default y
98 help
99 If yes and the Access side CPU has allocated an odd size in
100 MiB, this fix gives you one MiB extra that would otherwise be
101 lost due to Linux 2 MiB alignment policy.
102
103endmenu
104
105endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
new file mode 100644
index 000000000000..24950e0df4b4
--- /dev/null
+++ b/arch/arm/mach-u300/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel, U300 machine.
3#
4
5obj-y := core.o clock.o timer.o gpio.o padmux.o
6obj-m :=
7obj-n :=
8obj- :=
9
10obj-$(CONFIG_ARCH_U300) += u300.o
11obj-$(CONFIG_MMC) += mmc.o
diff --git a/arch/arm/mach-u300/Makefile.boot b/arch/arm/mach-u300/Makefile.boot
new file mode 100644
index 000000000000..6fbfc6ea2d35
--- /dev/null
+++ b/arch/arm/mach-u300/Makefile.boot
@@ -0,0 +1,15 @@
1# Note: the following conditions must always be true:
2# ZRELADDR == virt_to_phys(TEXTADDR)
3# PARAMS_PHYS must be within 4MB of ZRELADDR
4# INITRD_PHYS must be in RAM
5
6ifdef CONFIG_MACH_U300_SINGLE_RAM
7 zreladdr-y := 0x28E08000
8 params_phys-y := 0x28E00100
9else
10 zreladdr-y := 0x48008000
11 params_phys-y := 0x48000100
12endif
13
14# This isn't used.
15#initrd_phys-y := 0x29800000
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
new file mode 100644
index 000000000000..5cd04d6751b3
--- /dev/null
+++ b/arch/arm/mach-u300/clock.c
@@ -0,0 +1,1487 @@
1/*
2 *
3 * arch/arm/mach-u300/clock.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/clk.h>
20#include <linux/mutex.h>
21#include <linux/spinlock.h>
22#include <linux/debugfs.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/timer.h>
26#include <linux/io.h>
27
28#include <asm/clkdev.h>
29#include <mach/hardware.h>
30#include <mach/syscon.h>
31
32#include "clock.h"
33
34/*
35 * TODO:
36 * - move all handling of the CCR register into this file and create
37 * a spinlock for the CCR register
38 * - switch to the clkdevice lookup mechanism that maps clocks to
39 * device ID:s instead when it becomes available in kernel 2.6.29.
40 * - implement rate get/set for all clocks that need it.
41 */
42
43/*
44 * Syscon clock I/O registers lock so clock requests don't collide
45 * NOTE: this is a local lock only used to lock access to clock and
46 * reset registers in syscon.
47 */
48static DEFINE_SPINLOCK(syscon_clkreg_lock);
49static DEFINE_SPINLOCK(syscon_resetreg_lock);
50
51/*
52 * The clocking hierarchy currently looks like this.
53 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
54 * The ideas is to show dependencies, so a clock higher up in the
55 * hierarchy has to be on in order for another clock to be on. Now,
56 * both CPU and DMA can actually be on top of the hierarchy, and that
57 * is not modeled currently. Instead we have the backbone AMBA bus on
58 * top. This bus cannot be programmed in any way but conceptually it
59 * needs to be active for the bridges and devices to transport data.
60 *
61 * Please be aware that a few clocks are hw controlled, which mean that
62 * the hw itself can turn on/off or change the rate of the clock when
63 * needed!
64 *
65 * AMBA bus
66 * |
67 * +- CPU
68 * +- NANDIF NAND Flash interface
69 * +- SEMI Shared Memory interface
70 * +- ISP Image Signal Processor (U335 only)
71 * +- CDS (U335 only)
72 * +- DMA Direct Memory Access Controller
73 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
74 * +- APEX
75 * +- VIDEO_ENC AVE2/3 Video Encoder
76 * +- XGAM Graphics Accelerator Controller
77 * +- AHB
78 * |
79 * +- ahb:0 AHB Bridge
80 * | |
81 * | +- ahb:1 INTCON Interrupt controller
82 * | +- ahb:3 MSPRO Memory Stick Pro controller
83 * | +- ahb:4 EMIF External Memory interface
84 * |
85 * +- fast:0 FAST bridge
86 * | |
87 * | +- fast:1 MMCSD MMC/SD card reader controller
88 * | +- fast:2 I2S0 PCM I2S channel 0 controller
89 * | +- fast:3 I2S1 PCM I2S channel 1 controller
90 * | +- fast:4 I2C0 I2C channel 0 controller
91 * | +- fast:5 I2C1 I2C channel 1 controller
92 * | +- fast:6 SPI SPI controller
93 * | +- fast:7 UART1 Secondary UART (U335 only)
94 * |
95 * +- slow:0 SLOW bridge
96 * |
97 * +- slow:1 SYSCON (not possible to control)
98 * +- slow:2 WDOG Watchdog
99 * +- slow:3 UART0 primary UART
100 * +- slow:4 TIMER_APP Application timer - used in Linux
101 * +- slow:5 KEYPAD controller
102 * +- slow:6 GPIO controller
103 * +- slow:7 RTC controller
104 * +- slow:8 BT Bus Tracer (not used currently)
105 * +- slow:9 EH Event Handler (not used currently)
106 * +- slow:a TIMER_ACC Access style timer (not used currently)
107 * +- slow:b PPM (U335 only, what is that?)
108 */
109
110/*
111 * Reset control functions. We remember if a block has been
112 * taken out of reset and don't remove the reset assertion again
113 * and vice versa. Currently we only remove resets so the
114 * enablement function is defined out.
115 */
116static void syscon_block_reset_enable(struct clk *clk)
117{
118 u16 val;
119 unsigned long iflags;
120
121 /* Not all blocks support resetting */
122 if (!clk->res_reg || !clk->res_mask)
123 return;
124 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
125 val = readw(clk->res_reg);
126 val |= clk->res_mask;
127 writew(val, clk->res_reg);
128 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
129 clk->reset = true;
130}
131
132static void syscon_block_reset_disable(struct clk *clk)
133{
134 u16 val;
135 unsigned long iflags;
136
137 /* Not all blocks support resetting */
138 if (!clk->res_reg || !clk->res_mask)
139 return;
140 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
141 val = readw(clk->res_reg);
142 val &= ~clk->res_mask;
143 writew(val, clk->res_reg);
144 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
145 clk->reset = false;
146}
147
148int __clk_get(struct clk *clk)
149{
150 u16 val;
151
152 /* The MMC and MSPRO clocks need some special set-up */
153 if (!strcmp(clk->name, "MCLK")) {
154 /* Set default MMC clock divisor to 18.9 MHz */
155 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
156 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
157 /* Disable the MMC feedback clock */
158 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
159 /* Disable MSPRO frequency */
160 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
161 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
162 }
163 if (!strcmp(clk->name, "MSPRO")) {
164 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
165 /* Disable the MMC feedback clock */
166 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
167 /* Enable MSPRO frequency */
168 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
169 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
170 }
171 return 1;
172}
173EXPORT_SYMBOL(__clk_get);
174
175void __clk_put(struct clk *clk)
176{
177}
178EXPORT_SYMBOL(__clk_put);
179
180static void syscon_clk_disable(struct clk *clk)
181{
182 unsigned long iflags;
183
184 /* Don't touch the hardware controlled clocks */
185 if (clk->hw_ctrld)
186 return;
187
188 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
189 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
190 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
191}
192
193static void syscon_clk_enable(struct clk *clk)
194{
195 unsigned long iflags;
196
197 /* Don't touch the hardware controlled clocks */
198 if (clk->hw_ctrld)
199 return;
200
201 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
202 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
203 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
204}
205
206static u16 syscon_clk_get_rate(void)
207{
208 u16 val;
209 unsigned long iflags;
210
211 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
212 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
213 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
214 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
215 return val;
216}
217
218#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
219static void enable_i2s0_vcxo(void)
220{
221 u16 val;
222 unsigned long iflags;
223
224 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
225 /* Set I2S0 to use the VCXO 26 MHz clock */
226 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
227 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
228 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
229 val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
230 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
231 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
232 val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
233 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
234 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
235}
236
237static void enable_i2s1_vcxo(void)
238{
239 u16 val;
240 unsigned long iflags;
241
242 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
243 /* Set I2S1 to use the VCXO 26 MHz clock */
244 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
245 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
246 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
247 val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
248 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
249 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
250 val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
251 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
252 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
253}
254
255static void disable_i2s0_vcxo(void)
256{
257 u16 val;
258 unsigned long iflags;
259
260 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
261 /* Disable I2S0 use of the VCXO 26 MHz clock */
262 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
263 val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
264 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
265 /* Deactivate VCXO if noone else is using VCXO */
266 if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
267 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
268 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
269 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
270 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
271 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
272 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
273}
274
275static void disable_i2s1_vcxo(void)
276{
277 u16 val;
278 unsigned long iflags;
279
280 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
281 /* Disable I2S1 use of the VCXO 26 MHz clock */
282 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
283 val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
284 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
285 /* Deactivate VCXO if noone else is using VCXO */
286 if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
287 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
288 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
289 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
290 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
291 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
292 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
293}
294#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
295
296
297static void syscon_clk_rate_set_mclk(unsigned long rate)
298{
299 u16 val;
300 u32 reg;
301 unsigned long iflags;
302
303 switch (rate) {
304 case 18900000:
305 val = 0x0054;
306 break;
307 case 20800000:
308 val = 0x0044;
309 break;
310 case 23100000:
311 val = 0x0043;
312 break;
313 case 26000000:
314 val = 0x0033;
315 break;
316 case 29700000:
317 val = 0x0032;
318 break;
319 case 34700000:
320 val = 0x0022;
321 break;
322 case 41600000:
323 val = 0x0021;
324 break;
325 case 52000000:
326 val = 0x0011;
327 break;
328 case 104000000:
329 val = 0x0000;
330 break;
331 default:
332 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
333 rate);
334 return;
335 }
336
337 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
338 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
339 ~U300_SYSCON_MMF0R_MASK;
340 writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
341 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
342}
343
344void syscon_clk_rate_set_cpuclk(unsigned long rate)
345{
346 u16 val;
347 unsigned long iflags;
348
349 switch (rate) {
350 case 13000000:
351 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
352 break;
353 case 52000000:
354 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
355 break;
356 case 104000000:
357 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
358 break;
359 case 208000000:
360 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
361 break;
362 default:
363 return;
364 }
365 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
366 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
367 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
368 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
369 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
370}
371EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
372
373void clk_disable(struct clk *clk)
374{
375 unsigned long iflags;
376
377 spin_lock_irqsave(&clk->lock, iflags);
378 if (clk->usecount > 0 && !(--clk->usecount)) {
379 /* some blocks lack clocking registers and cannot be disabled */
380 if (clk->disable)
381 clk->disable(clk);
382 if (likely((u32)clk->parent))
383 clk_disable(clk->parent);
384 }
385#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
386 if (unlikely(!strcmp(clk->name, "I2S0")))
387 disable_i2s0_vcxo();
388 if (unlikely(!strcmp(clk->name, "I2S1")))
389 disable_i2s1_vcxo();
390#endif
391 spin_unlock_irqrestore(&clk->lock, iflags);
392}
393EXPORT_SYMBOL(clk_disable);
394
395int clk_enable(struct clk *clk)
396{
397 int ret = 0;
398 unsigned long iflags;
399
400 spin_lock_irqsave(&clk->lock, iflags);
401 if (clk->usecount++ == 0) {
402 if (likely((u32)clk->parent))
403 ret = clk_enable(clk->parent);
404
405 if (unlikely(ret != 0))
406 clk->usecount--;
407 else {
408 /* remove reset line (we never enable reset again) */
409 syscon_block_reset_disable(clk);
410 /* clocks without enable function are always on */
411 if (clk->enable)
412 clk->enable(clk);
413#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
414 if (unlikely(!strcmp(clk->name, "I2S0")))
415 enable_i2s0_vcxo();
416 if (unlikely(!strcmp(clk->name, "I2S1")))
417 enable_i2s1_vcxo();
418#endif
419 }
420 }
421 spin_unlock_irqrestore(&clk->lock, iflags);
422 return ret;
423
424}
425EXPORT_SYMBOL(clk_enable);
426
427/* Returns the clock rate in Hz */
428static unsigned long clk_get_rate_cpuclk(struct clk *clk)
429{
430 u16 val;
431
432 val = syscon_clk_get_rate();
433
434 switch (val) {
435 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
437 return 13000000;
438 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
439 return 52000000;
440 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
441 return 104000000;
442 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
443 return 208000000;
444 default:
445 break;
446 }
447 return clk->rate;
448}
449
450static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
451{
452 u16 val;
453
454 val = syscon_clk_get_rate();
455
456 switch (val) {
457 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
459 return 6500000;
460 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
461 return 26000000;
462 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
464 return 52000000;
465 default:
466 break;
467 }
468 return clk->rate;
469
470}
471
472static unsigned long clk_get_rate_emif_clk(struct clk *clk)
473{
474 u16 val;
475
476 val = syscon_clk_get_rate();
477
478 switch (val) {
479 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
481 return 13000000;
482 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
483 return 52000000;
484 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
486 return 104000000;
487 default:
488 break;
489 }
490 return clk->rate;
491
492}
493
494static unsigned long clk_get_rate_xgamclk(struct clk *clk)
495{
496 u16 val;
497
498 val = syscon_clk_get_rate();
499
500 switch (val) {
501 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
503 return 6500000;
504 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
505 return 26000000;
506 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
508 return 52000000;
509 default:
510 break;
511 }
512
513 return clk->rate;
514}
515
516static unsigned long clk_get_rate_mclk(struct clk *clk)
517{
518 u16 val;
519
520 val = syscon_clk_get_rate();
521
522 switch (val) {
523 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
524 /*
525 * Here, the 208 MHz PLL gets shut down and the always
526 * on 13 MHz PLL used for RTC etc kicks into use
527 * instead.
528 */
529 return 13000000;
530 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
534 {
535 /*
536 * This clock is under program control. The register is
537 * divided in two nybbles, bit 7-4 gives cycles-1 to count
538 * high, bit 3-0 gives cycles-1 to count low. Distribute
539 * these with no more than 1 cycle difference between
540 * low and high and add low and high to get the actual
541 * divisor. The base PLL is 208 MHz. Writing 0x00 will
542 * divide by 1 and 1 so the highest frequency possible
543 * is 104 MHz.
544 *
545 * e.g. 0x54 =>
546 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
547 */
548 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
549 U300_SYSCON_MMF0R_MASK;
550 switch (val) {
551 case 0x0054:
552 return 18900000;
553 case 0x0044:
554 return 20800000;
555 case 0x0043:
556 return 23100000;
557 case 0x0033:
558 return 26000000;
559 case 0x0032:
560 return 29700000;
561 case 0x0022:
562 return 34700000;
563 case 0x0021:
564 return 41600000;
565 case 0x0011:
566 return 52000000;
567 case 0x0000:
568 return 104000000;
569 default:
570 break;
571 }
572 }
573 default:
574 break;
575 }
576
577 return clk->rate;
578}
579
580static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
581{
582 u16 val;
583
584 val = syscon_clk_get_rate();
585
586 switch (val) {
587 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
589 return 13000000;
590 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
593 return 26000000;
594 default:
595 break;
596 }
597
598 return clk->rate;
599}
600
601unsigned long clk_get_rate(struct clk *clk)
602{
603 if (clk->get_rate)
604 return clk->get_rate(clk);
605 else
606 return clk->rate;
607}
608EXPORT_SYMBOL(clk_get_rate);
609
610static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
611{
612 if (rate >= 18900000)
613 return 18900000;
614 if (rate >= 20800000)
615 return 20800000;
616 if (rate >= 23100000)
617 return 23100000;
618 if (rate >= 26000000)
619 return 26000000;
620 if (rate >= 29700000)
621 return 29700000;
622 if (rate >= 34700000)
623 return 34700000;
624 if (rate >= 41600000)
625 return 41600000;
626 if (rate >= 52000000)
627 return 52000000;
628 return -EINVAL;
629}
630
631static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
632{
633 if (rate >= 13000000)
634 return 13000000;
635 if (rate >= 52000000)
636 return 52000000;
637 if (rate >= 104000000)
638 return 104000000;
639 if (rate >= 208000000)
640 return 208000000;
641 return -EINVAL;
642}
643
644/*
645 * This adjusts a requested rate to the closest exact rate
646 * a certain clock can provide. For a fixed clock it's
647 * mostly clk->rate.
648 */
649long clk_round_rate(struct clk *clk, unsigned long rate)
650{
651 /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
652 /* Else default to fixed value */
653
654 if (clk->round_rate) {
655 return (long) clk->round_rate(clk, rate);
656 } else {
657 printk(KERN_ERR "clock: Failed to round rate of %s\n",
658 clk->name);
659 }
660 return (long) clk->rate;
661}
662EXPORT_SYMBOL(clk_round_rate);
663
664static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
665{
666 syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
667 return 0;
668}
669
670static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
671{
672 syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
673 return 0;
674}
675
676int clk_set_rate(struct clk *clk, unsigned long rate)
677{
678 /* TODO: set for EMIFCLK and AHBCLK */
679 /* Else assume the clock is fixed and fail */
680 if (clk->set_rate) {
681 return clk->set_rate(clk, rate);
682 } else {
683 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
684 clk->name, rate);
685 return -EINVAL;
686 }
687}
688EXPORT_SYMBOL(clk_set_rate);
689
690/*
691 * Clock definitions. The clock parents are set to respective
692 * bridge and the clock framework makes sure that the clocks have
693 * parents activated and are brought out of reset when in use.
694 *
695 * Clocks that have hw_ctrld = true are hw controlled, and the hw
696 * can by itself turn these clocks on and off.
697 * So in other words, we don't really have to care about them.
698 */
699
700static struct clk amba_clk = {
701 .name = "AMBA",
702 .rate = 52000000, /* this varies! */
703 .hw_ctrld = true,
704 .reset = false,
705};
706
707/*
708 * These blocks are connected directly to the AMBA bus
709 * with no bridge.
710 */
711
712static struct clk cpu_clk = {
713 .name = "CPU",
714 .parent = &amba_clk,
715 .rate = 208000000, /* this varies! */
716 .hw_ctrld = true,
717 .reset = true,
718 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
719 .res_mask = U300_SYSCON_RRR_CPU_RESET_EN,
720 .set_rate = clk_set_rate_cpuclk,
721 .get_rate = clk_get_rate_cpuclk,
722 .round_rate = clk_round_rate_cpuclk,
723};
724
725static struct clk nandif_clk = {
726 .name = "NANDIF",
727 .parent = &amba_clk,
728 .hw_ctrld = false,
729 .reset = true,
730 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
731 .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN,
732 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
733 .enable = syscon_clk_enable,
734 .disable = syscon_clk_disable,
735};
736
737static struct clk semi_clk = {
738 .name = "SEMI",
739 .parent = &amba_clk,
740 .rate = 0, /* FIXME */
741 /* It is not possible to reset SEMI */
742 .hw_ctrld = false,
743 .reset = false,
744 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
745 .enable = syscon_clk_enable,
746 .disable = syscon_clk_disable,
747};
748
749#ifdef CONFIG_MACH_U300_BS335
750static struct clk isp_clk = {
751 .name = "ISP",
752 .parent = &amba_clk,
753 .rate = 0, /* FIXME */
754 .hw_ctrld = false,
755 .reset = true,
756 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
757 .res_mask = U300_SYSCON_RRR_ISP_RESET_EN,
758 .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN,
759 .enable = syscon_clk_enable,
760 .disable = syscon_clk_disable,
761};
762
763static struct clk cds_clk = {
764 .name = "CDS",
765 .parent = &amba_clk,
766 .rate = 0, /* FIXME */
767 .hw_ctrld = false,
768 .reset = true,
769 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
770 .res_mask = U300_SYSCON_RRR_CDS_RESET_EN,
771 .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN,
772 .enable = syscon_clk_enable,
773 .disable = syscon_clk_disable,
774};
775#endif
776
777static struct clk dma_clk = {
778 .name = "DMA",
779 .parent = &amba_clk,
780 .rate = 52000000, /* this varies! */
781 .hw_ctrld = true,
782 .reset = true,
783 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
784 .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN,
785 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
786 .enable = syscon_clk_enable,
787 .disable = syscon_clk_disable,
788};
789
790static struct clk aaif_clk = {
791 .name = "AAIF",
792 .parent = &amba_clk,
793 .rate = 52000000, /* this varies! */
794 .hw_ctrld = true,
795 .reset = true,
796 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
797 .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN,
798 .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN,
799 .enable = syscon_clk_enable,
800 .disable = syscon_clk_disable,
801};
802
803static struct clk apex_clk = {
804 .name = "APEX",
805 .parent = &amba_clk,
806 .rate = 0, /* FIXME */
807 .hw_ctrld = true,
808 .reset = true,
809 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
810 .res_mask = U300_SYSCON_RRR_APEX_RESET_EN,
811 .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN,
812 .enable = syscon_clk_enable,
813 .disable = syscon_clk_disable,
814};
815
816static struct clk video_enc_clk = {
817 .name = "VIDEO_ENC",
818 .parent = &amba_clk,
819 .rate = 208000000, /* this varies! */
820 .hw_ctrld = false,
821 .reset = false,
822 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
823 /* This has XGAM in the name but refers to the video encoder */
824 .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
825 .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
826 .enable = syscon_clk_enable,
827 .disable = syscon_clk_disable,
828};
829
830static struct clk xgam_clk = {
831 .name = "XGAMCLK",
832 .parent = &amba_clk,
833 .rate = 52000000, /* this varies! */
834 .hw_ctrld = false,
835 .reset = true,
836 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
837 .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN,
838 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
839 .get_rate = clk_get_rate_xgamclk,
840 .enable = syscon_clk_enable,
841 .disable = syscon_clk_disable,
842};
843
844/* This clock is used to activate the video encoder */
845static struct clk ahb_clk = {
846 .name = "AHB",
847 .parent = &amba_clk,
848 .rate = 52000000, /* this varies! */
849 .hw_ctrld = false, /* This one is set to false due to HW bug */
850 .reset = true,
851 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
852 .res_mask = U300_SYSCON_RRR_AHB_RESET_EN,
853 .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN,
854 .enable = syscon_clk_enable,
855 .disable = syscon_clk_disable,
856 .get_rate = clk_get_rate_ahb_clk,
857};
858
859
860/*
861 * Clocks on the AHB bridge
862 */
863
864static struct clk ahb_subsys_clk = {
865 .name = "AHB_SUBSYS",
866 .parent = &amba_clk,
867 .rate = 52000000, /* this varies! */
868 .hw_ctrld = true,
869 .reset = false,
870 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
871 .enable = syscon_clk_enable,
872 .disable = syscon_clk_disable,
873 .get_rate = clk_get_rate_ahb_clk,
874};
875
876static struct clk intcon_clk = {
877 .name = "INTCON",
878 .parent = &ahb_subsys_clk,
879 .rate = 52000000, /* this varies! */
880 .hw_ctrld = false,
881 .reset = true,
882 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
883 .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN,
884 /* INTCON can be reset but not clock-gated */
885};
886
887static struct clk mspro_clk = {
888 .name = "MSPRO",
889 .parent = &ahb_subsys_clk,
890 .rate = 0, /* FIXME */
891 .hw_ctrld = false,
892 .reset = true,
893 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
894 .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN,
895 .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN,
896 .enable = syscon_clk_enable,
897 .disable = syscon_clk_disable,
898};
899
900static struct clk emif_clk = {
901 .name = "EMIF",
902 .parent = &ahb_subsys_clk,
903 .rate = 104000000, /* this varies! */
904 .hw_ctrld = false,
905 .reset = true,
906 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
907 .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN,
908 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
909 .enable = syscon_clk_enable,
910 .disable = syscon_clk_disable,
911 .get_rate = clk_get_rate_emif_clk,
912};
913
914
915/*
916 * Clocks on the FAST bridge
917 */
918static struct clk fast_clk = {
919 .name = "FAST_BRIDGE",
920 .parent = &amba_clk,
921 .rate = 13000000, /* this varies! */
922 .hw_ctrld = true,
923 .reset = true,
924 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
925 .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
926 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
927 .enable = syscon_clk_enable,
928 .disable = syscon_clk_disable,
929};
930
931static struct clk mmcsd_clk = {
932 .name = "MCLK",
933 .parent = &fast_clk,
934 .rate = 18900000, /* this varies! */
935 .hw_ctrld = false,
936 .reset = true,
937 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
938 .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE,
939 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
940 .get_rate = clk_get_rate_mclk,
941 .set_rate = clk_set_rate_mclk,
942 .round_rate = clk_round_rate_mclk,
943 .disable = syscon_clk_disable,
944 .enable = syscon_clk_enable,
945};
946
947static struct clk i2s0_clk = {
948 .name = "i2s0",
949 .parent = &fast_clk,
950 .rate = 26000000, /* this varies! */
951 .hw_ctrld = true,
952 .reset = true,
953 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
954 .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
955 .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
956 .enable = syscon_clk_enable,
957 .disable = syscon_clk_disable,
958 .get_rate = clk_get_rate_i2s_i2c_spi,
959};
960
961static struct clk i2s1_clk = {
962 .name = "i2s1",
963 .parent = &fast_clk,
964 .rate = 26000000, /* this varies! */
965 .hw_ctrld = true,
966 .reset = true,
967 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
968 .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
969 .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
970 .enable = syscon_clk_enable,
971 .disable = syscon_clk_disable,
972 .get_rate = clk_get_rate_i2s_i2c_spi,
973};
974
975static struct clk i2c0_clk = {
976 .name = "I2C0",
977 .parent = &fast_clk,
978 .rate = 26000000, /* this varies! */
979 .hw_ctrld = false,
980 .reset = true,
981 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
982 .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
983 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
984 .enable = syscon_clk_enable,
985 .disable = syscon_clk_disable,
986 .get_rate = clk_get_rate_i2s_i2c_spi,
987};
988
989static struct clk i2c1_clk = {
990 .name = "I2C1",
991 .parent = &fast_clk,
992 .rate = 26000000, /* this varies! */
993 .hw_ctrld = false,
994 .reset = true,
995 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
996 .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
997 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
998 .enable = syscon_clk_enable,
999 .disable = syscon_clk_disable,
1000 .get_rate = clk_get_rate_i2s_i2c_spi,
1001};
1002
1003static struct clk spi_clk = {
1004 .name = "SPI",
1005 .parent = &fast_clk,
1006 .rate = 26000000, /* this varies! */
1007 .hw_ctrld = false,
1008 .reset = true,
1009 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1010 .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1011 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
1012 .enable = syscon_clk_enable,
1013 .disable = syscon_clk_disable,
1014 .get_rate = clk_get_rate_i2s_i2c_spi,
1015};
1016
1017#ifdef CONFIG_MACH_U300_BS335
1018static struct clk uart1_clk = {
1019 .name = "UART1",
1020 .parent = &fast_clk,
1021 .rate = 13000000,
1022 .hw_ctrld = false,
1023 .reset = true,
1024 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1025 .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1026 .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
1027 .enable = syscon_clk_enable,
1028 .disable = syscon_clk_disable,
1029};
1030#endif
1031
1032
1033/*
1034 * Clocks on the SLOW bridge
1035 */
1036static struct clk slow_clk = {
1037 .name = "SLOW_BRIDGE",
1038 .parent = &amba_clk,
1039 .rate = 13000000,
1040 .hw_ctrld = true,
1041 .reset = true,
1042 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1043 .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1044 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1045 .enable = syscon_clk_enable,
1046 .disable = syscon_clk_disable,
1047};
1048
1049/* TODO: implement SYSCON clock? */
1050
1051static struct clk wdog_clk = {
1052 .name = "WDOG",
1053 .parent = &slow_clk,
1054 .hw_ctrld = false,
1055 .rate = 32768,
1056 .reset = false,
1057 /* This is always on, cannot be enabled/disabled or reset */
1058};
1059
1060/* This one is hardwired to PLL13 */
1061static struct clk uart_clk = {
1062 .name = "UARTCLK",
1063 .parent = &slow_clk,
1064 .rate = 13000000,
1065 .hw_ctrld = false,
1066 .reset = true,
1067 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1068 .res_mask = U300_SYSCON_RSR_UART_RESET_EN,
1069 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
1070 .enable = syscon_clk_enable,
1071 .disable = syscon_clk_disable,
1072};
1073
1074static struct clk keypad_clk = {
1075 .name = "KEYPAD",
1076 .parent = &slow_clk,
1077 .rate = 32768,
1078 .hw_ctrld = false,
1079 .reset = true,
1080 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1081 .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1082 .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1083 .enable = syscon_clk_enable,
1084 .disable = syscon_clk_disable,
1085};
1086
1087static struct clk gpio_clk = {
1088 .name = "GPIO",
1089 .parent = &slow_clk,
1090 .rate = 13000000,
1091 .hw_ctrld = true,
1092 .reset = true,
1093 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1094 .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN,
1095 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
1096 .enable = syscon_clk_enable,
1097 .disable = syscon_clk_disable,
1098};
1099
1100static struct clk rtc_clk = {
1101 .name = "RTC",
1102 .parent = &slow_clk,
1103 .rate = 32768,
1104 .hw_ctrld = true,
1105 .reset = true,
1106 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1107 .res_mask = U300_SYSCON_RSR_RTC_RESET_EN,
1108 /* This clock is always on, cannot be enabled/disabled */
1109};
1110
1111static struct clk bustr_clk = {
1112 .name = "BUSTR",
1113 .parent = &slow_clk,
1114 .rate = 13000000,
1115 .hw_ctrld = true,
1116 .reset = true,
1117 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1118 .res_mask = U300_SYSCON_RSR_BTR_RESET_EN,
1119 .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN,
1120 .enable = syscon_clk_enable,
1121 .disable = syscon_clk_disable,
1122};
1123
1124static struct clk evhist_clk = {
1125 .name = "EVHIST",
1126 .parent = &slow_clk,
1127 .rate = 13000000,
1128 .hw_ctrld = true,
1129 .reset = true,
1130 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1131 .res_mask = U300_SYSCON_RSR_EH_RESET_EN,
1132 .clk_val = U300_SYSCON_SBCER_EH_CLK_EN,
1133 .enable = syscon_clk_enable,
1134 .disable = syscon_clk_disable,
1135};
1136
1137static struct clk timer_clk = {
1138 .name = "TIMER",
1139 .parent = &slow_clk,
1140 .rate = 13000000,
1141 .hw_ctrld = true,
1142 .reset = true,
1143 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1144 .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1145 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1146 .enable = syscon_clk_enable,
1147 .disable = syscon_clk_disable,
1148};
1149
1150static struct clk app_timer_clk = {
1151 .name = "TIMER_APP",
1152 .parent = &slow_clk,
1153 .rate = 13000000,
1154 .hw_ctrld = true,
1155 .reset = true,
1156 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1157 .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1158 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1159 .enable = syscon_clk_enable,
1160 .disable = syscon_clk_disable,
1161};
1162
1163#ifdef CONFIG_MACH_U300_BS335
1164static struct clk ppm_clk = {
1165 .name = "PPM",
1166 .parent = &slow_clk,
1167 .rate = 0, /* FIXME */
1168 .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */
1169 .reset = true,
1170 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1171 .res_mask = U300_SYSCON_RSR_PPM_RESET_EN,
1172 .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN,
1173 .enable = syscon_clk_enable,
1174 .disable = syscon_clk_disable,
1175};
1176#endif
1177
1178#define DEF_LOOKUP(devid, clkref) \
1179 { \
1180 .dev_id = devid, \
1181 .clk = clkref, \
1182 }
1183
1184/*
1185 * Here we only define clocks that are meaningful to
1186 * look up through clockdevice.
1187 */
1188static struct clk_lookup lookups[] = {
1189 /* Connected directly to the AMBA bus */
1190 DEF_LOOKUP("amba", &amba_clk),
1191 DEF_LOOKUP("cpu", &cpu_clk),
1192 DEF_LOOKUP("nandif", &nandif_clk),
1193 DEF_LOOKUP("semi", &semi_clk),
1194#ifdef CONFIG_MACH_U300_BS335
1195 DEF_LOOKUP("isp", &isp_clk),
1196 DEF_LOOKUP("cds", &cds_clk),
1197#endif
1198 DEF_LOOKUP("dma", &dma_clk),
1199 DEF_LOOKUP("aaif", &aaif_clk),
1200 DEF_LOOKUP("apex", &apex_clk),
1201 DEF_LOOKUP("video_enc", &video_enc_clk),
1202 DEF_LOOKUP("xgam", &xgam_clk),
1203 DEF_LOOKUP("ahb", &ahb_clk),
1204 /* AHB bridge clocks */
1205 DEF_LOOKUP("ahb", &ahb_subsys_clk),
1206 DEF_LOOKUP("intcon", &intcon_clk),
1207 DEF_LOOKUP("mspro", &mspro_clk),
1208 DEF_LOOKUP("pl172", &emif_clk),
1209 /* FAST bridge clocks */
1210 DEF_LOOKUP("fast", &fast_clk),
1211 DEF_LOOKUP("mmci", &mmcsd_clk),
1212 /*
1213 * The .0 and .1 identifiers on these comes from the platform device
1214 * .id field and are assigned when the platform devices are registered.
1215 */
1216 DEF_LOOKUP("i2s.0", &i2s0_clk),
1217 DEF_LOOKUP("i2s.1", &i2s1_clk),
1218 DEF_LOOKUP("stddci2c.0", &i2c0_clk),
1219 DEF_LOOKUP("stddci2c.1", &i2c1_clk),
1220 DEF_LOOKUP("pl022", &spi_clk),
1221#ifdef CONFIG_MACH_U300_BS335
1222 DEF_LOOKUP("uart1", &uart1_clk),
1223#endif
1224 /* SLOW bridge clocks */
1225 DEF_LOOKUP("slow", &slow_clk),
1226 DEF_LOOKUP("wdog", &wdog_clk),
1227 DEF_LOOKUP("uart0", &uart_clk),
1228 DEF_LOOKUP("apptimer", &app_timer_clk),
1229 DEF_LOOKUP("keypad", &keypad_clk),
1230 DEF_LOOKUP("u300-gpio", &gpio_clk),
1231 DEF_LOOKUP("rtc0", &rtc_clk),
1232 DEF_LOOKUP("bustr", &bustr_clk),
1233 DEF_LOOKUP("evhist", &evhist_clk),
1234 DEF_LOOKUP("timer", &timer_clk),
1235#ifdef CONFIG_MACH_U300_BS335
1236 DEF_LOOKUP("ppm", &ppm_clk),
1237#endif
1238};
1239
1240static void __init clk_register(void)
1241{
1242 int i;
1243
1244 /* Register the lookups */
1245 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1246 clkdev_add(&lookups[i]);
1247}
1248
1249/*
1250 * These are the clocks for cells registered as primecell drivers
1251 * on the AMBA bus. These must be on during AMBA device registration
1252 * since the bus probe will attempt to read magic configuration
1253 * registers for these devices. If they are deactivated these probes
1254 * will fail.
1255 *
1256 *
1257 * Please note that on emif, both RAM and NAND is connected in dual
1258 * RAM phones. On single RAM phones, ram is on semi and NAND on emif.
1259 *
1260 */
1261void u300_clock_primecells(void)
1262{
1263 clk_enable(&intcon_clk);
1264 clk_enable(&uart_clk);
1265#ifdef CONFIG_MACH_U300_BS335
1266 clk_enable(&uart1_clk);
1267#endif
1268 clk_enable(&spi_clk);
1269
1270 clk_enable(&mmcsd_clk);
1271
1272}
1273EXPORT_SYMBOL(u300_clock_primecells);
1274
1275void u300_unclock_primecells(void)
1276{
1277
1278 clk_disable(&intcon_clk);
1279 clk_disable(&uart_clk);
1280#ifdef CONFIG_MACH_U300_BS335
1281 clk_disable(&uart1_clk);
1282#endif
1283 clk_disable(&spi_clk);
1284 clk_disable(&mmcsd_clk);
1285
1286}
1287EXPORT_SYMBOL(u300_unclock_primecells);
1288
1289/*
1290 * The interrupt controller is enabled before the clock API is registered.
1291 */
1292void u300_enable_intcon_clock(void)
1293{
1294 clk_enable(&intcon_clk);
1295}
1296EXPORT_SYMBOL(u300_enable_intcon_clock);
1297
1298/*
1299 * The timer is enabled before the clock API is registered.
1300 */
1301void u300_enable_timer_clock(void)
1302{
1303 clk_enable(&app_timer_clk);
1304}
1305EXPORT_SYMBOL(u300_enable_timer_clock);
1306
1307#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1308/*
1309 * The following makes it possible to view the status (especially
1310 * reference count and reset status) for the clocks in the platform
1311 * by looking into the special file <debugfs>/u300_clocks
1312 */
1313
1314/* A list of all clocks in the platform */
1315static struct clk *clks[] = {
1316 /* Top node clock for the AMBA bus */
1317 &amba_clk,
1318 /* Connected directly to the AMBA bus */
1319 &cpu_clk,
1320 &nandif_clk,
1321 &semi_clk,
1322#ifdef CONFIG_MACH_U300_BS335
1323 &isp_clk,
1324 &cds_clk,
1325#endif
1326 &dma_clk,
1327 &aaif_clk,
1328 &apex_clk,
1329 &video_enc_clk,
1330 &xgam_clk,
1331 &ahb_clk,
1332
1333 /* AHB bridge clocks */
1334 &ahb_subsys_clk,
1335 &intcon_clk,
1336 &mspro_clk,
1337 &emif_clk,
1338 /* FAST bridge clocks */
1339 &fast_clk,
1340 &mmcsd_clk,
1341 &i2s0_clk,
1342 &i2s1_clk,
1343 &i2c0_clk,
1344 &i2c1_clk,
1345 &spi_clk,
1346#ifdef CONFIG_MACH_U300_BS335
1347 &uart1_clk,
1348#endif
1349 /* SLOW bridge clocks */
1350 &slow_clk,
1351 &wdog_clk,
1352 &uart_clk,
1353 &app_timer_clk,
1354 &keypad_clk,
1355 &gpio_clk,
1356 &rtc_clk,
1357 &bustr_clk,
1358 &evhist_clk,
1359 &timer_clk,
1360#ifdef CONFIG_MACH_U300_BS335
1361 &ppm_clk,
1362#endif
1363};
1364
1365static int u300_clocks_show(struct seq_file *s, void *data)
1366{
1367 struct clk *clk;
1368 int i;
1369
1370 seq_printf(s, "CLOCK DEVICE RESET STATE\t" \
1371 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1372 seq_printf(s, "---------------------------------------------" \
1373 "-----------------------------------------\n");
1374 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1375 clk = clks[i];
1376 if (clk != ERR_PTR(-ENOENT)) {
1377 /* Format clock and device name nicely */
1378 char cdp[33];
1379 int chars;
1380
1381 chars = snprintf(&cdp[0], 17, "%s", clk->name);
1382 while (chars < 16) {
1383 cdp[chars] = ' ';
1384 chars++;
1385 }
1386 chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1387 dev_name(clk->dev) : "N/A");
1388 while (chars < 16) {
1389 cdp[chars+16] = ' ';
1390 chars++;
1391 }
1392 cdp[32] = '\0';
1393 if (clk->get_rate)
1394 seq_printf(s,
1395 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1396 &cdp[0],
1397 clk->reset ?
1398 "ASSERTED" : "RELEASED",
1399 clk->usecount ? "ON" : "OFF",
1400 clk->usecount,
1401 clk->hw_ctrld ? "YES" : "NO ",
1402 clk->get_rate(clk));
1403 else
1404 seq_printf(s,
1405 "%s%s\t%s\t%d\t%s\t" \
1406 "(unknown rate)\n",
1407 &cdp[0],
1408 clk->reset ?
1409 "ASSERTED" : "RELEASED",
1410 clk->usecount ? "ON" : "OFF",
1411 clk->usecount,
1412 clk->hw_ctrld ? "YES" : "NO ");
1413 }
1414 }
1415 return 0;
1416}
1417
1418static int u300_clocks_open(struct inode *inode, struct file *file)
1419{
1420 return single_open(file, u300_clocks_show, NULL);
1421}
1422
1423static const struct file_operations u300_clocks_operations = {
1424 .open = u300_clocks_open,
1425 .read = seq_read,
1426 .llseek = seq_lseek,
1427 .release = single_release,
1428};
1429
1430static void init_clk_read_procfs(void)
1431{
1432 /* Expose a simple debugfs interface to view all clocks */
1433 (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1434 NULL, NULL, &u300_clocks_operations);
1435}
1436#else
1437static inline void init_clk_read_procfs(void)
1438{
1439}
1440#endif
1441
1442static int __init u300_clock_init(void)
1443{
1444 u16 val;
1445
1446 /*
1447 * FIXME: shall all this powermanagement stuff really live here???
1448 */
1449
1450 /* Set system to run at PLL208, max performance, a known state. */
1451 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1452 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1453 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1454 /* Wait for the PLL208 to lock if not locked in yet */
1455 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1456 U300_SYSCON_CSR_PLL208_LOCK_IND));
1457
1458 /* Power management enable */
1459 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1460 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1461 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1462
1463 clk_register();
1464
1465 init_clk_read_procfs();
1466
1467 /*
1468 * Some of these may be on when we boot the system so make sure they
1469 * are turned OFF.
1470 */
1471 syscon_block_reset_enable(&timer_clk);
1472 timer_clk.disable(&timer_clk);
1473
1474 /*
1475 * These shall be turned on by default when we boot the system
1476 * so make sure they are ON. (Adding CPU here is a bit too much.)
1477 * These clocks will be claimed by drivers later.
1478 */
1479 syscon_block_reset_disable(&semi_clk);
1480 syscon_block_reset_disable(&emif_clk);
1481 semi_clk.enable(&semi_clk);
1482 emif_clk.enable(&emif_clk);
1483
1484 return 0;
1485}
1486/* initialize clocking early to be available later in the boot */
1487core_initcall(u300_clock_init);
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
new file mode 100644
index 000000000000..fc6d9ccfe7e3
--- /dev/null
+++ b/arch/arm/mach-u300/clock.h
@@ -0,0 +1,53 @@
1/*
2 * arch/arm/mach-u300/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * Copyright (C) 2007-2009 ST-Ericsson AB
8 * Adopted to ST-Ericsson U300 platforms by
9 * Jonas Aaberg <jonas.aberg@stericsson.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#ifndef __MACH_CLOCK_H
18#define __MACH_CLOCK_H
19
20#include <linux/clk.h>
21
22struct clk {
23 struct list_head node;
24 struct module *owner;
25 struct device *dev;
26 const char *name;
27 struct clk *parent;
28
29 spinlock_t lock;
30 unsigned long rate;
31 bool reset;
32 __u16 clk_val;
33 __s8 usecount;
34 __u32 res_reg;
35 __u16 res_mask;
36
37 bool hw_ctrld;
38
39 void (*recalc) (struct clk *);
40 int (*set_rate) (struct clk *, unsigned long);
41 unsigned long (*get_rate) (struct clk *);
42 unsigned long (*round_rate) (struct clk *, unsigned long);
43 void (*init) (struct clk *);
44 void (*enable) (struct clk *);
45 void (*disable) (struct clk *);
46};
47
48void u300_clock_primecells(void);
49void u300_unclock_primecells(void);
50void u300_enable_intcon_clock(void);
51void u300_enable_timer_clock(void);
52
53#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
new file mode 100644
index 000000000000..89b3ccf35e1b
--- /dev/null
+++ b/arch/arm/mach-u300/core.c
@@ -0,0 +1,649 @@
1/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
19#include <linux/amba/bus.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22
23#include <asm/types.h>
24#include <asm/setup.h>
25#include <asm/memory.h>
26#include <asm/hardware/vic.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34#include "mmc.h"
35
36/*
37 * Static I/O mappings that are needed for booting the U300 platforms. The
38 * only things we need are the areas where we find the timer, syscon and
39 * intcon, since the remaining device drivers will map their own memory
40 * physical to virtual as the need arise.
41 */
42static struct map_desc u300_io_desc[] __initdata = {
43 {
44 .virtual = U300_SLOW_PER_VIRT_BASE,
45 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
46 .length = SZ_64K,
47 .type = MT_DEVICE,
48 },
49 {
50 .virtual = U300_AHB_PER_VIRT_BASE,
51 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
52 .length = SZ_32K,
53 .type = MT_DEVICE,
54 },
55 {
56 .virtual = U300_FAST_PER_VIRT_BASE,
57 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
58 .length = SZ_32K,
59 .type = MT_DEVICE,
60 },
61 {
62 .virtual = 0xffff2000, /* TCM memory */
63 .pfn = __phys_to_pfn(0xffff2000),
64 .length = SZ_16K,
65 .type = MT_DEVICE,
66 },
67
68 /*
69 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
70 * may have to be moved to 0x00000000 in order to use the ROM.
71 */
72 /*
73 {
74 .virtual = U300_BOOTROM_VIRT_BASE,
75 .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
76 .length = SZ_64K,
77 .type = MT_ROM,
78 },
79 */
80};
81
82void __init u300_map_io(void)
83{
84 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
85}
86
87/*
88 * Declaration of devices found on the U300 board and
89 * their respective memory locations.
90 */
91static struct amba_device uart0_device = {
92 .dev = {
93 .init_name = "uart0", /* Slow device at 0x3000 offset */
94 .platform_data = NULL,
95 },
96 .res = {
97 .start = U300_UART0_BASE,
98 .end = U300_UART0_BASE + SZ_4K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 .irq = { IRQ_U300_UART0, NO_IRQ },
102};
103
104/* The U335 have an additional UART1 on the APP CPU */
105#ifdef CONFIG_MACH_U300_BS335
106static struct amba_device uart1_device = {
107 .dev = {
108 .init_name = "uart1", /* Fast device at 0x7000 offset */
109 .platform_data = NULL,
110 },
111 .res = {
112 .start = U300_UART1_BASE,
113 .end = U300_UART1_BASE + SZ_4K - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 .irq = { IRQ_U300_UART1, NO_IRQ },
117};
118#endif
119
120static struct amba_device pl172_device = {
121 .dev = {
122 .init_name = "pl172", /* AHB device at 0x4000 offset */
123 .platform_data = NULL,
124 },
125 .res = {
126 .start = U300_EMIF_CFG_BASE,
127 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
128 .flags = IORESOURCE_MEM,
129 },
130};
131
132
133/*
134 * Everything within this next ifdef deals with external devices connected to
135 * the APP SPI bus.
136 */
137static struct amba_device pl022_device = {
138 .dev = {
139 .coherent_dma_mask = ~0,
140 .init_name = "pl022", /* Fast device at 0x6000 offset */
141 },
142 .res = {
143 .start = U300_SPI_BASE,
144 .end = U300_SPI_BASE + SZ_4K - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 .irq = {IRQ_U300_SPI, NO_IRQ },
148 /*
149 * This device has a DMA channel but the Linux driver does not use
150 * it currently.
151 */
152};
153
154static struct amba_device mmcsd_device = {
155 .dev = {
156 .init_name = "mmci", /* Fast device at 0x1000 offset */
157 .platform_data = NULL, /* Added later */
158 },
159 .res = {
160 .start = U300_MMCSD_BASE,
161 .end = U300_MMCSD_BASE + SZ_4K - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
165 /*
166 * This device has a DMA channel but the Linux driver does not use
167 * it currently.
168 */
169};
170
171/*
172 * The order of device declaration may be important, since some devices
173 * have dependencies on other devices being initialized first.
174 */
175static struct amba_device *amba_devs[] __initdata = {
176 &uart0_device,
177#ifdef CONFIG_MACH_U300_BS335
178 &uart1_device,
179#endif
180 &pl022_device,
181 &pl172_device,
182 &mmcsd_device,
183};
184
185/* Here follows a list of all hw resources that the platform devices
186 * allocate. Note, clock dependencies are not included
187 */
188
189static struct resource gpio_resources[] = {
190 {
191 .start = U300_GPIO_BASE,
192 .end = (U300_GPIO_BASE + SZ_4K - 1),
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .name = "gpio0",
197 .start = IRQ_U300_GPIO_PORT0,
198 .end = IRQ_U300_GPIO_PORT0,
199 .flags = IORESOURCE_IRQ,
200 },
201 {
202 .name = "gpio1",
203 .start = IRQ_U300_GPIO_PORT1,
204 .end = IRQ_U300_GPIO_PORT1,
205 .flags = IORESOURCE_IRQ,
206 },
207 {
208 .name = "gpio2",
209 .start = IRQ_U300_GPIO_PORT2,
210 .end = IRQ_U300_GPIO_PORT2,
211 .flags = IORESOURCE_IRQ,
212 },
213#ifdef U300_COH901571_3
214 {
215 .name = "gpio3",
216 .start = IRQ_U300_GPIO_PORT3,
217 .end = IRQ_U300_GPIO_PORT3,
218 .flags = IORESOURCE_IRQ,
219 },
220 {
221 .name = "gpio4",
222 .start = IRQ_U300_GPIO_PORT4,
223 .end = IRQ_U300_GPIO_PORT4,
224 .flags = IORESOURCE_IRQ,
225 },
226#ifdef CONFIG_MACH_U300_BS335
227 {
228 .name = "gpio5",
229 .start = IRQ_U300_GPIO_PORT5,
230 .end = IRQ_U300_GPIO_PORT5,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .name = "gpio6",
235 .start = IRQ_U300_GPIO_PORT6,
236 .end = IRQ_U300_GPIO_PORT6,
237 .flags = IORESOURCE_IRQ,
238 },
239#endif /* CONFIG_MACH_U300_BS335 */
240#endif /* U300_COH901571_3 */
241};
242
243static struct resource keypad_resources[] = {
244 {
245 .start = U300_KEYPAD_BASE,
246 .end = U300_KEYPAD_BASE + SZ_4K - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 {
250 .name = "coh901461-press",
251 .start = IRQ_U300_KEYPAD_KEYBF,
252 .end = IRQ_U300_KEYPAD_KEYBF,
253 .flags = IORESOURCE_IRQ,
254 },
255 {
256 .name = "coh901461-release",
257 .start = IRQ_U300_KEYPAD_KEYBR,
258 .end = IRQ_U300_KEYPAD_KEYBR,
259 .flags = IORESOURCE_IRQ,
260 },
261};
262
263static struct resource rtc_resources[] = {
264 {
265 .start = U300_RTC_BASE,
266 .end = U300_RTC_BASE + SZ_4K - 1,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .start = IRQ_U300_RTC,
271 .end = IRQ_U300_RTC,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276/*
277 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
278 * but these are not yet used by the driver.
279 */
280static struct resource fsmc_resources[] = {
281 {
282 .start = U300_NAND_IF_PHYS_BASE,
283 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
284 .flags = IORESOURCE_MEM,
285 },
286};
287
288static struct resource i2c0_resources[] = {
289 {
290 .start = U300_I2C0_BASE,
291 .end = U300_I2C0_BASE + SZ_4K - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = IRQ_U300_I2C0,
296 .end = IRQ_U300_I2C0,
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301static struct resource i2c1_resources[] = {
302 {
303 .start = U300_I2C1_BASE,
304 .end = U300_I2C1_BASE + SZ_4K - 1,
305 .flags = IORESOURCE_MEM,
306 },
307 {
308 .start = IRQ_U300_I2C1,
309 .end = IRQ_U300_I2C1,
310 .flags = IORESOURCE_IRQ,
311 },
312
313};
314
315static struct resource wdog_resources[] = {
316 {
317 .start = U300_WDOG_BASE,
318 .end = U300_WDOG_BASE + SZ_4K - 1,
319 .flags = IORESOURCE_MEM,
320 },
321 {
322 .start = IRQ_U300_WDOG,
323 .end = IRQ_U300_WDOG,
324 .flags = IORESOURCE_IRQ,
325 }
326};
327
328/* TODO: These should be protected by suitable #ifdef's */
329static struct resource ave_resources[] = {
330 {
331 .name = "AVE3e I/O Area",
332 .start = U300_VIDEOENC_BASE,
333 .end = U300_VIDEOENC_BASE + SZ_512K - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .name = "AVE3e IRQ0",
338 .start = IRQ_U300_VIDEO_ENC_0,
339 .end = IRQ_U300_VIDEO_ENC_0,
340 .flags = IORESOURCE_IRQ,
341 },
342 {
343 .name = "AVE3e IRQ1",
344 .start = IRQ_U300_VIDEO_ENC_1,
345 .end = IRQ_U300_VIDEO_ENC_1,
346 .flags = IORESOURCE_IRQ,
347 },
348 {
349 .name = "AVE3e Physmem Area",
350 .start = 0, /* 0 will be remapped to reserved memory */
351 .end = SZ_1M - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 /*
355 * The AVE3e requires two regions of 256MB that it considers
356 * "invisible". The hardware will not be able to access these
357 * adresses, so they should never point to system RAM.
358 */
359 {
360 .name = "AVE3e Reserved 0",
361 .start = 0xd0000000,
362 .end = 0xd0000000 + SZ_256M - 1,
363 .flags = IORESOURCE_MEM,
364 },
365 {
366 .name = "AVE3e Reserved 1",
367 .start = 0xe0000000,
368 .end = 0xe0000000 + SZ_256M - 1,
369 .flags = IORESOURCE_MEM,
370 },
371};
372
373static struct platform_device wdog_device = {
374 .name = "wdog",
375 .id = -1,
376 .num_resources = ARRAY_SIZE(wdog_resources),
377 .resource = wdog_resources,
378};
379
380static struct platform_device i2c0_device = {
381 .name = "stddci2c",
382 .id = 0,
383 .num_resources = ARRAY_SIZE(i2c0_resources),
384 .resource = i2c0_resources,
385};
386
387static struct platform_device i2c1_device = {
388 .name = "stddci2c",
389 .id = 1,
390 .num_resources = ARRAY_SIZE(i2c1_resources),
391 .resource = i2c1_resources,
392};
393
394static struct platform_device gpio_device = {
395 .name = "u300-gpio",
396 .id = -1,
397 .num_resources = ARRAY_SIZE(gpio_resources),
398 .resource = gpio_resources,
399};
400
401static struct platform_device keypad_device = {
402 .name = "keypad",
403 .id = -1,
404 .num_resources = ARRAY_SIZE(keypad_resources),
405 .resource = keypad_resources,
406};
407
408static struct platform_device rtc_device = {
409 .name = "rtc0",
410 .id = -1,
411 .num_resources = ARRAY_SIZE(rtc_resources),
412 .resource = rtc_resources,
413};
414
415static struct platform_device fsmc_device = {
416 .name = "nandif",
417 .id = -1,
418 .num_resources = ARRAY_SIZE(fsmc_resources),
419 .resource = fsmc_resources,
420};
421
422static struct platform_device ave_device = {
423 .name = "video_enc",
424 .id = -1,
425 .num_resources = ARRAY_SIZE(ave_resources),
426 .resource = ave_resources,
427};
428
429/*
430 * Notice that AMBA devices are initialized before platform devices.
431 *
432 */
433static struct platform_device *platform_devs[] __initdata = {
434 &i2c0_device,
435 &i2c1_device,
436 &keypad_device,
437 &rtc_device,
438 &gpio_device,
439 &fsmc_device,
440 &wdog_device,
441 &ave_device
442};
443
444
445/*
446 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
447 * together so some interrupts are connected to the first one and some
448 * to the second one.
449 */
450void __init u300_init_irq(void)
451{
452 u32 mask[2] = {0, 0};
453 int i;
454
455 for (i = 0; i < NR_IRQS; i++)
456 set_bit(i, (unsigned long *) &mask[0]);
457 u300_enable_intcon_clock();
458 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], 0);
459 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], 0);
460}
461
462
463/*
464 * U300 platforms peripheral handling
465 */
466struct db_chip {
467 u16 chipid;
468 const char *name;
469};
470
471/*
472 * This is a list of the Digital Baseband chips used in the U300 platform.
473 */
474static struct db_chip db_chips[] __initdata = {
475 {
476 .chipid = 0xb800,
477 .name = "DB3000",
478 },
479 {
480 .chipid = 0xc000,
481 .name = "DB3100",
482 },
483 {
484 .chipid = 0xc800,
485 .name = "DB3150",
486 },
487 {
488 .chipid = 0xd800,
489 .name = "DB3200",
490 },
491 {
492 .chipid = 0xe000,
493 .name = "DB3250",
494 },
495 {
496 .chipid = 0xe800,
497 .name = "DB3210",
498 },
499 {
500 .chipid = 0xf000,
501 .name = "DB3350 P1x",
502 },
503 {
504 .chipid = 0xf100,
505 .name = "DB3350 P2x",
506 },
507 {
508 .chipid = 0x0000, /* List terminator */
509 .name = NULL,
510 }
511};
512
513static void u300_init_check_chip(void)
514{
515
516 u16 val;
517 struct db_chip *chip;
518 const char *chipname;
519 const char unknown[] = "UNKNOWN";
520
521 /* Read out and print chip ID */
522 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
523 /* This is in funky bigendian order... */
524 val = (val & 0xFFU) << 8 | (val >> 8);
525 chip = db_chips;
526 chipname = unknown;
527
528 for ( ; chip->chipid; chip++) {
529 if (chip->chipid == (val & 0xFF00U)) {
530 chipname = chip->name;
531 break;
532 }
533 }
534 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
535 "(chip ID 0x%04x)\n", chipname, val);
536
537#ifdef CONFIG_MACH_U300_BS26
538 if ((val & 0xFF00U) != 0xc800) {
539 printk(KERN_ERR "Platform configured for BS25/BS26 " \
540 "with DB3150 but %s detected, expect problems!",
541 chipname);
542 }
543#endif
544#ifdef CONFIG_MACH_U300_BS330
545 if ((val & 0xFF00U) != 0xd800) {
546 printk(KERN_ERR "Platform configured for BS330 " \
547 "with DB3200 but %s detected, expect problems!",
548 chipname);
549 }
550#endif
551#ifdef CONFIG_MACH_U300_BS335
552 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
553 printk(KERN_ERR "Platform configured for BS365 " \
554 " with DB3350 but %s detected, expect problems!",
555 chipname);
556 }
557#endif
558#ifdef CONFIG_MACH_U300_BS365
559 if ((val & 0xFF00U) != 0xe800) {
560 printk(KERN_ERR "Platform configured for BS365 " \
561 "with DB3210 but %s detected, expect problems!",
562 chipname);
563 }
564#endif
565
566
567}
568
569/*
570 * Some devices and their resources require reserved physical memory from
571 * the end of the available RAM. This function traverses the list of devices
572 * and assigns actual adresses to these.
573 */
574static void __init u300_assign_physmem(void)
575{
576 unsigned long curr_start = __pa(high_memory);
577 int i, j;
578
579 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
580 for (j = 0; j < platform_devs[i]->num_resources; j++) {
581 struct resource *const res =
582 &platform_devs[i]->resource[j];
583
584 if (IORESOURCE_MEM == res->flags &&
585 0 == res->start) {
586 res->start = curr_start;
587 res->end += curr_start;
588 curr_start += (res->end - res->start + 1);
589
590 printk(KERN_INFO "core.c: Mapping RAM " \
591 "%#x-%#x to device %s:%s\n",
592 res->start, res->end,
593 platform_devs[i]->name, res->name);
594 }
595 }
596 }
597}
598
599void __init u300_init_devices(void)
600{
601 int i;
602 u16 val;
603
604 /* Check what platform we run and print some status information */
605 u300_init_check_chip();
606
607 /* Set system to run at PLL208, max performance, a known state. */
608 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
609 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
610 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
611 /* Wait for the PLL208 to lock if not locked in yet */
612 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
613 U300_SYSCON_CSR_PLL208_LOCK_IND));
614
615 /* Register the AMBA devices in the AMBA bus abstraction layer */
616 u300_clock_primecells();
617 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
618 struct amba_device *d = amba_devs[i];
619 amba_device_register(d, &iomem_resource);
620 }
621 u300_unclock_primecells();
622
623 u300_assign_physmem();
624
625 /* Register the platform devices */
626 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
627
628#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
629 /*
630 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
631 * both subsystems are requesting this mode.
632 * If we not share the Acc SDRAM, this is never the case. Therefore
633 * enable it here from the App side.
634 */
635 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
636 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
637 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
638#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
639}
640
641static int core_module_init(void)
642{
643 /*
644 * This needs to be initialized later: it needs the input framework
645 * to be initialized first.
646 */
647 return mmc_init(&mmcsd_device);
648}
649module_init(core_module_init);
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
new file mode 100644
index 000000000000..308cdb197a92
--- /dev/null
+++ b/arch/arm/mach-u300/gpio.c
@@ -0,0 +1,703 @@
1/*
2 *
3 * arch/arm/mach-u300/gpio.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 GPIO module.
9 * This can driver either of the two basic GPIO cores
10 * available in the U300 platforms:
11 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
12 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
13 * Notice that you also have inline macros in <asm-arch/gpio.h>
14 * Author: Linus Walleij <linus.walleij@stericsson.com>
15 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
16 *
17 */
18#include <linux/module.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27
28/* Need access to SYSCON registers for PADmuxing */
29#include <mach/syscon.h>
30
31#include "padmux.h"
32
33/* Reference to GPIO block clock */
34static struct clk *clk;
35
36/* Memory resource */
37static struct resource *memres;
38static void __iomem *virtbase;
39static struct device *gpiodev;
40
41struct u300_gpio_port {
42 const char *name;
43 int irq;
44 int number;
45};
46
47
48static struct u300_gpio_port gpio_ports[] = {
49 {
50 .name = "gpio0",
51 .number = 0,
52 },
53 {
54 .name = "gpio1",
55 .number = 1,
56 },
57 {
58 .name = "gpio2",
59 .number = 2,
60 },
61#ifdef U300_COH901571_3
62 {
63 .name = "gpio3",
64 .number = 3,
65 },
66 {
67 .name = "gpio4",
68 .number = 4,
69 },
70#ifdef CONFIG_MACH_U300_BS335
71 {
72 .name = "gpio5",
73 .number = 5,
74 },
75 {
76 .name = "gpio6",
77 .number = 6,
78 },
79#endif
80#endif
81
82};
83
84
85#ifdef U300_COH901571_3
86
87/* Default input value */
88#define DEFAULT_OUTPUT_LOW 0
89#define DEFAULT_OUTPUT_HIGH 1
90
91/* GPIO Pull-Up status */
92#define DISABLE_PULL_UP 0
93#define ENABLE_PULL_UP 1
94
95#define GPIO_NOT_USED 0
96#define GPIO_IN 1
97#define GPIO_OUT 2
98
99struct u300_gpio_configuration_data {
100 unsigned char pin_usage;
101 unsigned char default_output_value;
102 unsigned char pull_up;
103};
104
105/* Initial configuration */
106const struct u300_gpio_configuration_data
107u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
108#ifdef CONFIG_MACH_U300_BS335
109 /* Port 0, pins 0-7 */
110 {
111 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
112 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
113 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
114 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
115 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
116 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
117 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
118 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
119 },
120 /* Port 1, pins 0-7 */
121 {
122 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
123 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
124 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
125 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
126 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
127 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
128 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
129 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
130 },
131 /* Port 2, pins 0-7 */
132 {
133 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
134 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
135 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
136 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
137 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
138 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
139 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
140 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
141 },
142 /* Port 3, pins 0-7 */
143 {
144 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
145 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
146 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
147 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
148 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
149 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
152 },
153 /* Port 4, pins 0-7 */
154 {
155 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
156 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
157 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
158 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
159 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
160 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
163 },
164 /* Port 5, pins 0-7 */
165 {
166 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
167 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
168 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
169 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
170 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
171 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
174 },
175 /* Port 6, pind 0-7 */
176 {
177 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
178 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
179 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
180 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
181 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
182 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
183 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
184 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
185 }
186#endif
187
188#ifdef CONFIG_MACH_U300_BS365
189 /* Port 0, pins 0-7 */
190 {
191 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
192 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
193 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
194 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
195 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
196 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
197 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
199 },
200 /* Port 1, pins 0-7 */
201 {
202 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
203 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
204 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
205 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
206 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
207 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP},
208 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
209 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}
210 },
211 /* Port 2, pins 0-7 */
212 {
213 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
214 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
215 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
216 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP},
217 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
218 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
221 },
222 /* Port 3, pins 0-7 */
223 {
224 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
225 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
226 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
227 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
228 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
229 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
231 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
232 },
233 /* Port 4, pins 0-7 */
234 {
235 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
236 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
237 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
238 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
239 /* These 4 pins doesn't exist on DB3210 */
240 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
241 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
242 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP},
243 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}
244 }
245#endif
246};
247#endif
248
249
250/* No users == we can power down GPIO */
251static int gpio_users;
252
253struct gpio_struct {
254 int (*callback)(void *);
255 void *data;
256 int users;
257};
258
259static struct gpio_struct gpio_pin[U300_GPIO_MAX];
260
261/*
262 * Let drivers register callback in order to get notified when there is
263 * an interrupt on the gpio pin
264 */
265int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
266{
267 if (gpio_pin[gpio].callback)
268 dev_warn(gpiodev, "%s: WARNING: callback already "
269 "registered for gpio pin#%d\n", __func__, gpio);
270 gpio_pin[gpio].callback = func;
271 gpio_pin[gpio].data = data;
272
273 return 0;
274}
275EXPORT_SYMBOL(gpio_register_callback);
276
277int gpio_unregister_callback(unsigned gpio)
278{
279 if (!gpio_pin[gpio].callback)
280 dev_warn(gpiodev, "%s: WARNING: callback already "
281 "unregistered for gpio pin#%d\n", __func__, gpio);
282 gpio_pin[gpio].callback = NULL;
283 gpio_pin[gpio].data = NULL;
284
285 return 0;
286}
287EXPORT_SYMBOL(gpio_unregister_callback);
288
289int gpio_request(unsigned gpio, const char *label)
290{
291 if (gpio_pin[gpio].users)
292 return -EINVAL;
293 else
294 gpio_pin[gpio].users++;
295
296 gpio_users++;
297
298 return 0;
299}
300EXPORT_SYMBOL(gpio_request);
301
302void gpio_free(unsigned gpio)
303{
304 gpio_users--;
305 gpio_pin[gpio].users--;
306 if (unlikely(gpio_pin[gpio].users < 0)) {
307 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
308 gpio);
309 gpio_pin[gpio].users = 0;
310 }
311
312 return;
313}
314EXPORT_SYMBOL(gpio_free);
315
316/* This returns zero or nonzero */
317int gpio_get_value(unsigned gpio)
318{
319 return readl(virtbase + U300_GPIO_PXPDIR +
320 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
321}
322EXPORT_SYMBOL(gpio_get_value);
323
324/*
325 * We hope that the compiler will optimize away the unused branch
326 * in case "value" is a constant
327 */
328void gpio_set_value(unsigned gpio, int value)
329{
330 u32 val;
331 unsigned long flags;
332
333 local_irq_save(flags);
334 if (value) {
335 /* set */
336 val = readl(virtbase + U300_GPIO_PXPDOR +
337 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
338 & (1 << (gpio & 0x07));
339 writel(val | (1 << (gpio & 0x07)), virtbase +
340 U300_GPIO_PXPDOR +
341 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
342 } else {
343 /* clear */
344 val = readl(virtbase + U300_GPIO_PXPDOR +
345 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
346 & (1 << (gpio & 0x07));
347 writel(val & ~(1 << (gpio & 0x07)), virtbase +
348 U300_GPIO_PXPDOR +
349 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
350 }
351 local_irq_restore(flags);
352}
353EXPORT_SYMBOL(gpio_set_value);
354
355int gpio_direction_input(unsigned gpio)
356{
357 unsigned long flags;
358 u32 val;
359
360 if (gpio > U300_GPIO_MAX)
361 return -EINVAL;
362
363 local_irq_save(flags);
364 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
365 U300_GPIO_PORTX_SPACING);
366 /* Mask out this pin*/
367 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
368 /* This is not needed since it sets the bits to zero.*/
369 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
370 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
371 U300_GPIO_PORTX_SPACING);
372 local_irq_restore(flags);
373 return 0;
374}
375EXPORT_SYMBOL(gpio_direction_input);
376
377int gpio_direction_output(unsigned gpio, int value)
378{
379 unsigned long flags;
380 u32 val;
381
382 if (gpio > U300_GPIO_MAX)
383 return -EINVAL;
384
385 local_irq_save(flags);
386 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
387 U300_GPIO_PORTX_SPACING);
388 /* Mask out this pin */
389 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
390 /*
391 * FIXME: configure for push/pull, open drain or open source per pin
392 * in setup. The current driver will only support push/pull.
393 */
394 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
395 << ((gpio & 0x07) << 1));
396 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
397 U300_GPIO_PORTX_SPACING);
398 gpio_set_value(gpio, value);
399 local_irq_restore(flags);
400 return 0;
401}
402EXPORT_SYMBOL(gpio_direction_output);
403
404/*
405 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
406 */
407void enable_irq_on_gpio_pin(unsigned gpio, int edge)
408{
409 u32 val;
410 unsigned long flags;
411 local_irq_save(flags);
412
413 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
414 U300_GPIO_PORTX_SPACING);
415 val |= (1 << (gpio & 0x07));
416 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
417 U300_GPIO_PORTX_SPACING);
418 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
419 U300_GPIO_PORTX_SPACING);
420 if (edge)
421 val |= (1 << (gpio & 0x07));
422 else
423 val &= ~(1 << (gpio & 0x07));
424 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
425 U300_GPIO_PORTX_SPACING);
426 local_irq_restore(flags);
427}
428EXPORT_SYMBOL(enable_irq_on_gpio_pin);
429
430void disable_irq_on_gpio_pin(unsigned gpio)
431{
432 u32 val;
433 unsigned long flags;
434
435 local_irq_save(flags);
436 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
437 U300_GPIO_PORTX_SPACING);
438 val &= ~(1 << (gpio & 0x07));
439 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
440 U300_GPIO_PORTX_SPACING);
441 local_irq_restore(flags);
442}
443EXPORT_SYMBOL(disable_irq_on_gpio_pin);
444
445/* Enable (value == 0) or disable (value == 1) internal pullup */
446void gpio_pullup(unsigned gpio, int value)
447{
448 u32 val;
449 unsigned long flags;
450
451 local_irq_save(flags);
452 if (value) {
453 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
454 U300_GPIO_PORTX_SPACING);
455 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
456 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
457 } else {
458 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
459 U300_GPIO_PORTX_SPACING);
460 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
461 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
462 }
463 local_irq_restore(flags);
464}
465EXPORT_SYMBOL(gpio_pullup);
466
467static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
468{
469 struct u300_gpio_port *port = dev_id;
470 u32 val;
471 int pin;
472
473 /* Read event register */
474 val = readl(virtbase + U300_GPIO_PXIEV + port->number *
475 U300_GPIO_PORTX_SPACING);
476 /* Mask with enable register */
477 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
478 U300_GPIO_PORTX_SPACING);
479 /* Mask relevant bits */
480 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
481 /* ACK IRQ (clear event) */
482 writel(val, virtbase + U300_GPIO_PXIEV + port->number *
483 U300_GPIO_PORTX_SPACING);
484 /* Print message */
485 while (val != 0) {
486 unsigned gpio;
487
488 pin = __ffs(val);
489 /* mask off this pin */
490 val &= ~(1 << pin);
491 gpio = (port->number << 3) + pin;
492
493 if (gpio_pin[gpio].callback)
494 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
495 else
496 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
497 gpio);
498 }
499 return IRQ_HANDLED;
500}
501
502static void gpio_set_initial_values(void)
503{
504#ifdef U300_COH901571_3
505 int i, j;
506 unsigned long flags;
507 u32 val;
508
509 /* Write default values to all pins */
510 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
511 val = 0;
512 for (j = 0; j < 8; j++)
513 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
514 local_irq_save(flags);
515 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
516 local_irq_restore(flags);
517 }
518
519 /*
520 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
521 * to output and 'GPIO_IN' to input for each port. And initalize
522 * default value on outputs.
523 */
524 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
525 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
526 local_irq_save(flags);
527 val = readl(virtbase + U300_GPIO_PXPCR +
528 i * U300_GPIO_PORTX_SPACING);
529 /* Mask out this pin */
530 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
531
532 if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
533 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
534 writel(val, virtbase + U300_GPIO_PXPCR +
535 i * U300_GPIO_PORTX_SPACING);
536 local_irq_restore(flags);
537 }
538 }
539
540 /* Enable or disable the internal pull-ups in the GPIO ASIC block */
541 for (i = 0; i < U300_GPIO_MAX; i++) {
542 val = 0;
543 for (j = 0; j < 8; j++)
544 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
545 local_irq_save(flags);
546 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
547 local_irq_restore(flags);
548 }
549#endif
550}
551
552static int __init gpio_probe(struct platform_device *pdev)
553{
554 u32 val;
555 int err = 0;
556 int i;
557 int num_irqs;
558
559 gpiodev = &pdev->dev;
560 memset(gpio_pin, 0, sizeof(gpio_pin));
561
562 /* Get GPIO clock */
563 clk = clk_get(&pdev->dev, NULL);
564 if (IS_ERR(clk)) {
565 err = PTR_ERR(clk);
566 dev_err(gpiodev, "could not get GPIO clock\n");
567 goto err_no_clk;
568 }
569 err = clk_enable(clk);
570 if (err) {
571 dev_err(gpiodev, "could not enable GPIO clock\n");
572 goto err_no_clk_enable;
573 }
574
575 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
576 if (!memres)
577 goto err_no_resource;
578
579 if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
580 == NULL) {
581 err = -ENODEV;
582 goto err_no_ioregion;
583 }
584
585 virtbase = ioremap(memres->start, resource_size(memres));
586 if (!virtbase) {
587 err = -ENOMEM;
588 goto err_no_ioremap;
589 }
590 dev_info(gpiodev, "remapped 0x%08x to %p\n",
591 memres->start, virtbase);
592
593#ifdef U300_COH901335
594 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
595 /* Turn on the GPIO block */
596 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
597#endif
598
599#ifdef U300_COH901571_3
600 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
601 val = readl(virtbase + U300_GPIO_CR);
602 dev_info(gpiodev, "COH901571/3 block version: %d, " \
603 "number of cores: %d\n",
604 ((val & 0x0000FE00) >> 9),
605 ((val & 0x000001FC) >> 2));
606 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
607#endif
608
609 /* Set up some padmuxing here */
610#ifdef CONFIG_MMC
611 pmx_set_mission_mode_mmc();
612#endif
613#ifdef CONFIG_SPI_PL022
614 pmx_set_mission_mode_spi();
615#endif
616
617 gpio_set_initial_values();
618
619 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
620
621 gpio_ports[num_irqs].irq =
622 platform_get_irq_byname(pdev,
623 gpio_ports[num_irqs].name);
624
625 err = request_irq(gpio_ports[num_irqs].irq,
626 gpio_irq_handler, IRQF_DISABLED,
627 gpio_ports[num_irqs].name,
628 &gpio_ports[num_irqs]);
629 if (err) {
630 dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
631 gpio_ports[num_irqs].name);
632 goto err_no_irq;
633 }
634 /* Turns off PortX_irq_force */
635 writel(0x0, virtbase + U300_GPIO_PXIFR +
636 num_irqs * U300_GPIO_PORTX_SPACING);
637 }
638
639 return 0;
640
641 err_no_irq:
642 for (i = 0; i < num_irqs; i++)
643 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
644 iounmap(virtbase);
645 err_no_ioremap:
646 release_mem_region(memres->start, memres->end - memres->start);
647 err_no_ioregion:
648 err_no_resource:
649 clk_disable(clk);
650 err_no_clk_enable:
651 clk_put(clk);
652 err_no_clk:
653 dev_info(gpiodev, "module ERROR:%d\n", err);
654 return err;
655}
656
657static int __exit gpio_remove(struct platform_device *pdev)
658{
659 int i;
660
661 /* Turn off the GPIO block */
662 writel(0x00000000U, virtbase + U300_GPIO_CR);
663 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
664 free_irq(gpio_ports[i].irq, &gpio_ports[i]);
665 iounmap(virtbase);
666 release_mem_region(memres->start, memres->end - memres->start);
667 clk_disable(clk);
668 clk_put(clk);
669 return 0;
670}
671
672static struct platform_driver gpio_driver = {
673 .driver = {
674 .name = "u300-gpio",
675 },
676 .remove = __exit_p(gpio_remove),
677};
678
679
680static int __init u300_gpio_init(void)
681{
682 return platform_driver_probe(&gpio_driver, gpio_probe);
683}
684
685static void __exit u300_gpio_exit(void)
686{
687 platform_driver_unregister(&gpio_driver);
688}
689
690arch_initcall(u300_gpio_init);
691module_exit(u300_gpio_exit);
692
693MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
694
695#ifdef U300_COH901571_3
696MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
697#endif
698
699#ifdef U300_COH901335
700MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
701#endif
702
703MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
new file mode 100644
index 000000000000..92e3cc872c66
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H
2#define __MACH_CLKDEV_H
3
4int __clk_get(struct clk *clk);
5void __clk_put(struct clk *clk);
6
7#endif
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
new file mode 100644
index 000000000000..f3a1cbbeeab3
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
1/*
2 *
3 * arch-arm/mach-u300/include/mach/debug-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Debugging macro include header.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12
13 .macro addruart,rx
14 /* If we move the adress using MMU, use this. */
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 ldreq \rx, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
18 ldrne \rx, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
19 orr \rx, \rx, #0x00003000
20 .endm
21
22#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
new file mode 100644
index 000000000000..20731ae39d38
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
1/*
2 *
3 * arch-arm/mach-u300/include/mach/entry-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Low-level IRQ helper macros for ST-Ericsson U300
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/hardware/vic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
25 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
26 mov \irqnr, #0
27 teq \irqstat, #0
28 bne 1002f
291001: ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
30 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
31 mov \irqnr, #32
32 teq \irqstat, #0
33 beq 1003f
341002: tst \irqstat, #1
35 bne 1003f
36 add \irqnr, \irqnr, #1
37 movs \irqstat, \irqstat, lsr #1
38 bne 1002b
391003: /* EQ will be set if no irqs pending */
40 .endm
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
new file mode 100644
index 000000000000..c8174128d7eb
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -0,0 +1,290 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/gpio.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * GPIO block resgister definitions and inline macros for
9 * U300 GPIO COH 901 335 or COH 901 571/3
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_GPIO_H
14#define __MACH_U300_GPIO_H
15
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <mach/hardware.h>
19#include <asm/irq.h>
20
21/* Switch type depending on platform/chip variant */
22#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
23#define U300_COH901335
24#endif
25#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
26#define U300_COH901571_3
27#endif
28
29/* Get base address for regs here */
30#include "u300-regs.h"
31/* IRQ numbers */
32#include "irqs.h"
33
34/*
35 * This is the GPIO block definitions. GPIO (General Purpose I/O) can be
36 * used for anything, and often is. The event/enable etc figures are for
37 * the lowermost pin (pin 0 on each port), shift this left to match your
38 * pin if you're gonna use these values.
39 */
40#ifdef U300_COH901335
41#define U300_GPIO_PORTX_SPACING (0x1C)
42/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
43#define U300_GPIO_PXPDIR (0x00)
44#define U300_GPIO_PXPDOR (0x00)
45/* Port X Pin Config Register 32bit (R/W) */
46#define U300_GPIO_PXPCR (0x04)
47#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
48#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
49#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
50#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
51#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
52#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
53#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
54/* Port X Interrupt Event Register 32bit (R/W) */
55#define U300_GPIO_PXIEV (0x08)
56#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
57#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
58/* Port X Interrupt Enable Register 32bit (R/W) */
59#define U300_GPIO_PXIEN (0x0C)
60#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
61#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
62/* Port X Interrupt Force Register 32bit (R/W) */
63#define U300_GPIO_PXIFR (0x10)
64#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
65#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
66/* Port X Interrupt Config Register 32bit (R/W) */
67#define U300_GPIO_PXICR (0x14)
68#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
69#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
70#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
71#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
72/* Port X Pull-up Enable Register 32bit (R/W) */
73#define U300_GPIO_PXPER (0x18)
74#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
75#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
76/* Control Register 32bit (R/W) */
77#define U300_GPIO_CR (0x54)
78#define U300_GPIO_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
79/* three ports of 8 bits each = GPIO pins 0..23 */
80#define U300_GPIO_NUM_PORTS 3
81#define U300_GPIO_PINS_PER_PORT 8
82#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
83#endif
84
85#ifdef U300_COH901571_3
86/*
87 * Control Register 32bit (R/W)
88 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
89 * gives the number of GPIO pins.
90 * bit 8-2 (mask 0x000001FC) contains the core version ID.
91 */
92#define U300_GPIO_CR (0x00)
93#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
94#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
95#define U300_GPIO_PORTX_SPACING (0x30)
96/* Port X Pin Data INPUT Register 32bit (R/W) */
97#define U300_GPIO_PXPDIR (0x04)
98/* Port X Pin Data OUTPUT Register 32bit (R/W) */
99#define U300_GPIO_PXPDOR (0x08)
100/* Port X Pin Config Register 32bit (R/W) */
101#define U300_GPIO_PXPCR (0x0C)
102#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
103#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
104#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
105#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
106#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
107#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
108#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
109/* Port X Pull-up Enable Register 32bit (R/W) */
110#define U300_GPIO_PXPER (0x10)
111#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
112#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
113/* Port X Interrupt Event Register 32bit (R/W) */
114#define U300_GPIO_PXIEV (0x14)
115#define U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK (0x000000FFUL)
116#define U300_GPIO_PXIEV_IRQ_EVENT (0x00000001UL)
117/* Port X Interrupt Enable Register 32bit (R/W) */
118#define U300_GPIO_PXIEN (0x18)
119#define U300_GPIO_PXIEN_ALL_IRQ_ENABLE_MASK (0x000000FFUL)
120#define U300_GPIO_PXIEN_IRQ_ENABLE (0x00000001UL)
121/* Port X Interrupt Force Register 32bit (R/W) */
122#define U300_GPIO_PXIFR (0x1C)
123#define U300_GPIO_PXIFR_ALL_IRQ_FORCE_MASK (0x000000FFUL)
124#define U300_GPIO_PXIFR_IRQ_FORCE (0x00000001UL)
125/* Port X Interrupt Config Register 32bit (R/W) */
126#define U300_GPIO_PXICR (0x20)
127#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
128#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
129#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
130#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
131#ifdef CONFIG_MACH_U300_BS335
132/* seven ports of 8 bits each = GPIO pins 0..55 */
133#define U300_GPIO_NUM_PORTS 7
134#else
135/* five ports of 8 bits each = GPIO pins 0..39 */
136#define U300_GPIO_NUM_PORTS 5
137#endif
138#define U300_GPIO_PINS_PER_PORT 8
139#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS - 1)
140#endif
141
142/*
143 * Individual pin assignments for the B26/S26. Notice that the
144 * actual usage of these pins depends on the PAD MUX settings, that
145 * is why the same number can potentially appear several times.
146 * In the reference design each pin is only used for one purpose.
147 * These were determined by inspecting the B26/S26 schematic:
148 * 2/1911-ROA 128 1603
149 */
150#ifdef CONFIG_MACH_U300_BS2X
151#define U300_GPIO_PIN_UART_RX 0
152#define U300_GPIO_PIN_UART_TX 1
153#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
154#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
155#define U300_GPIO_PIN_CAM_SLEEP 4
156#define U300_GPIO_PIN_CAM_REG_EN 5
157#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
158#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
159
160#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
161#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
162#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
163#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
164#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
165#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
166#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
167#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
168
169#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
170#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
171#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
172#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
173#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
174#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
175#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
176#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
177#endif
178
179/*
180 * Individual pin assignments for the B330/S330 and B365/S365.
181 * Notice that the actual usage of these pins depends on the
182 * PAD MUX settings, that is why the same number can potentially
183 * appear several times. In the reference design each pin is only
184 * used for one purpose. These were determined by inspecting the
185 * S365 schematic.
186 */
187#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
188 defined(CONFIG_MACH_U300_BS335)
189#define U300_GPIO_PIN_UART_RX 0
190#define U300_GPIO_PIN_UART_TX 1
191#define U300_GPIO_PIN_UART_CTS 2
192#define U300_GPIO_PIN_UART_RTS 3
193#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
194#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
195#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
196#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
197
198#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
199#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
200#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
201#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
202#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
203#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
204#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
205#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
206
207#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
208#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
209#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
210#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
211#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
212#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
213#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
214#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
215
216#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
217#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
218#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
219#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
220#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
221#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
222#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
223#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
224
225#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
226#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
227#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
228#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
229#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
230#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
231#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
232#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
233
234#ifdef CONFIG_MACH_U300_BS335
235
236#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
237#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
238#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
239#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
240#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
241#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
242#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
243#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
244
245#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
246#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
247#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
248#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
249#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
250#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
251#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
252#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
253#endif
254
255#endif
256
257/* translates a pin number to a port number */
258#define PIN_TO_PORT(val) (val >> 3)
259
260/* These can be found in arch/arm/mach-u300/gpio.c */
261extern int gpio_request(unsigned gpio, const char *label);
262extern void gpio_free(unsigned gpio);
263extern int gpio_direction_input(unsigned gpio);
264extern int gpio_direction_output(unsigned gpio, int value);
265extern int gpio_register_callback(unsigned gpio,
266 int (*func)(void *arg),
267 void *);
268extern int gpio_unregister_callback(unsigned gpio);
269extern void enable_irq_on_gpio_pin(unsigned gpio, int edge);
270extern void disable_irq_on_gpio_pin(unsigned gpio);
271extern void gpio_pullup(unsigned gpio, int value);
272extern int gpio_get_value(unsigned gpio);
273extern void gpio_set_value(unsigned gpio, int value);
274
275/* wrappers to sleep-enable the previous two functions */
276static inline unsigned gpio_to_irq(unsigned gpio)
277{
278 return PIN_TO_PORT(gpio) + IRQ_U300_GPIO_PORT0;
279}
280
281static inline unsigned irq_to_gpio(unsigned irq)
282{
283 /*
284 * FIXME: This is no 1-1 mapping at all, it points to the
285 * whole block of 8 pins.
286 */
287 return (irq - IRQ_U300_GPIO_PORT0) << 3;
288}
289
290#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
new file mode 100644
index 000000000000..b99d4ce0ac2b
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/hardware.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-u300/include/mach/hardware.h
3 */
4#include <asm/sizes.h>
5#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
new file mode 100644
index 000000000000..5d6b4c13b3a0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -0,0 +1,20 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/io.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Dummy IO map for being able to use writew()/readw(),
9 * writel()/readw() and similar accessor functions.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12#ifndef __MACH_IO_H
13#define __MACH_IO_H
14
15#define IO_SPACE_LIMIT 0xffffffff
16
17#define __io(a) __typesafe_io(a)
18#define __mem_pci(a) (a)
19
20#endif
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
new file mode 100644
index 000000000000..a6867b12773e
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -0,0 +1,114 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/irqs.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * IRQ channel definitions for the U300 platforms.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#ifndef __MACH_IRQS_H
13#define __MACH_IRQS_H
14
15#define IRQ_U300_INTCON0_START 0
16#define IRQ_U300_INTCON1_START 32
17/* These are on INTCON0 - 30 lines */
18#define IRQ_U300_IRQ0_EXT 0
19#define IRQ_U300_IRQ1_EXT 1
20#define IRQ_U300_DMA 2
21#define IRQ_U300_VIDEO_ENC_0 3
22#define IRQ_U300_VIDEO_ENC_1 4
23#define IRQ_U300_AAIF_RX 5
24#define IRQ_U300_AAIF_TX 6
25#define IRQ_U300_AAIF_VGPIO 7
26#define IRQ_U300_AAIF_WAKEUP 8
27#define IRQ_U300_PCM_I2S0_FRAME 9
28#define IRQ_U300_PCM_I2S0_FIFO 10
29#define IRQ_U300_PCM_I2S1_FRAME 11
30#define IRQ_U300_PCM_I2S1_FIFO 12
31#define IRQ_U300_XGAM_GAMCON 13
32#define IRQ_U300_XGAM_CDI 14
33#define IRQ_U300_XGAM_CDICON 15
34#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
35/* MMIACC not used on the DB3210 or DB3350 chips */
36#define IRQ_U300_XGAM_MMIACC 16
37#endif
38#define IRQ_U300_XGAM_PDI 17
39#define IRQ_U300_XGAM_PDICON 18
40#define IRQ_U300_XGAM_GAMEACC 19
41#define IRQ_U300_XGAM_MCIDCT 20
42#define IRQ_U300_APEX 21
43#define IRQ_U300_UART0 22
44#define IRQ_U300_SPI 23
45#define IRQ_U300_TIMER_APP_OS 24
46#define IRQ_U300_TIMER_APP_DD 25
47#define IRQ_U300_TIMER_APP_GP1 26
48#define IRQ_U300_TIMER_APP_GP2 27
49#define IRQ_U300_TIMER_OS 28
50#define IRQ_U300_TIMER_MS 29
51#define IRQ_U300_KEYPAD_KEYBF 30
52#define IRQ_U300_KEYPAD_KEYBR 31
53/* These are on INTCON1 - 32 lines */
54#define IRQ_U300_GPIO_PORT0 32
55#define IRQ_U300_GPIO_PORT1 33
56#define IRQ_U300_GPIO_PORT2 34
57
58#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
59 defined(CONFIG_MACH_U300_BS335)
60/* These are for DB3150, DB3200 and DB3350 */
61#define IRQ_U300_WDOG 35
62#define IRQ_U300_EVHIST 36
63#define IRQ_U300_MSPRO 37
64#define IRQ_U300_MMCSD_MCIINTR0 38
65#define IRQ_U300_MMCSD_MCIINTR1 39
66#define IRQ_U300_I2C0 40
67#define IRQ_U300_I2C1 41
68#define IRQ_U300_RTC 42
69#define IRQ_U300_NFIF 43
70#define IRQ_U300_NFIF2 44
71#endif
72
73/* DB3150 and DB3200 have only 45 IRQs */
74#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
75#define U300_NR_IRQS 45
76#endif
77
78/* The DB3350-specific interrupt lines */
79#ifdef CONFIG_MACH_U300_BS335
80#define IRQ_U300_ISP_F0 45
81#define IRQ_U300_ISP_F1 46
82#define IRQ_U300_ISP_F2 47
83#define IRQ_U300_ISP_F3 48
84#define IRQ_U300_ISP_F4 49
85#define IRQ_U300_GPIO_PORT3 50
86#define IRQ_U300_SYSCON_PLL_LOCK 51
87#define IRQ_U300_UART1 52
88#define IRQ_U300_GPIO_PORT4 53
89#define IRQ_U300_GPIO_PORT5 54
90#define IRQ_U300_GPIO_PORT6 55
91#define U300_NR_IRQS 56
92#endif
93
94/* The DB3210-specific interrupt lines */
95#ifdef CONFIG_MACH_U300_BS365
96#define IRQ_U300_GPIO_PORT3 35
97#define IRQ_U300_GPIO_PORT4 36
98#define IRQ_U300_WDOG 37
99#define IRQ_U300_EVHIST 38
100#define IRQ_U300_MSPRO 39
101#define IRQ_U300_MMCSD_MCIINTR0 40
102#define IRQ_U300_MMCSD_MCIINTR1 41
103#define IRQ_U300_I2C0 42
104#define IRQ_U300_I2C1 43
105#define IRQ_U300_RTC 44
106#define IRQ_U300_NFIF 45
107#define IRQ_U300_NFIF2 46
108#define IRQ_U300_SYSCON_PLL_LOCK 47
109#define U300_NR_IRQS 48
110#endif
111
112#define NR_IRQS U300_NR_IRQS
113
114#endif
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
new file mode 100644
index 000000000000..bf134bcc129d
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/memory.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Memory virtual/physical mapping constants.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 */
12
13#ifndef __MACH_MEMORY_H
14#define __MACH_MEMORY_H
15
16#ifdef CONFIG_MACH_U300_DUAL_RAM
17
18#define PHYS_OFFSET UL(0x48000000)
19#define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100)
20
21#else
22
23#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
24#define PHYS_OFFSET (0x28000000 + \
25 (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
26 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
27#else
28#define PHYS_OFFSET (0x28000000 + \
29 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
30 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
31#endif
32#define BOOT_PARAMS_OFFSET (0x28000000 + \
33 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
34 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
35#endif
36
37/*
38 * We enable a real big DMA buffer if need be.
39 */
40#define CONSISTENT_DMA_SIZE SZ_4M
41
42#endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
new file mode 100644
index 000000000000..77d9210a82e2
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/platform.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/platform.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Basic platform init and mapping functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#ifndef __ASSEMBLY__
13
14void u300_map_io(void);
15void u300_init_irq(void);
16void u300_init_devices(void);
17extern struct sys_timer u300_timer;
18
19#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
new file mode 100644
index 000000000000..1c90d1b1ccb6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -0,0 +1,644 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/syscon.h
4 *
5 *
6 * Copyright (C) 2008 ST-Ericsson AB
7 *
8 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
9 */
10
11#ifndef __MACH_SYSCON_H
12#define __MACH_SYSCON_H
13
14/*
15 * All register defines for SYSCON registers that concerns individual
16 * block clocks and reset lines are registered here. This is because
17 * we don't want any other file to try to fool around with this stuff.
18 */
19
20/* APP side SYSCON registers */
21/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
22/* CLK Control Register 16bit (R/W) */
23#define U300_SYSCON_CCR (0x0000)
24#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
25#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
26#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
27#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
28#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
29#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
30#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
31#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
32#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
33/* CLK Status Register 16bit (R/W) */
34#define U300_SYSCON_CSR (0x0004)
35#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
36#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
37/* Reset lines for SLOW devices 16bit (R/W) */
38#define U300_SYSCON_RSR (0x0014)
39#ifdef CONFIG_MACH_U300_BS335
40#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
41#endif
42#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
43#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
44#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
45#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
46#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
47#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
48#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
49#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
50#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
51/* Reset lines for FAST devices 16bit (R/W) */
52#define U300_SYSCON_RFR (0x0018)
53#ifdef CONFIG_MACH_U300_BS335
54#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
55#endif
56#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
57#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
58#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
59#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
60#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
61#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
62#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
63/* Reset lines for the rest of the peripherals 16bit (R/W) */
64#define U300_SYSCON_RRR (0x001c)
65#ifdef CONFIG_MACH_U300_BS335
66#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
67#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
68#endif
69#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
70#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
71#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
72#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
73#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
74#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
75#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
76#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
77#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
78#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
79#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
80/* Clock enable for SLOW peripherals 16bit (R/W) */
81#define U300_SYSCON_CESR (0x0020)
82#ifdef CONFIG_MACH_U300_BS335
83#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
84#endif
85#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
86#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
87#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
88#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
89#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
90#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
91#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
92#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
93/* Clock enable for FAST peripherals 16bit (R/W) */
94#define U300_SYSCON_CEFR (0x0024)
95#ifdef CONFIG_MACH_U300_BS335
96#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
97#endif
98#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
99#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
100#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
101#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
102#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
103#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
104#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
105#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
106#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
107/* Clock enable for the rest of the peripherals 16bit (R/W) */
108#define U300_SYSCON_CERR (0x0028)
109#ifdef CONFIG_MACH_U300_BS335
110#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
111#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
112#endif
113#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
114#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
115#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
116#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
117#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
118#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
119#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
120#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
121#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
122#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
123#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
124#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
125/* Single block clock enable 16bit (-/W) */
126#define U300_SYSCON_SBCER (0x002c)
127#ifdef CONFIG_MACH_U300_BS335
128#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
129#endif
130#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
131#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
132#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
133#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
134#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
135#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
136#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
137#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
138#ifdef CONFIG_MACH_U300_BS335
139#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
140#endif
141#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
142#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
143#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
144#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
145#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
146#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
147#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
148#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
149#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
150#ifdef CONFIG_MACH_U300_BS335
151#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
152#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
153#endif
154#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
155#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
156#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
157#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
158#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
159#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
160#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
161#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
162#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
163#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
164#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
165#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
166/* Single block clock disable 16bit (-/W) */
167#define U300_SYSCON_SBCDR (0x0030)
168/* Same values as above for SBCER */
169/* Clock force SLOW peripherals 16bit (R/W) */
170#define U300_SYSCON_CFSR (0x003c)
171#ifdef CONFIG_MACH_U300_BS335
172#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
173#endif
174#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
175#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
176#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
177#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
178#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
179#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
180#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
181#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
182/* Clock force FAST peripherals 16bit (R/W) */
183#define U300_SYSCON_CFFR (0x40)
184/* Values not defined. Define if you want to use them. */
185/* Clock force the rest of the peripherals 16bit (R/W) */
186#define U300_SYSCON_CFRR (0x44)
187#ifdef CONFIG_MACH_U300_BS335
188#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
189#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
190#endif
191#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
192#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
193#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
194#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
195#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
196#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
197#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
198#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
199#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
200#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
201#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
202#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
203/* PLL208 Frequency Control 16bit (R/W) */
204#define U300_SYSCON_PFCR (0x48)
205#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
206/* Power Management Control 16bit (R/W) */
207#define U300_SYSCON_PMCR (0x50)
208#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
209#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
210/*
211 * All other clocking registers moved to clock.c!
212 */
213/* Reset Out 16bit (R/W) */
214#define U300_SYSCON_RCR (0x6c)
215#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
216/* EMIF Slew Rate Control 16bit (R/W) */
217#define U300_SYSCON_SRCLR (0x70)
218#define U300_SYSCON_SRCLR_MASK (0x03FF)
219#define U300_SYSCON_SRCLR_VALUE (0x03FF)
220#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
221#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
222#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
223#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
224#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
225#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
226#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
227#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
228#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
229#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
230/* EMIF Clock Control Register 16bit (R/W) */
231#define U300_SYSCON_ECCR (0x0078)
232#define U300_SYSCON_ECCR_MASK (0x000F)
233#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
234#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
235#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
236#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
237/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
238#define U300_SYSCON_PMC1LR (0x007C)
239#define U300_SYSCON_PMC1LR_MASK (0xFFFF)
240#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000)
241#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000)
242#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000)
243#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000)
244#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000)
245#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000)
246#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000)
247#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000)
248#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000)
249#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00)
250#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000)
251#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400)
252#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800)
253#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00)
254#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300)
255#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000)
256#define U300_SYSCON_PMC1LR_ETM_APP (0x0100)
257#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0)
258#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000)
259#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040)
260#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080)
261#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0)
262#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030)
263#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000)
264#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010)
265#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020)
266#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030)
267#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C)
268#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000)
269#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004)
270#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008)
271#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C)
272#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003)
273#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000)
274#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001)
275#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002)
276#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003)
277/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
278#define U300_SYSCON_PMC1HR (0x007E)
279#define U300_SYSCON_PMC1HR_MASK (0xFFFF)
280#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000)
281#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000)
282#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000)
283#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000)
284#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000)
285#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000)
286#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000)
287#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000)
288#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000)
289#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000)
290#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00)
291#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000)
292#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400)
293#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800)
294#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00)
295#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300)
296#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000)
297#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100)
298#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300)
299#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0)
300#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000)
301#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040)
302#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0)
303#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030)
304#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000)
305#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010)
306#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020)
307#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030)
308#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C)
309#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000)
310#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004)
311#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008)
312#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C)
313#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003)
314#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000)
315#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001)
316#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003)
317/* Step one for killing the applications system 16bit (-/W) */
318#define U300_SYSCON_KA1R (0x0080)
319#define U300_SYSCON_KA1R_MASK (0xFFFF)
320#define U300_SYSCON_KA1R_VALUE (0xFFFF)
321/* Step two for killing the application system 16bit (-/W) */
322#define U300_SYSCON_KA2R (0x0084)
323#define U300_SYSCON_KA2R_MASK (0xFFFF)
324#define U300_SYSCON_KA2R_VALUE (0xFFFF)
325/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
326#define U300_SYSCON_MMF0R (0x90)
327#define U300_SYSCON_MMF0R_MASK (0x00FF)
328#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
329#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
330/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
331#define U300_SYSCON_MMF1R (0x94)
332#define U300_SYSCON_MMF1R_MASK (0x00FF)
333#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
334#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
335/* AAIF control register 16 bit (R/W) */
336#define U300_SYSCON_AAIFCR (0x98)
337#define U300_SYSCON_AAIFCR_MASK (0x0003)
338#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
339#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
340#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
341#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
342#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
343/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
344#define U300_SYSCON_MMCR (0x9C)
345#define U300_SYSCON_MMCR_MASK (0x0003)
346#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
347#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
348
349/* TODO: More SYSCON registers missing */
350#define U300_SYSCON_PMC3R (0x10c)
351#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000)
352#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000)
353#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000)
354#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000)
355/* TODO: Missing other configs, I just added the SPI stuff */
356
357/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
358#define U300_SYSCON_S0CCR (0x120)
359#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
360#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
361#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
362#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
363#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
364#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
365#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
366#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
367#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
368#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
369#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
370#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
371#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
372#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
373#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
374/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
375#define U300_SYSCON_S1CCR (0x124)
376#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
377#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
378#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
379#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
380#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
381#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
382#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
383#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
384#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
385#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
386#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
387#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
388#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
389#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
390#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
391/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
392#define U300_SYSCON_S2CCR (0x128)
393#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
394#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
395#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
396#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
397#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
398#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
399#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
400#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
401#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
402#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
403#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
404#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
405#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
406#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
407#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
408#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
409/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
410#define U300_SYSCON_MCR (0x12c)
411#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
412#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
413#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
414#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
415#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
416#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
417#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
418#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
419#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
420#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
421#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
422#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
423#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
424#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
425#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
426#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
427#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
428/* Clock activity observability register 0 */
429#define U300_SYSCON_C0OAR (0x140)
430#define U300_SYSCON_C0OAR_MASK (0xFFFF)
431#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
432#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
433#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
434#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
435#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
436#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
437#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
438#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
439#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
440#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
441#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
442#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
443#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
444#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
445#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
446#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
447#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
448/* Clock activity observability register 1 */
449#define U300_SYSCON_C1OAR (0x144)
450#define U300_SYSCON_C1OAR_MASK (0x3FFE)
451#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
452#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
453#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
454#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
455#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
456#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
457#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
458#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
459#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
460#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
461#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
462#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
463#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
464#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
465/* Clock activity observability register 2 */
466#define U300_SYSCON_C2OAR (0x148)
467#define U300_SYSCON_C2OAR_MASK (0x0FFF)
468#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
469#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
470#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
471#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
472#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
473#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
474#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
475#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
476#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
477#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
478#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
479#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
480#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
481
482/* Chip ID register 16bit (R/-) */
483#define U300_SYSCON_CIDR (0x400)
484/* Video IRQ clear 16bit (R/W) */
485#define U300_SYSCON_VICR (0x404)
486#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
487#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
488/* SMCR */
489#define U300_SYSCON_SMCR (0x4d0)
490#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
491#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
492#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
493#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
494/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
495#define U300_SYSCON_CSDR (0x4f0)
496#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
497/* PRINT_CONTROL Print Control 16bit (R/-) */
498#define U300_SYSCON_PCR (0x4f8)
499#define U300_SYSCON_PCR_SERV_IND (0x0001)
500/* BOOT_CONTROL 16bit (R/-) */
501#define U300_SYSCON_BCR (0x4fc)
502#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
503#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
504#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
505#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
506
507
508/* CPU clock defines */
509/**
510 * CPU high frequency in MHz
511 */
512#define SYSCON_CPU_CLOCK_HIGH 208
513/**
514 * CPU medium frequency in MHz
515 */
516#define SYSCON_CPU_CLOCK_MEDIUM 104
517/**
518 * CPU low frequency in MHz
519 */
520#define SYSCON_CPU_CLOCK_LOW 13
521
522/* EMIF clock defines */
523/**
524 * EMIF high frequency in MHz
525 */
526#define SYSCON_EMIF_CLOCK_HIGH 104
527/**
528 * EMIF medium frequency in MHz
529 */
530#define SYSCON_EMIF_CLOCK_MEDIUM 104
531/**
532 * EMIF low frequency in MHz
533 */
534#define SYSCON_EMIF_CLOCK_LOW 13
535
536/* AHB clock defines */
537/**
538 * AHB high frequency in MHz
539 */
540#define SYSCON_AHB_CLOCK_HIGH 52
541/**
542 * AHB medium frequency in MHz
543 */
544#define SYSCON_AHB_CLOCK_MEDIUM 52
545/**
546 * AHB low frequency in MHz
547 */
548#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
549
550enum syscon_busmaster {
551 SYSCON_BM_DMAC,
552 SYSCON_BM_XGAM,
553 SYSCON_BM_VIDEO_ENC
554};
555
556/*
557 * Note that this array must match the order of the array "clk_reg"
558 * in syscon.c
559 */
560enum syscon_clk {
561 SYSCON_CLKCONTROL_SLOW_BRIDGE,
562 SYSCON_CLKCONTROL_UART,
563 SYSCON_CLKCONTROL_BTR,
564 SYSCON_CLKCONTROL_EH,
565 SYSCON_CLKCONTROL_GPIO,
566 SYSCON_CLKCONTROL_KEYPAD,
567 SYSCON_CLKCONTROL_APP_TIMER,
568 SYSCON_CLKCONTROL_ACC_TIMER,
569 SYSCON_CLKCONTROL_FAST_BRIDGE,
570 SYSCON_CLKCONTROL_I2C0,
571 SYSCON_CLKCONTROL_I2C1,
572 SYSCON_CLKCONTROL_I2S0,
573 SYSCON_CLKCONTROL_I2S1,
574 SYSCON_CLKCONTROL_MMC,
575 SYSCON_CLKCONTROL_SPI,
576 SYSCON_CLKCONTROL_I2S0_CORE,
577 SYSCON_CLKCONTROL_I2S1_CORE,
578 SYSCON_CLKCONTROL_AAIF,
579 SYSCON_CLKCONTROL_AHB,
580 SYSCON_CLKCONTROL_APEX,
581 SYSCON_CLKCONTROL_CPU,
582 SYSCON_CLKCONTROL_DMA,
583 SYSCON_CLKCONTROL_EMIF,
584 SYSCON_CLKCONTROL_NAND_IF,
585 SYSCON_CLKCONTROL_VIDEO_ENC,
586 SYSCON_CLKCONTROL_XGAM,
587 SYSCON_CLKCONTROL_SEMI,
588 SYSCON_CLKCONTROL_AHB_SUBSYS,
589 SYSCON_CLKCONTROL_MSPRO
590};
591
592enum syscon_sysclk_mode {
593 SYSCON_SYSCLK_DISABLED,
594 SYSCON_SYSCLK_M_CLK,
595 SYSCON_SYSCLK_ACC_FSM,
596 SYSCON_SYSCLK_PLL60_48,
597 SYSCON_SYSCLK_PLL60_60,
598 SYSCON_SYSCLK_ACC_PLL208,
599 SYSCON_SYSCLK_APP_PLL13,
600 SYSCON_SYSCLK_APP_FSM,
601 SYSCON_SYSCLK_RTC,
602 SYSCON_SYSCLK_APP_PLL208
603};
604
605enum syscon_sysclk_req {
606 SYSCON_SYSCLKREQ_DISABLED,
607 SYSCON_SYSCLKREQ_ACTIVE_LOW
608};
609
610enum syscon_clk_mode {
611 SYSCON_CLKMODE_OFF,
612 SYSCON_CLKMODE_DEFAULT,
613 SYSCON_CLKMODE_LOW,
614 SYSCON_CLKMODE_MEDIUM,
615 SYSCON_CLKMODE_HIGH,
616 SYSCON_CLKMODE_PERMANENT,
617 SYSCON_CLKMODE_ON,
618};
619
620enum syscon_call_mode {
621 SYSCON_CLKCALL_NOWAIT,
622 SYSCON_CLKCALL_WAIT,
623};
624
625int syscon_dc_on(bool keep_power_on);
626int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
627 bool active);
628bool syscon_get_busmaster_active_state(void);
629int syscon_set_sleep_mask(enum syscon_clk,
630 bool sleep_ctrl);
631int syscon_config_sysclk(u32 sysclk,
632 enum syscon_sysclk_mode sysclkmode,
633 bool inverse,
634 u32 divisor,
635 enum syscon_sysclk_req sysclkreq);
636bool syscon_can_turn_off_semi_clock(void);
637
638/* This function is restricted to core.c */
639int syscon_request_normal_power(bool req);
640
641/* This function is restricted to be used by platform_speed.c */
642int syscon_speed_request(enum syscon_call_mode wait_mode,
643 enum syscon_clk_mode req_clk_mode);
644#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
new file mode 100644
index 000000000000..8daf13634ce0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/system.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/system.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * System shutdown and reset functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/io.h>
13#include <asm/hardware/vic.h>
14#include <asm/irq.h>
15
16/* Forward declare this function from the watchdog */
17void coh901327_watchdog_reset(void);
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24static void arch_reset(char mode, const char *cmd)
25{
26 switch (mode) {
27 case 's':
28 case 'h':
29 printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
30 /* Disable interrupts */
31 local_irq_disable();
32#ifdef CONFIG_COH901327_WATCHDOG
33 coh901327_watchdog_reset();
34#endif
35 break;
36 default:
37 /* Do nothing */
38 break;
39 }
40 /* Wait for system do die/reset. */
41 while (1);
42}
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
new file mode 100644
index 000000000000..f233b72633f6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/timex.h
@@ -0,0 +1,17 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/timex.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform tick rate definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#ifndef __MACH_TIMEX_H
12#define __MACH_TIMEX_H
13
14/* This is for the APP OS GP1 (General Purpose 1) timer */
15#define CLOCK_TICK_RATE 1000000
16
17#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
new file mode 100644
index 000000000000..88333dfb19fc
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -0,0 +1,187 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/u300-regs.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Basic register address definitions in physical memory and
9 * some block defintions for core devices like the timer.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_REGS_H
14#define __MACH_U300_REGS_H
15
16/*
17 * These are the large blocks of memory allocated for I/O.
18 * the defines are used for setting up the I/O memory mapping.
19 */
20
21/* NAND Flash CS0 */
22#define U300_NAND_CS0_PHYS_BASE 0x80000000
23#define U300_NAND_CS0_VIRT_BASE 0xff040000
24
25/* NFIF */
26#define U300_NAND_IF_PHYS_BASE 0x9f800000
27#define U300_NAND_IF_VIRT_BASE 0xff030000
28
29/* AHB Peripherals */
30#define U300_AHB_PER_PHYS_BASE 0xa0000000
31#define U300_AHB_PER_VIRT_BASE 0xff010000
32
33/* FAST Peripherals */
34#define U300_FAST_PER_PHYS_BASE 0xc0000000
35#define U300_FAST_PER_VIRT_BASE 0xff020000
36
37/* SLOW Peripherals */
38#define U300_SLOW_PER_PHYS_BASE 0xc0010000
39#define U300_SLOW_PER_VIRT_BASE 0xff000000
40
41/* Boot ROM */
42#define U300_BOOTROM_PHYS_BASE 0xffff0000
43#define U300_BOOTROM_VIRT_BASE 0xffff0000
44
45/* SEMI config base */
46#ifdef CONFIG_MACH_U300_BS335
47#define U300_SEMI_CONFIG_BASE 0x2FFE0000
48#else
49#define U300_SEMI_CONFIG_BASE 0x30000000
50#endif
51
52/*
53 * All the following peripherals are specified at their PHYSICAL address,
54 * so if you need to access them (in the kernel), you MUST use the macros
55 * defined in <asm/io.h> to map to the IO_ADDRESS_AHB() IO_ADDRESS_FAST()
56 * etc.
57 */
58
59/*
60 * AHB peripherals
61 */
62
63/* AHB Peripherals Bridge Controller */
64#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
65
66/* Vectored Interrupt Controller 0, servicing 32 interrupts */
67#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
68#define U300_INTCON0_VBASE (U300_AHB_PER_VIRT_BASE+0x1000)
69
70/* Vectored Interrupt Controller 1, servicing 32 interrupts */
71#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
72#define U300_INTCON1_VBASE (U300_AHB_PER_VIRT_BASE+0x2000)
73
74/* Memory Stick Pro (MSPRO) controller */
75#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
76
77/* EMIF Configuration Area */
78#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
79
80
81/*
82 * FAST peripherals
83 */
84
85/* FAST bridge control */
86#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
87
88/* MMC/SD controller */
89#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
90
91/* PCM I2S0 controller */
92#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
93
94/* PCM I2S1 controller */
95#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
96
97/* I2C0 controller */
98#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
99
100/* I2C1 controller */
101#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
102
103/* SPI controller */
104#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
105
106#ifdef CONFIG_MACH_U300_BS335
107/* Fast UART1 on U335 only */
108#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
109#endif
110
111/*
112 * SLOW peripherals
113 */
114
115/* SLOW bridge control */
116#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
117
118/* SYSCON */
119#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
120#define U300_SYSCON_VBASE (U300_SLOW_PER_VIRT_BASE+0x1000)
121
122/* Watchdog */
123#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
124
125/* UART0 */
126#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
127
128/* APP side special timer */
129#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
130#define U300_TIMER_APP_VBASE (U300_SLOW_PER_VIRT_BASE+0x4000)
131
132/* Keypad */
133#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
134
135/* GPIO */
136#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
137
138/* RTC */
139#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
140
141/* Bus tracer */
142#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
143
144/* Event handler (hardware queue) */
145#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
146
147/* Genric Timer */
148#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
149
150/* PPM */
151#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
152
153
154/*
155 * REST peripherals
156 */
157
158/* ISP (image signal processor) is only available in U335 */
159#ifdef CONFIG_MACH_U300_BS335
160#define U300_ISP_BASE (0xA0008000)
161#endif
162
163/* DMA Controller base */
164#define U300_DMAC_BASE (0xC0020000)
165
166/* MSL Base */
167#define U300_MSL_BASE (0xc0022000)
168
169/* APEX Base */
170#define U300_APEX_BASE (0xc0030000)
171
172/* Video Encoder Base */
173#ifdef CONFIG_MACH_U300_BS335
174#define U300_VIDEOENC_BASE (0xc0080000)
175#else
176#define U300_VIDEOENC_BASE (0xc0040000)
177#endif
178
179/* XGAM Base */
180#define U300_XGAM_BASE (0xd0000000)
181
182/*
183 * Virtual accessor macros for static devices
184 */
185
186
187#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
new file mode 100644
index 000000000000..29acb718acf7
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/uncompress.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-u300/include/mach/uncompress.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
21#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
22#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
23#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
24
25/*
26 * This does not append a newline
27 */
28static inline void putc(int c)
29{
30 while (AMBA_UART_FR & (1 << 5))
31 barrier();
32
33 AMBA_UART_DR = c;
34}
35
36static inline void flush(void)
37{
38 while (AMBA_UART_FR & (1 << 3))
39 barrier();
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
46#define arch_decomp_wdog()
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b00c51a66fbe
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/vmalloc.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Virtual memory allocations
9 * End must be above the I/O registers and on an even 2MiB boundary.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12#define VMALLOC_END 0xfe800000
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
new file mode 100644
index 000000000000..3138d3955c9e
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.c
@@ -0,0 +1,216 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Johan Lundin <johan.lundin@stericsson.com>
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */
13#include <linux/device.h>
14#include <linux/amba/bus.h>
15#include <linux/mmc/host.h>
16#include <linux/input.h>
17#include <linux/workqueue.h>
18#include <linux/delay.h>
19#include <linux/regulator/consumer.h>
20#include <linux/regulator/machine.h>
21#include <linux/gpio.h>
22
23#include <asm/mach/mmc.h>
24#include "mmc.h"
25
26struct mmci_card_event {
27 struct input_dev *mmc_input;
28 int mmc_inserted;
29 struct work_struct workq;
30 struct mmc_platform_data mmc0_plat_data;
31};
32
33static unsigned int mmc_status(struct device *dev)
34{
35 struct mmci_card_event *mmci_card = container_of(
36 dev->platform_data,
37 struct mmci_card_event, mmc0_plat_data);
38
39 return mmci_card->mmc_inserted;
40}
41
42/*
43 * Here follows a large chunk of code which will only be enabled if you
44 * have both the AB3100 chip mounted and the MMC subsystem activated.
45 */
46
47static u32 mmc_translate_vdd(struct device *dev, unsigned int voltage)
48{
49 int v;
50
51 /*
52 * MMC Spec:
53 * bit 7: 1.70 - 1.95V
54 * bit 8 - 14: 2.0 - 2.6V
55 * bit 15 - 23: 2.7 - 3.6V
56 *
57 * ab3100 voltages:
58 * 000 - 2.85V
59 * 001 - 2.75V
60 * 010 - 1.8V
61 * 011 - 1.5V
62 */
63 switch (voltage) {
64 case 8:
65 v = 3;
66 break;
67 case 9:
68 case 10:
69 case 11:
70 case 12:
71 case 13:
72 case 14:
73 case 15:
74 v = 1;
75 break;
76 case 16:
77 v = 1;
78 break;
79 case 17:
80 case 18:
81 case 19:
82 case 20:
83 case 21:
84 case 22:
85 case 23:
86 case 24:
87 v = 0;
88 break;
89 default:
90 v = 0;
91 break;
92 }
93
94 /* PL180 voltage register bits */
95 return v << 2;
96}
97
98
99
100static int mmci_callback(void *data)
101{
102 struct mmci_card_event *mmci_card = data;
103
104 disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
105 schedule_work(&mmci_card->workq);
106
107 return 0;
108}
109
110
111static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
112 char *buf)
113{
114 struct mmci_card_event *mmci_card = container_of(
115 dev->platform_data,
116 struct mmci_card_event, mmc0_plat_data);
117
118
119 return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
120}
121
122static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
123
124static void _mmci_callback(struct work_struct *ws)
125{
126
127 struct mmci_card_event *mmci_card = container_of(
128 ws,
129 struct mmci_card_event, workq);
130
131 mdelay(20);
132
133 mmci_card->mmc_inserted = !!gpio_get_value(U300_GPIO_PIN_MMC_CD);
134
135 input_report_switch(mmci_card->mmc_input, KEY_INSERT,
136 !mmci_card->mmc_inserted);
137 input_sync(mmci_card->mmc_input);
138
139 pr_debug("MMC/SD card was %s\n",
140 mmci_card->mmc_inserted ? "removed" : "inserted");
141
142 enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, !mmci_card->mmc_inserted);
143}
144
145int __devinit mmc_init(struct amba_device *adev)
146{
147 struct mmci_card_event *mmci_card;
148 struct device *mmcsd_device = &adev->dev;
149 int ret = 0;
150
151 mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL);
152 if (!mmci_card)
153 return -ENOMEM;
154
155 /* Nominally 2.85V on our platform */
156 mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
157 mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
158 mmci_card->mmc0_plat_data.status = mmc_status;
159
160 mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
161
162 INIT_WORK(&mmci_card->workq, _mmci_callback);
163
164 ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
165 if (ret) {
166 printk(KERN_CRIT "Could not allocate MMC card detection " \
167 "GPIO pin\n");
168 goto out;
169 }
170
171 ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
172 if (ret) {
173 printk(KERN_CRIT "Invalid GPIO pin requested\n");
174 goto out;
175 }
176
177 ret = sysfs_create_file(&mmcsd_device->kobj,
178 &dev_attr_mmc_inserted.attr);
179 if (ret)
180 goto out;
181
182 mmci_card->mmc_input = input_allocate_device();
183 if (!mmci_card->mmc_input) {
184 printk(KERN_CRIT "Could not allocate MMC input device\n");
185 return -ENOMEM;
186 }
187
188 mmci_card->mmc_input->name = "MMC insert notification";
189 mmci_card->mmc_input->id.bustype = BUS_HOST;
190 mmci_card->mmc_input->id.vendor = 0;
191 mmci_card->mmc_input->id.product = 0;
192 mmci_card->mmc_input->id.version = 0x0100;
193 mmci_card->mmc_input->dev.parent = mmcsd_device;
194 input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
195
196 /*
197 * Since this must always be compiled into the kernel, this input
198 * is never unregistered or free:ed.
199 */
200 ret = input_register_device(mmci_card->mmc_input);
201 if (ret) {
202 input_free_device(mmci_card->mmc_input);
203 goto out;
204 }
205
206 input_set_drvdata(mmci_card->mmc_input, mmci_card);
207
208 ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
209 mmci_card);
210
211 schedule_work(&mmci_card->workq);
212
213 printk(KERN_INFO "Registered MMC insert/remove notification\n");
214out:
215 return ret;
216}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
new file mode 100644
index 000000000000..92b85125abb3
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.h
@@ -0,0 +1,18 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
10 */
11#ifndef MMC_H
12#define MMC_H
13
14#include <linux/amba/bus.h>
15
16int __devinit mmc_init(struct amba_device *adev);
17
18#endif
diff --git a/arch/arm/mach-u300/padmux.c b/arch/arm/mach-u300/padmux.c
new file mode 100644
index 000000000000..f3664564f086
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.c
@@ -0,0 +1,58 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX functions
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 */
12#include <linux/io.h>
13#include <linux/err.h>
14#include <mach/u300-regs.h>
15#include <mach/syscon.h>
16
17#include "padmux.h"
18
19/* Set the PAD MUX to route the MMC reader correctly to GPIO0. */
20void pmx_set_mission_mode_mmc(void)
21{
22 u16 val;
23
24 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
25 val &= ~U300_SYSCON_PMC1LR_MMCSD_MASK;
26 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1LR);
27 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
28 val &= ~U300_SYSCON_PMC1HR_APP_GPIO_1_MASK;
29 val |= U300_SYSCON_PMC1HR_APP_GPIO_1_MMC;
30 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
31}
32
33void pmx_set_mission_mode_spi(void)
34{
35 u16 val;
36
37 /* Set up padmuxing so the SPI port and its chipselects are active */
38 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
39 /*
40 * Activate the SPI port (disable the use of these pins for generic
41 * GPIO, DSP, AAIF
42 */
43 val &= ~U300_SYSCON_PMC1HR_APP_SPI_2_MASK;
44 val |= U300_SYSCON_PMC1HR_APP_SPI_2_SPI;
45 /*
46 * Use GPIO pin SPI CS1 for CS1 actually (it can be used for other
47 * things also)
48 */
49 val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK;
50 val |= U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI;
51 /*
52 * Use GPIO pin SPI CS2 for CS2 actually (it can be used for other
53 * things also)
54 */
55 val &= ~U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK;
56 val |= U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI;
57 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMC1HR);
58}
diff --git a/arch/arm/mach-u300/padmux.h b/arch/arm/mach-u300/padmux.h
new file mode 100644
index 000000000000..8c2099ac5046
--- /dev/null
+++ b/arch/arm/mach-u300/padmux.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * arch/arm/mach-u300/padmux.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * U300 PADMUX API
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 */
12
13#ifndef __MACH_U300_PADMUX_H
14#define __MACH_U300_PADMUX_H
15
16void pmx_set_mission_mode_mmc(void);
17void pmx_set_mission_mode_spi(void);
18
19#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
new file mode 100644
index 000000000000..cce53204880e
--- /dev/null
+++ b/arch/arm/mach-u300/timer.c
@@ -0,0 +1,422 @@
1/*
2 *
3 * arch/arm/mach-u300/timer.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Timer COH 901 328, runs the OS timer interrupt.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/timex.h>
14#include <linux/clockchips.h>
15#include <linux/clocksource.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20
21/* Generic stuff */
22#include <asm/mach/map.h>
23#include <asm/mach/time.h>
24#include <asm/mach/irq.h>
25
26#include "clock.h"
27
28/*
29 * APP side special timer registers
30 * This timer contains four timers which can fire an interrupt each.
31 * OS (operating system) timer @ 32768 Hz
32 * DD (device driver) timer @ 1 kHz
33 * GP1 (general purpose 1) timer @ 1MHz
34 * GP2 (general purpose 2) timer @ 1MHz
35 */
36
37/* Reset OS Timer 32bit (-/W) */
38#define U300_TIMER_APP_ROST (0x0000)
39#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
40/* Enable OS Timer 32bit (-/W) */
41#define U300_TIMER_APP_EOST (0x0004)
42#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
43/* Disable OS Timer 32bit (-/W) */
44#define U300_TIMER_APP_DOST (0x0008)
45#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
46/* OS Timer Mode Register 32bit (-/W) */
47#define U300_TIMER_APP_SOSTM (0x000c)
48#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
49#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
50/* OS Timer Status Register 32bit (R/-) */
51#define U300_TIMER_APP_OSTS (0x0010)
52#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
53#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
54#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
55#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
56#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
57#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
58#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
59#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
60#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
61/* OS Timer Current Count Register 32bit (R/-) */
62#define U300_TIMER_APP_OSTCC (0x0014)
63/* OS Timer Terminal Count Register 32bit (R/W) */
64#define U300_TIMER_APP_OSTTC (0x0018)
65/* OS Timer Interrupt Enable Register 32bit (-/W) */
66#define U300_TIMER_APP_OSTIE (0x001c)
67#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
68#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
69/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
70#define U300_TIMER_APP_OSTIA (0x0020)
71#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
72
73/* Reset DD Timer 32bit (-/W) */
74#define U300_TIMER_APP_RDDT (0x0040)
75#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
76/* Enable DD Timer 32bit (-/W) */
77#define U300_TIMER_APP_EDDT (0x0044)
78#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
79/* Disable DD Timer 32bit (-/W) */
80#define U300_TIMER_APP_DDDT (0x0048)
81#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
82/* DD Timer Mode Register 32bit (-/W) */
83#define U300_TIMER_APP_SDDTM (0x004c)
84#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
85#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
86/* DD Timer Status Register 32bit (R/-) */
87#define U300_TIMER_APP_DDTS (0x0050)
88#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
89#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
90#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
91#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
92#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
93#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
94#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
95#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
96#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
97/* DD Timer Current Count Register 32bit (R/-) */
98#define U300_TIMER_APP_DDTCC (0x0054)
99/* DD Timer Terminal Count Register 32bit (R/W) */
100#define U300_TIMER_APP_DDTTC (0x0058)
101/* DD Timer Interrupt Enable Register 32bit (-/W) */
102#define U300_TIMER_APP_DDTIE (0x005c)
103#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
104#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
105/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
106#define U300_TIMER_APP_DDTIA (0x0060)
107#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
108
109/* Reset GP1 Timer 32bit (-/W) */
110#define U300_TIMER_APP_RGPT1 (0x0080)
111#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
112/* Enable GP1 Timer 32bit (-/W) */
113#define U300_TIMER_APP_EGPT1 (0x0084)
114#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
115/* Disable GP1 Timer 32bit (-/W) */
116#define U300_TIMER_APP_DGPT1 (0x0088)
117#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
118/* GP1 Timer Mode Register 32bit (-/W) */
119#define U300_TIMER_APP_SGPT1M (0x008c)
120#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
121#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
122/* GP1 Timer Status Register 32bit (R/-) */
123#define U300_TIMER_APP_GPT1S (0x0090)
124#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
125#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
126#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
127#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
128#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
129#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
130#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
131#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
132#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
133/* GP1 Timer Current Count Register 32bit (R/-) */
134#define U300_TIMER_APP_GPT1CC (0x0094)
135/* GP1 Timer Terminal Count Register 32bit (R/W) */
136#define U300_TIMER_APP_GPT1TC (0x0098)
137/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
138#define U300_TIMER_APP_GPT1IE (0x009c)
139#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
140#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
141/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
142#define U300_TIMER_APP_GPT1IA (0x00a0)
143#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
144
145/* Reset GP2 Timer 32bit (-/W) */
146#define U300_TIMER_APP_RGPT2 (0x00c0)
147#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
148/* Enable GP2 Timer 32bit (-/W) */
149#define U300_TIMER_APP_EGPT2 (0x00c4)
150#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
151/* Disable GP2 Timer 32bit (-/W) */
152#define U300_TIMER_APP_DGPT2 (0x00c8)
153#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
154/* GP2 Timer Mode Register 32bit (-/W) */
155#define U300_TIMER_APP_SGPT2M (0x00cc)
156#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
157#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
158/* GP2 Timer Status Register 32bit (R/-) */
159#define U300_TIMER_APP_GPT2S (0x00d0)
160#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
161#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
162#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
163#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
164#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
165#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
166#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
167#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
168#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
169/* GP2 Timer Current Count Register 32bit (R/-) */
170#define U300_TIMER_APP_GPT2CC (0x00d4)
171/* GP2 Timer Terminal Count Register 32bit (R/W) */
172#define U300_TIMER_APP_GPT2TC (0x00d8)
173/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
174#define U300_TIMER_APP_GPT2IE (0x00dc)
175#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
176#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
177/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
178#define U300_TIMER_APP_GPT2IA (0x00e0)
179#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
180
181/* Clock request control register - all four timers */
182#define U300_TIMER_APP_CRC (0x100)
183#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
184
185#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
186#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
187
188/*
189 * The u300_set_mode() function is always called first, if we
190 * have oneshot timer active, the oneshot scheduling function
191 * u300_set_next_event() is called immediately after.
192 */
193static void u300_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt)
195{
196 switch (mode) {
197 case CLOCK_EVT_MODE_PERIODIC:
198 /* Disable interrupts on GPT1 */
199 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
200 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
201 /* Disable GP1 while we're reprogramming it. */
202 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
203 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
204 /*
205 * Set the periodic mode to a certain number of ticks per
206 * jiffy.
207 */
208 writel(TICKS_PER_JIFFY,
209 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
210 /*
211 * Set continuous mode, so the timer keeps triggering
212 * interrupts.
213 */
214 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
215 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
216 /* Enable timer interrupts */
217 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
218 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
219 /* Then enable the OS timer again */
220 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
221 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
222 break;
223 case CLOCK_EVT_MODE_ONESHOT:
224 /* Just break; here? */
225 /*
226 * The actual event will be programmed by the next event hook,
227 * so we just set a dummy value somewhere at the end of the
228 * universe here.
229 */
230 /* Disable interrupts on GPT1 */
231 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
232 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
233 /* Disable GP1 while we're reprogramming it. */
234 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
235 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
236 /*
237 * Expire far in the future, u300_set_next_event() will be
238 * called soon...
239 */
240 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
241 /* We run one shot per tick here! */
242 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
243 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
244 /* Enable interrupts for this timer */
245 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
246 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
247 /* Enable timer */
248 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
249 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
250 break;
251 case CLOCK_EVT_MODE_UNUSED:
252 case CLOCK_EVT_MODE_SHUTDOWN:
253 /* Disable interrupts on GP1 */
254 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
255 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
256 /* Disable GP1 */
257 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
258 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
259 break;
260 case CLOCK_EVT_MODE_RESUME:
261 /* Ignore this call */
262 break;
263 }
264}
265
266/*
267 * The app timer in one shot mode obviously has to be reprogrammed
268 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
269 * the interrupt disable + timer disable commands with a reset command,
270 * it will fail miserably. Apparently (and I found this the hard way)
271 * the timer is very sensitive to the instruction order, though you don't
272 * get that impression from the data sheet.
273 */
274static int u300_set_next_event(unsigned long cycles,
275 struct clock_event_device *evt)
276
277{
278 /* Disable interrupts on GPT1 */
279 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
280 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
281 /* Disable GP1 while we're reprogramming it. */
282 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
283 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
284 /* Reset the General Purpose timer 1. */
285 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
286 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
287 /* IRQ in n * cycles */
288 writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
289 /*
290 * We run one shot per tick here! (This is necessary to reconfigure,
291 * the timer will tilt if you don't!)
292 */
293 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
294 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
295 /* Enable timer interrupts */
296 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
297 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
298 /* Then enable the OS timer again */
299 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
300 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
301 return 0;
302}
303
304
305/* Use general purpose timer 1 as clock event */
306static struct clock_event_device clockevent_u300_1mhz = {
307 .name = "GPT1",
308 .rating = 300, /* Reasonably fast and accurate clock event */
309 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
310 /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
311 .shift = 22,
312 .set_next_event = u300_set_next_event,
313 .set_mode = u300_set_mode,
314};
315
316/* Clock event timer interrupt handler */
317static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
318{
319 struct clock_event_device *evt = &clockevent_u300_1mhz;
320 /* ACK/Clear timer IRQ for the APP GPT1 Timer */
321 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
322 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
323 evt->event_handler(evt);
324 return IRQ_HANDLED;
325}
326
327static struct irqaction u300_timer_irq = {
328 .name = "U300 Timer Tick",
329 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
330 .handler = u300_timer_interrupt,
331};
332
333/* Use general purpose timer 2 as clock source */
334static cycle_t u300_get_cycles(struct clocksource *cs)
335{
336 return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
337}
338
339static struct clocksource clocksource_u300_1mhz = {
340 .name = "GPT2",
341 .rating = 300, /* Reasonably fast and accurate clock source */
342 .read = u300_get_cycles,
343 .mask = CLOCKSOURCE_MASK(32), /* 32 bits */
344 /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
345 .shift = 22,
346 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
347};
348
349
350/*
351 * This sets up the system timers, clock source and clock event.
352 */
353static void __init u300_timer_init(void)
354{
355 u300_enable_timer_clock();
356 /*
357 * Disable the "OS" and "DD" timers - these are designed for Symbian!
358 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
359 */
360 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
361 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
362 writel(U300_TIMER_APP_ROST_TIMER_RESET,
363 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
364 writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
365 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
366 writel(U300_TIMER_APP_RDDT_TIMER_RESET,
367 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
368 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
369 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
370
371 /* Reset the General Purpose timer 1. */
372 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
373 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
374
375 /* Set up the IRQ handler */
376 setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
377
378 /* Reset the General Purpose timer 2 */
379 writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
380 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
381 /* Set this timer to run around forever */
382 writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
383 /* Set continuous mode so it wraps around */
384 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
385 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
386 /* Disable timer interrupts */
387 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
388 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
389 /* Then enable the GP2 timer to use as a free running us counter */
390 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
391 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
392
393 /* This is a pure microsecond clock source */
394 clocksource_u300_1mhz.mult =
395 clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
396 if (clocksource_register(&clocksource_u300_1mhz))
397 printk(KERN_ERR "timer: failed to initialize clock "
398 "source %s\n", clocksource_u300_1mhz.name);
399
400 clockevent_u300_1mhz.mult =
401 div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
402 /* 32bit counter, so 32bits delta is max */
403 clockevent_u300_1mhz.max_delta_ns =
404 clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
405 /* This timer is slow enough to set for 1 cycle == 1 MHz */
406 clockevent_u300_1mhz.min_delta_ns =
407 clockevent_delta2ns(1, &clockevent_u300_1mhz);
408 clockevent_u300_1mhz.cpumask = cpumask_of(0);
409 clockevents_register_device(&clockevent_u300_1mhz);
410 /*
411 * TODO: init and register the rest of the timers too, they can be
412 * used by hrtimers!
413 */
414}
415
416/*
417 * Very simple system timer that only register the clock event and
418 * clock source.
419 */
420struct sys_timer u300_timer = {
421 .init = u300_timer_init,
422};
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
new file mode 100644
index 000000000000..d2a0b8847a18
--- /dev/null
+++ b/arch/arm/mach-u300/u300.c
@@ -0,0 +1,55 @@
1/*
2 *
3 * arch/arm/mach-u300/u300.c
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform machine definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <mach/hardware.h>
20#include <mach/platform.h>
21#include <mach/memory.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24
25static void __init u300_init_machine(void)
26{
27 u300_init_devices();
28}
29
30#ifdef CONFIG_MACH_U300_BS2X
31#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
32#endif
33
34#ifdef CONFIG_MACH_U300_BS330
35#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
36#endif
37
38#ifdef CONFIG_MACH_U300_BS335
39#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
40#endif
41
42#ifdef CONFIG_MACH_U300_BS365
43#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
44#endif
45
46MACHINE_START(U300, MACH_U300_STRING)
47 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
48 .phys_io = U300_AHB_PER_PHYS_BASE,
49 .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
50 .boot_params = BOOT_PARAMS_OFFSET,
51 .map_io = u300_map_io,
52 .init_irq = u300_init_irq,
53 .timer = &u300_timer,
54 .init_machine = u300_init_machine,
55MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 23:50:01 -0500