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-rw-r--r--arch/arm/mach-u300/include/mach/gpio.h1
-rw-r--r--arch/arm/mach-u300/include/mach/syscon.h136
2 files changed, 1 insertions, 136 deletions
diff --git a/arch/arm/mach-u300/include/mach/gpio.h b/arch/arm/mach-u300/include/mach/gpio.h
index e69de29bb2d1..40a8c178f10d 100644
--- a/arch/arm/mach-u300/include/mach/gpio.h
+++ b/arch/arm/mach-u300/include/mach/gpio.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 7444f5c7da97..6e84f07a7c6f 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -234,91 +234,6 @@
234#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) 234#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
235#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) 235#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
236#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) 236#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
237/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
238#define U300_SYSCON_PMC1LR (0x007C)
239#define U300_SYSCON_PMC1LR_MASK (0xFFFF)
240#define U300_SYSCON_PMC1LR_CDI_MASK (0xC000)
241#define U300_SYSCON_PMC1LR_CDI_CDI (0x0000)
242#define U300_SYSCON_PMC1LR_CDI_EMIF (0x4000)
243#ifdef CONFIG_MACH_U300_BS335
244#define U300_SYSCON_PMC1LR_CDI_CDI2 (0x8000)
245#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO (0xC000)
246#elif CONFIG_MACH_U300_BS365
247#define U300_SYSCON_PMC1LR_CDI_GPIO (0x8000)
248#define U300_SYSCON_PMC1LR_CDI_WCDMA (0xC000)
249#endif
250#define U300_SYSCON_PMC1LR_PDI_MASK (0x3000)
251#define U300_SYSCON_PMC1LR_PDI_PDI (0x0000)
252#define U300_SYSCON_PMC1LR_PDI_EGG (0x1000)
253#define U300_SYSCON_PMC1LR_PDI_WCDMA (0x3000)
254#define U300_SYSCON_PMC1LR_MMCSD_MASK (0x0C00)
255#define U300_SYSCON_PMC1LR_MMCSD_MMCSD (0x0000)
256#define U300_SYSCON_PMC1LR_MMCSD_MSPRO (0x0400)
257#define U300_SYSCON_PMC1LR_MMCSD_DSP (0x0800)
258#define U300_SYSCON_PMC1LR_MMCSD_WCDMA (0x0C00)
259#define U300_SYSCON_PMC1LR_ETM_MASK (0x0300)
260#define U300_SYSCON_PMC1LR_ETM_ACC (0x0000)
261#define U300_SYSCON_PMC1LR_ETM_APP (0x0100)
262#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK (0x00C0)
263#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC (0x0000)
264#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF (0x0040)
265#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM (0x0080)
266#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB (0x00C0)
267#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK (0x0030)
268#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC (0x0000)
269#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF (0x0010)
270#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM (0x0020)
271#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI (0x0030)
272#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK (0x000C)
273#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC (0x0000)
274#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF (0x0004)
275#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM (0x0008)
276#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI (0x000C)
277#define U300_SYSCON_PMC1LR_EMIF_1_MASK (0x0003)
278#define U300_SYSCON_PMC1LR_EMIF_1_STATIC (0x0000)
279#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 (0x0001)
280#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 (0x0002)
281#define U300_SYSCON_PMC1LR_EMIF_1 (0x0003)
282/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
283#define U300_SYSCON_PMC1HR (0x007E)
284#define U300_SYSCON_PMC1HR_MASK (0xFFFF)
285#define U300_SYSCON_PMC1HR_MISC_2_MASK (0xC000)
286#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO (0x0000)
287#define U300_SYSCON_PMC1HR_MISC_2_MSPRO (0x4000)
288#define U300_SYSCON_PMC1HR_MISC_2_DSP (0x8000)
289#define U300_SYSCON_PMC1HR_MISC_2_AAIF (0xC000)
290#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK (0x3000)
291#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO (0x0000)
292#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF (0x1000)
293#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP (0x2000)
294#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF (0x3000)
295#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK (0x0C00)
296#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO (0x0000)
297#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC (0x0400)
298#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP (0x0800)
299#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF (0x0C00)
300#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK (0x0300)
301#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO (0x0000)
302#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI (0x0100)
303#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF (0x0300)
304#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK (0x00C0)
305#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO (0x0000)
306#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI (0x0040)
307#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF (0x00C0)
308#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK (0x0030)
309#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO (0x0000)
310#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI (0x0010)
311#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP (0x0020)
312#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF (0x0030)
313#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK (0x000C)
314#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO (0x0000)
315#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 (0x0004)
316#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS (0x0008)
317#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF (0x000C)
318#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK (0x0003)
319#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO (0x0000)
320#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 (0x0001)
321#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF (0x0003)
322/* Step one for killing the applications system 16bit (-/W) */ 237/* Step one for killing the applications system 16bit (-/W) */
323#define U300_SYSCON_KA1R (0x0080) 238#define U300_SYSCON_KA1R (0x0080)
324#define U300_SYSCON_KA1R_MASK (0xFFFF) 239#define U300_SYSCON_KA1R_MASK (0xFFFF)
@@ -357,57 +272,6 @@
357#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) 272#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
358#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) 273#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
359#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) 274#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
360/* Padmux 2 control */
361#define U300_SYSCON_PMC2R (0x100)
362#define U300_SYSCON_PMC2R_APP_MISC_0_MASK (0x00C0)
363#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO (0x0000)
364#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM (0x0040)
365#define U300_SYSCON_PMC2R_APP_MISC_0_MMC (0x0080)
366#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 (0x00C0)
367#define U300_SYSCON_PMC2R_APP_MISC_1_MASK (0x0300)
368#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO (0x0000)
369#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM (0x0100)
370#define U300_SYSCON_PMC2R_APP_MISC_1_MMC (0x0200)
371#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 (0x0300)
372#define U300_SYSCON_PMC2R_APP_MISC_2_MASK (0x0C00)
373#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO (0x0000)
374#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM (0x0400)
375#define U300_SYSCON_PMC2R_APP_MISC_2_MMC (0x0800)
376#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 (0x0C00)
377#define U300_SYSCON_PMC2R_APP_MISC_3_MASK (0x3000)
378#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO (0x0000)
379#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM (0x1000)
380#define U300_SYSCON_PMC2R_APP_MISC_3_MMC (0x2000)
381#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 (0x3000)
382#define U300_SYSCON_PMC2R_APP_MISC_4_MASK (0xC000)
383#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO (0x0000)
384#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM (0x4000)
385#define U300_SYSCON_PMC2R_APP_MISC_4_MMC (0x8000)
386#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO (0xC000)
387/* TODO: More SYSCON registers missing */
388#define U300_SYSCON_PMC3R (0x10c)
389#define U300_SYSCON_PMC3R_APP_MISC_11_MASK (0xc000)
390#define U300_SYSCON_PMC3R_APP_MISC_11_SPI (0x4000)
391#define U300_SYSCON_PMC3R_APP_MISC_10_MASK (0x3000)
392#define U300_SYSCON_PMC3R_APP_MISC_10_SPI (0x1000)
393/* TODO: Missing other configs */
394#define U300_SYSCON_PMC4R (0x168)
395#define U300_SYSCON_PMC4R_APP_MISC_12_MASK (0x0003)
396#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO (0x0000)
397#define U300_SYSCON_PMC4R_APP_MISC_13_MASK (0x000C)
398#define U300_SYSCON_PMC4R_APP_MISC_13_CDI (0x0000)
399#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA (0x0004)
400#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 (0x0008)
401#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO (0x000C)
402#define U300_SYSCON_PMC4R_APP_MISC_14_MASK (0x0030)
403#define U300_SYSCON_PMC4R_APP_MISC_14_CDI (0x0000)
404#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA (0x0010)
405#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 (0x0020)
406#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO (0x0030)
407#define U300_SYSCON_PMC4R_APP_MISC_16_MASK (0x0300)
408#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 (0x0000)
409#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS (0x0100)
410#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N (0x0200)
411/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ 275/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
412#define U300_SYSCON_S0CCR (0x120) 276#define U300_SYSCON_S0CCR (0x120)
413#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) 277#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 23:33:09 -0500