diff options
Diffstat (limited to 'arch/arm/mach-u300/clock.c')
-rw-r--r-- | arch/arm/mach-u300/clock.c | 139 |
1 files changed, 57 insertions, 82 deletions
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c index 5d12d547789e..60acf9e708ae 100644 --- a/arch/arm/mach-u300/clock.c +++ b/arch/arm/mach-u300/clock.c | |||
@@ -947,6 +947,10 @@ static struct clk fast_clk = { | |||
947 | .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock), | 947 | .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock), |
948 | }; | 948 | }; |
949 | 949 | ||
950 | /* | ||
951 | * The MMCI apb_pclk is hardwired to the same terminal as the | ||
952 | * external MCI clock. Thus this will be referenced twice. | ||
953 | */ | ||
950 | static struct clk mmcsd_clk = { | 954 | static struct clk mmcsd_clk = { |
951 | .name = "MCLK", | 955 | .name = "MCLK", |
952 | .parent = &fast_clk, | 956 | .parent = &fast_clk, |
@@ -1024,6 +1028,10 @@ static struct clk i2c1_clk = { | |||
1024 | .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock), | 1028 | .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock), |
1025 | }; | 1029 | }; |
1026 | 1030 | ||
1031 | /* | ||
1032 | * The SPI apb_pclk is hardwired to the same terminal as the | ||
1033 | * external SPI clock. Thus this will be referenced twice. | ||
1034 | */ | ||
1027 | static struct clk spi_clk = { | 1035 | static struct clk spi_clk = { |
1028 | .name = "SPI", | 1036 | .name = "SPI", |
1029 | .parent = &fast_clk, | 1037 | .parent = &fast_clk, |
@@ -1040,10 +1048,9 @@ static struct clk spi_clk = { | |||
1040 | }; | 1048 | }; |
1041 | 1049 | ||
1042 | #ifdef CONFIG_MACH_U300_BS335 | 1050 | #ifdef CONFIG_MACH_U300_BS335 |
1043 | static struct clk uart1_clk = { | 1051 | static struct clk uart1_pclk = { |
1044 | .name = "UART1", | 1052 | .name = "UART1_PCLK", |
1045 | .parent = &fast_clk, | 1053 | .parent = &fast_clk, |
1046 | .rate = 13000000, | ||
1047 | .hw_ctrld = false, | 1054 | .hw_ctrld = false, |
1048 | .reset = true, | 1055 | .reset = true, |
1049 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, | 1056 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR, |
@@ -1051,6 +1058,14 @@ static struct clk uart1_clk = { | |||
1051 | .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, | 1058 | .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN, |
1052 | .enable = syscon_clk_enable, | 1059 | .enable = syscon_clk_enable, |
1053 | .disable = syscon_clk_disable, | 1060 | .disable = syscon_clk_disable, |
1061 | .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock), | ||
1062 | }; | ||
1063 | |||
1064 | /* This one is hardwired to PLL13 */ | ||
1065 | static struct clk uart1_clk = { | ||
1066 | .name = "UART1_CLK", | ||
1067 | .rate = 13000000, | ||
1068 | .hw_ctrld = true, | ||
1054 | .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock), | 1069 | .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock), |
1055 | }; | 1070 | }; |
1056 | #endif | 1071 | #endif |
@@ -1085,11 +1100,9 @@ static struct clk wdog_clk = { | |||
1085 | .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock), | 1100 | .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock), |
1086 | }; | 1101 | }; |
1087 | 1102 | ||
1088 | /* This one is hardwired to PLL13 */ | 1103 | static struct clk uart0_pclk = { |
1089 | static struct clk uart_clk = { | 1104 | .name = "UART0_PCLK", |
1090 | .name = "UARTCLK", | ||
1091 | .parent = &slow_clk, | 1105 | .parent = &slow_clk, |
1092 | .rate = 13000000, | ||
1093 | .hw_ctrld = false, | 1106 | .hw_ctrld = false, |
1094 | .reset = true, | 1107 | .reset = true, |
1095 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, | 1108 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
@@ -1097,7 +1110,16 @@ static struct clk uart_clk = { | |||
1097 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, | 1110 | .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, |
1098 | .enable = syscon_clk_enable, | 1111 | .enable = syscon_clk_enable, |
1099 | .disable = syscon_clk_disable, | 1112 | .disable = syscon_clk_disable, |
1100 | .lock = __SPIN_LOCK_UNLOCKED(uart_clk.lock), | 1113 | .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock), |
1114 | }; | ||
1115 | |||
1116 | /* This one is hardwired to PLL13 */ | ||
1117 | static struct clk uart0_clk = { | ||
1118 | .name = "UART0_CLK", | ||
1119 | .parent = &slow_clk, | ||
1120 | .rate = 13000000, | ||
1121 | .hw_ctrld = true, | ||
1122 | .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock), | ||
1101 | }; | 1123 | }; |
1102 | 1124 | ||
1103 | static struct clk keypad_clk = { | 1125 | static struct clk keypad_clk = { |
@@ -1182,10 +1204,14 @@ static struct clk timer_clk = { | |||
1182 | .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), | 1204 | .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock), |
1183 | }; | 1205 | }; |
1184 | 1206 | ||
1207 | /* | ||
1208 | * There is a binary divider in the hardware that divides | ||
1209 | * the 13MHz PLL by 13 down to 1 MHz. | ||
1210 | */ | ||
1185 | static struct clk app_timer_clk = { | 1211 | static struct clk app_timer_clk = { |
1186 | .name = "TIMER_APP", | 1212 | .name = "TIMER_APP", |
1187 | .parent = &slow_clk, | 1213 | .parent = &slow_clk, |
1188 | .rate = 13000000, | 1214 | .rate = 1000000, |
1189 | .hw_ctrld = true, | 1215 | .hw_ctrld = true, |
1190 | .reset = true, | 1216 | .reset = true, |
1191 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, | 1217 | .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR, |
@@ -1212,23 +1238,24 @@ static struct clk ppm_clk = { | |||
1212 | }; | 1238 | }; |
1213 | #endif | 1239 | #endif |
1214 | 1240 | ||
1215 | static struct clk dummy_apb_pclk; | ||
1216 | |||
1217 | #define DEF_LOOKUP(devid, clkref) \ | 1241 | #define DEF_LOOKUP(devid, clkref) \ |
1218 | { \ | 1242 | { \ |
1219 | .dev_id = devid, \ | 1243 | .dev_id = devid, \ |
1220 | .clk = clkref, \ | 1244 | .clk = clkref, \ |
1221 | } | 1245 | } |
1222 | 1246 | ||
1247 | #define DEF_LOOKUP_CON(devid, conid, clkref) \ | ||
1248 | { \ | ||
1249 | .dev_id = devid, \ | ||
1250 | .con_id = conid, \ | ||
1251 | .clk = clkref, \ | ||
1252 | } | ||
1253 | |||
1223 | /* | 1254 | /* |
1224 | * Here we only define clocks that are meaningful to | 1255 | * Here we only define clocks that are meaningful to |
1225 | * look up through clockdevice. | 1256 | * look up through clockdevice. |
1226 | */ | 1257 | */ |
1227 | static struct clk_lookup lookups[] = { | 1258 | static struct clk_lookup lookups[] = { |
1228 | { | ||
1229 | .con_id = "apb_pclk", | ||
1230 | .clk = &dummy_apb_pclk, | ||
1231 | }, | ||
1232 | /* Connected directly to the AMBA bus */ | 1259 | /* Connected directly to the AMBA bus */ |
1233 | DEF_LOOKUP("amba", &amba_clk), | 1260 | DEF_LOOKUP("amba", &amba_clk), |
1234 | DEF_LOOKUP("cpu", &cpu_clk), | 1261 | DEF_LOOKUP("cpu", &cpu_clk), |
@@ -1247,11 +1274,14 @@ static struct clk_lookup lookups[] = { | |||
1247 | /* AHB bridge clocks */ | 1274 | /* AHB bridge clocks */ |
1248 | DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk), | 1275 | DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk), |
1249 | DEF_LOOKUP("intcon", &intcon_clk), | 1276 | DEF_LOOKUP("intcon", &intcon_clk), |
1277 | DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk), | ||
1250 | DEF_LOOKUP("mspro", &mspro_clk), | 1278 | DEF_LOOKUP("mspro", &mspro_clk), |
1251 | DEF_LOOKUP("pl172", &emif_clk), | 1279 | DEF_LOOKUP("pl172", &emif_clk), |
1280 | DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk), | ||
1252 | /* FAST bridge clocks */ | 1281 | /* FAST bridge clocks */ |
1253 | DEF_LOOKUP("fast", &fast_clk), | 1282 | DEF_LOOKUP("fast", &fast_clk), |
1254 | DEF_LOOKUP("mmci", &mmcsd_clk), | 1283 | DEF_LOOKUP("mmci", &mmcsd_clk), |
1284 | DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk), | ||
1255 | /* | 1285 | /* |
1256 | * The .0 and .1 identifiers on these comes from the platform device | 1286 | * The .0 and .1 identifiers on these comes from the platform device |
1257 | * .id field and are assigned when the platform devices are registered. | 1287 | * .id field and are assigned when the platform devices are registered. |
@@ -1261,13 +1291,16 @@ static struct clk_lookup lookups[] = { | |||
1261 | DEF_LOOKUP("stu300.0", &i2c0_clk), | 1291 | DEF_LOOKUP("stu300.0", &i2c0_clk), |
1262 | DEF_LOOKUP("stu300.1", &i2c1_clk), | 1292 | DEF_LOOKUP("stu300.1", &i2c1_clk), |
1263 | DEF_LOOKUP("pl022", &spi_clk), | 1293 | DEF_LOOKUP("pl022", &spi_clk), |
1294 | DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk), | ||
1264 | #ifdef CONFIG_MACH_U300_BS335 | 1295 | #ifdef CONFIG_MACH_U300_BS335 |
1265 | DEF_LOOKUP("uart1", &uart1_clk), | 1296 | DEF_LOOKUP("uart1", &uart1_clk), |
1297 | DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk), | ||
1266 | #endif | 1298 | #endif |
1267 | /* SLOW bridge clocks */ | 1299 | /* SLOW bridge clocks */ |
1268 | DEF_LOOKUP("slow", &slow_clk), | 1300 | DEF_LOOKUP("slow", &slow_clk), |
1269 | DEF_LOOKUP("coh901327_wdog", &wdog_clk), | 1301 | DEF_LOOKUP("coh901327_wdog", &wdog_clk), |
1270 | DEF_LOOKUP("uart0", &uart_clk), | 1302 | DEF_LOOKUP("uart0", &uart0_clk), |
1303 | DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk), | ||
1271 | DEF_LOOKUP("apptimer", &app_timer_clk), | 1304 | DEF_LOOKUP("apptimer", &app_timer_clk), |
1272 | DEF_LOOKUP("coh901461-keypad", &keypad_clk), | 1305 | DEF_LOOKUP("coh901461-keypad", &keypad_clk), |
1273 | DEF_LOOKUP("u300-gpio", &gpio_clk), | 1306 | DEF_LOOKUP("u300-gpio", &gpio_clk), |
@@ -1286,64 +1319,6 @@ static void __init clk_register(void) | |||
1286 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | 1319 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
1287 | } | 1320 | } |
1288 | 1321 | ||
1289 | /* | ||
1290 | * These are the clocks for cells registered as primecell drivers | ||
1291 | * on the AMBA bus. These must be on during AMBA device registration | ||
1292 | * since the bus probe will attempt to read magic configuration | ||
1293 | * registers for these devices. If they are deactivated these probes | ||
1294 | * will fail. | ||
1295 | * | ||
1296 | * | ||
1297 | * Please note that on emif, both RAM and NAND is connected in dual | ||
1298 | * RAM phones. On single RAM phones, ram is on semi and NAND on emif. | ||
1299 | * | ||
1300 | */ | ||
1301 | void u300_clock_primecells(void) | ||
1302 | { | ||
1303 | clk_enable(&intcon_clk); | ||
1304 | clk_enable(&uart_clk); | ||
1305 | #ifdef CONFIG_MACH_U300_BS335 | ||
1306 | clk_enable(&uart1_clk); | ||
1307 | #endif | ||
1308 | clk_enable(&spi_clk); | ||
1309 | |||
1310 | clk_enable(&mmcsd_clk); | ||
1311 | |||
1312 | } | ||
1313 | EXPORT_SYMBOL(u300_clock_primecells); | ||
1314 | |||
1315 | void u300_unclock_primecells(void) | ||
1316 | { | ||
1317 | |||
1318 | clk_disable(&intcon_clk); | ||
1319 | clk_disable(&uart_clk); | ||
1320 | #ifdef CONFIG_MACH_U300_BS335 | ||
1321 | clk_disable(&uart1_clk); | ||
1322 | #endif | ||
1323 | clk_disable(&spi_clk); | ||
1324 | clk_disable(&mmcsd_clk); | ||
1325 | |||
1326 | } | ||
1327 | EXPORT_SYMBOL(u300_unclock_primecells); | ||
1328 | |||
1329 | /* | ||
1330 | * The interrupt controller is enabled before the clock API is registered. | ||
1331 | */ | ||
1332 | void u300_enable_intcon_clock(void) | ||
1333 | { | ||
1334 | clk_enable(&intcon_clk); | ||
1335 | } | ||
1336 | EXPORT_SYMBOL(u300_enable_intcon_clock); | ||
1337 | |||
1338 | /* | ||
1339 | * The timer is enabled before the clock API is registered. | ||
1340 | */ | ||
1341 | void u300_enable_timer_clock(void) | ||
1342 | { | ||
1343 | clk_enable(&app_timer_clk); | ||
1344 | } | ||
1345 | EXPORT_SYMBOL(u300_enable_timer_clock); | ||
1346 | |||
1347 | #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) | 1322 | #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG)) |
1348 | /* | 1323 | /* |
1349 | * The following makes it possible to view the status (especially | 1324 | * The following makes it possible to view the status (especially |
@@ -1385,11 +1360,13 @@ static struct clk *clks[] = { | |||
1385 | &spi_clk, | 1360 | &spi_clk, |
1386 | #ifdef CONFIG_MACH_U300_BS335 | 1361 | #ifdef CONFIG_MACH_U300_BS335 |
1387 | &uart1_clk, | 1362 | &uart1_clk, |
1363 | &uart1_pclk, | ||
1388 | #endif | 1364 | #endif |
1389 | /* SLOW bridge clocks */ | 1365 | /* SLOW bridge clocks */ |
1390 | &slow_clk, | 1366 | &slow_clk, |
1391 | &wdog_clk, | 1367 | &wdog_clk, |
1392 | &uart_clk, | 1368 | &uart0_clk, |
1369 | &uart0_pclk, | ||
1393 | &app_timer_clk, | 1370 | &app_timer_clk, |
1394 | &keypad_clk, | 1371 | &keypad_clk, |
1395 | &gpio_clk, | 1372 | &gpio_clk, |
@@ -1430,7 +1407,7 @@ static int u300_clocks_show(struct seq_file *s, void *data) | |||
1430 | chars++; | 1407 | chars++; |
1431 | } | 1408 | } |
1432 | cdp[32] = '\0'; | 1409 | cdp[32] = '\0'; |
1433 | if (clk->get_rate) | 1410 | if (clk->get_rate || clk->rate != 0) |
1434 | seq_printf(s, | 1411 | seq_printf(s, |
1435 | "%s%s\t%s\t%d\t%s\t%lu Hz\n", | 1412 | "%s%s\t%s\t%d\t%s\t%lu Hz\n", |
1436 | &cdp[0], | 1413 | &cdp[0], |
@@ -1439,7 +1416,7 @@ static int u300_clocks_show(struct seq_file *s, void *data) | |||
1439 | clk->usecount ? "ON" : "OFF", | 1416 | clk->usecount ? "ON" : "OFF", |
1440 | clk->usecount, | 1417 | clk->usecount, |
1441 | clk->hw_ctrld ? "YES" : "NO ", | 1418 | clk->hw_ctrld ? "YES" : "NO ", |
1442 | clk->get_rate(clk)); | 1419 | clk_get_rate(clk)); |
1443 | else | 1420 | else |
1444 | seq_printf(s, | 1421 | seq_printf(s, |
1445 | "%s%s\t%s\t%d\t%s\t" \ | 1422 | "%s%s\t%s\t%d\t%s\t" \ |
@@ -1483,7 +1460,7 @@ static int __init init_clk_read_debugfs(void) | |||
1483 | module_init(init_clk_read_debugfs); | 1460 | module_init(init_clk_read_debugfs); |
1484 | #endif | 1461 | #endif |
1485 | 1462 | ||
1486 | static int __init u300_clock_init(void) | 1463 | int __init u300_clock_init(void) |
1487 | { | 1464 | { |
1488 | u16 val; | 1465 | u16 val; |
1489 | 1466 | ||
@@ -1520,10 +1497,8 @@ static int __init u300_clock_init(void) | |||
1520 | */ | 1497 | */ |
1521 | syscon_block_reset_disable(&semi_clk); | 1498 | syscon_block_reset_disable(&semi_clk); |
1522 | syscon_block_reset_disable(&emif_clk); | 1499 | syscon_block_reset_disable(&emif_clk); |
1523 | semi_clk.enable(&semi_clk); | 1500 | clk_enable(&semi_clk); |
1524 | emif_clk.enable(&emif_clk); | 1501 | clk_enable(&emif_clk); |
1525 | 1502 | ||
1526 | return 0; | 1503 | return 0; |
1527 | } | 1504 | } |
1528 | /* initialize clocking early to be available later in the boot */ | ||
1529 | core_initcall(u300_clock_init); | ||