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-rw-r--r--arch/arm/mach-tegra/Kconfig14
-rw-r--r--arch/arm/mach-tegra/Makefile6
-rw-r--r--arch/arm/mach-tegra/apbio.c2
-rw-r--r--arch/arm/mach-tegra/board-paz00.c5
-rw-r--r--arch/arm/mach-tegra/board-paz00.h25
-rw-r--r--arch/arm/mach-tegra/board.h12
-rw-r--r--arch/arm/mach-tegra/common.c115
-rw-r--r--arch/arm/mach-tegra/cpuidle.c4
-rw-r--r--arch/arm/mach-tegra/flowctrl.c2
-rw-r--r--arch/arm/mach-tegra/fuse.c56
-rw-r--r--arch/arm/mach-tegra/fuse.h1
-rw-r--r--arch/arm/mach-tegra/gpio-names.h247
-rw-r--r--arch/arm/mach-tegra/hotplug.c2
-rw-r--r--arch/arm/mach-tegra/iomap.h155
-rw-r--r--arch/arm/mach-tegra/irammap.h6
-rw-r--r--arch/arm/mach-tegra/platsmp.c2
-rw-r--r--arch/arm/mach-tegra/pm.c20
-rw-r--r--arch/arm/mach-tegra/pm.h3
-rw-r--r--arch/arm/mach-tegra/pmc.c58
-rw-r--r--arch/arm/mach-tegra/pmc.h5
-rw-r--r--arch/arm/mach-tegra/powergate.c48
-rw-r--r--arch/arm/mach-tegra/reset-handler.S13
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/sleep-tegra20.S5
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S54
-rw-r--r--arch/arm/mach-tegra/tegra.c73
26 files changed, 306 insertions, 629 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 67a76f2dfb9f..09e740f58b27 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -3,7 +3,6 @@ config ARCH_TEGRA
3 select ARCH_HAS_CPUFREQ 3 select ARCH_HAS_CPUFREQ
4 select ARCH_REQUIRE_GPIOLIB 4 select ARCH_REQUIRE_GPIOLIB
5 select ARM_GIC 5 select ARM_GIC
6 select CLKDEV_LOOKUP
7 select CLKSRC_MMIO 6 select CLKSRC_MMIO
8 select CLKSRC_OF 7 select CLKSRC_OF
9 select COMMON_CLK 8 select COMMON_CLK
@@ -11,7 +10,6 @@ config ARCH_TEGRA
11 select GENERIC_CLOCKEVENTS 10 select GENERIC_CLOCKEVENTS
12 select HAVE_ARM_SCU if SMP 11 select HAVE_ARM_SCU if SMP
13 select HAVE_ARM_TWD if SMP 12 select HAVE_ARM_TWD if SMP
14 select HAVE_CLK
15 select HAVE_SMP 13 select HAVE_SMP
16 select MIGHT_HAVE_CACHE_L2X0 14 select MIGHT_HAVE_CACHE_L2X0
17 select MIGHT_HAVE_PCI 15 select MIGHT_HAVE_PCI
@@ -53,14 +51,22 @@ config ARCH_TEGRA_3x_SOC
53 51
54config ARCH_TEGRA_114_SOC 52config ARCH_TEGRA_114_SOC
55 bool "Enable support for Tegra114 family" 53 bool "Enable support for Tegra114 family"
56 select HAVE_ARM_ARCH_TIMER 54 select ARM_ERRATA_798181 if SMP
57 select ARM_ERRATA_798181
58 select ARM_L1_CACHE_SHIFT_6 55 select ARM_L1_CACHE_SHIFT_6
56 select HAVE_ARM_ARCH_TIMER
59 select PINCTRL_TEGRA114 57 select PINCTRL_TEGRA114
60 help 58 help
61 Support for NVIDIA Tegra T114 processor family, based on the 59 Support for NVIDIA Tegra T114 processor family, based on the
62 ARM CortexA15MP CPU 60 ARM CortexA15MP CPU
63 61
62config ARCH_TEGRA_124_SOC
63 bool "Enable support for Tegra124 family"
64 select ARM_L1_CACHE_SHIFT_6
65 select HAVE_ARM_ARCH_TIMER
66 help
67 Support for NVIDIA Tegra T124 processor family, based on the
68 ARM CortexA15MP CPU
69
64config TEGRA_AHB 70config TEGRA_AHB
65 bool "Enable AHB driver for NVIDIA Tegra SoCs" 71 bool "Enable AHB driver for NVIDIA Tegra SoCs"
66 default y 72 default y
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e7e5f45c6558..019bb1758662 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,5 @@
1asflags-y += -march=armv7-a 1asflags-y += -march=armv7-a
2 2
3obj-y += common.o
4obj-y += io.o 3obj-y += io.o
5obj-y += irq.o 4obj-y += irq.o
6obj-y += fuse.o 5obj-y += fuse.o
@@ -36,5 +35,10 @@ obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
36ifeq ($(CONFIG_CPU_IDLE),y) 35ifeq ($(CONFIG_CPU_IDLE),y)
37obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o 36obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
38endif 37endif
38obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
39obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
40ifeq ($(CONFIG_CPU_IDLE),y)
41obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
42endif
39 43
40obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o 44obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index d7aa52ea6cfc..bc471973cf04 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -114,7 +114,7 @@ static int do_dma_transfer(unsigned long apb_add,
114 dma_desc->callback = apb_dma_complete; 114 dma_desc->callback = apb_dma_complete;
115 dma_desc->callback_param = NULL; 115 dma_desc->callback_param = NULL;
116 116
117 INIT_COMPLETION(tegra_apb_wait); 117 reinit_completion(&tegra_apb_wait);
118 118
119 dmaengine_submit(dma_desc); 119 dmaengine_submit(dma_desc);
120 dma_async_issue_pending(tegra_apb_dma_chan); 120 dma_async_issue_pending(tegra_apb_dma_chan);
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 740e16f64728..06f024070dab 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -20,12 +20,11 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/rfkill-gpio.h> 21#include <linux/rfkill-gpio.h>
22#include "board.h" 22#include "board.h"
23#include "board-paz00.h"
24 23
25static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { 24static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
26 .name = "wifi_rfkill", 25 .name = "wifi_rfkill",
27 .reset_gpio = TEGRA_WIFI_RST, 26 .reset_gpio = 25, /* PD1 */
28 .shutdown_gpio = TEGRA_WIFI_PWRN, 27 .shutdown_gpio = 85, /* PK5 */
29 .type = RFKILL_TYPE_WLAN, 28 .type = RFKILL_TYPE_WLAN,
30}; 29};
31 30
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
deleted file mode 100644
index 25c08ecef52f..000000000000
--- a/arch/arm/mach-tegra/board-paz00.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * arch/arm/mach-tegra/board-paz00.h
3 *
4 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef _MACH_TEGRA_BOARD_PAZ00_H
18#define _MACH_TEGRA_BOARD_PAZ00_H
19
20#include "gpio-names.h"
21
22#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
23#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
24
25#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index db6810dc0b3d..bcf5dbf69d58 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,20 +25,8 @@
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/reboot.h> 26#include <linux/reboot.h>
27 27
28void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd);
29
30void __init tegra_init_early(void);
31void __init tegra_map_common_io(void); 28void __init tegra_map_common_io(void);
32void __init tegra_init_irq(void); 29void __init tegra_init_irq(void);
33void __init tegra_dt_init_irq(void);
34
35void tegra_init_late(void);
36
37#ifdef CONFIG_DEBUG_FS
38int tegra_clk_debugfs_init(void);
39#else
40static inline int tegra_clk_debugfs_init(void) { return 0; }
41#endif
42 30
43int __init tegra_powergate_init(void); 31int __init tegra_powergate_init(void);
44#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) 32#if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
deleted file mode 100644
index 94a119a35af8..000000000000
--- a/arch/arm/mach-tegra/common.c
+++ /dev/null
@@ -1,115 +0,0 @@
1/*
2 * arch/arm/mach-tegra/common.c
3 *
4 * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5 * Copyright (C) 2010 Google, Inc.
6 *
7 * Author:
8 * Colin Cross <ccross@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/reboot.h>
26#include <linux/irqchip.h>
27#include <linux/clk-provider.h>
28
29#include <asm/hardware/cache-l2x0.h>
30
31#include "board.h"
32#include "common.h"
33#include "cpuidle.h"
34#include "fuse.h"
35#include "iomap.h"
36#include "irq.h"
37#include "pmc.h"
38#include "apbio.h"
39#include "sleep.h"
40#include "pm.h"
41#include "reset.h"
42
43/*
44 * Storage for debug-macro.S's state.
45 *
46 * This must be in .data not .bss so that it gets initialized each time the
47 * kernel is loaded. The data is declared here rather than debug-macro.S so
48 * that multiple inclusions of debug-macro.S point at the same data.
49 */
50u32 tegra_uart_config[4] = {
51 /* Debug UART initialization required */
52 1,
53 /* Debug UART physical address */
54 0,
55 /* Debug UART virtual address */
56 0,
57 /* Scratch space for debug macro */
58 0,
59};
60
61#ifdef CONFIG_OF
62void __init tegra_dt_init_irq(void)
63{
64 of_clk_init(NULL);
65 tegra_pmc_init();
66 tegra_init_irq();
67 irqchip_init();
68 tegra_legacy_irq_syscore_init();
69}
70#endif
71
72void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
73{
74 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
75 u32 reg;
76
77 reg = readl_relaxed(reset);
78 reg |= 0x10;
79 writel_relaxed(reg, reset);
80}
81
82static void __init tegra_init_cache(void)
83{
84#ifdef CONFIG_CACHE_L2X0
85 int ret;
86 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
87 u32 aux_ctrl, cache_type;
88
89 cache_type = readl(p + L2X0_CACHE_TYPE);
90 aux_ctrl = (cache_type & 0x700) << (17-8);
91 aux_ctrl |= 0x7C400001;
92
93 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
94 if (!ret)
95 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
96#endif
97
98}
99
100void __init tegra_init_early(void)
101{
102 tegra_cpu_reset_handler_init();
103 tegra_apb_io_init();
104 tegra_init_fuse();
105 tegra_init_cache();
106 tegra_powergate_init();
107 tegra_hotplug_init();
108}
109
110void __init tegra_init_late(void)
111{
112 tegra_init_suspend();
113 tegra_cpuidle_init();
114 tegra_powergate_debugfs_init();
115}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 0961dfcf83a4..7bc5d8d667fe 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -39,7 +39,9 @@ void __init tegra_cpuidle_init(void)
39 tegra30_cpuidle_init(); 39 tegra30_cpuidle_init();
40 break; 40 break;
41 case TEGRA114: 41 case TEGRA114:
42 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) 42 case TEGRA124:
43 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
44 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
43 tegra114_cpuidle_init(); 45 tegra114_cpuidle_init();
44 break; 46 break;
45 } 47 }
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index 5348543382bf..ce8ab8abf061 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -87,6 +87,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
87 break; 87 break;
88 case TEGRA30: 88 case TEGRA30:
89 case TEGRA114: 89 case TEGRA114:
90 case TEGRA124:
90 /* clear wfe bitmap */ 91 /* clear wfe bitmap */
91 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; 92 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
92 /* clear wfi bitmap */ 93 /* clear wfi bitmap */
@@ -125,6 +126,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
125 break; 126 break;
126 case TEGRA30: 127 case TEGRA30:
127 case TEGRA114: 128 case TEGRA114:
129 case TEGRA124:
128 /* clear wfe bitmap */ 130 /* clear wfe bitmap */
129 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; 131 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
130 /* clear wfi bitmap */ 132 /* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index e035cd284a6e..d4639c506622 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -21,14 +21,26 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/export.h> 23#include <linux/export.h>
24#include <linux/random.h>
24#include <linux/tegra-soc.h> 25#include <linux/tegra-soc.h>
25 26
26#include "fuse.h" 27#include "fuse.h"
27#include "iomap.h" 28#include "iomap.h"
28#include "apbio.h" 29#include "apbio.h"
29 30
31/* Tegra20 only */
30#define FUSE_UID_LOW 0x108 32#define FUSE_UID_LOW 0x108
31#define FUSE_UID_HIGH 0x10c 33#define FUSE_UID_HIGH 0x10c
34
35/* Tegra30 and later */
36#define FUSE_VENDOR_CODE 0x200
37#define FUSE_FAB_CODE 0x204
38#define FUSE_LOT_CODE_0 0x208
39#define FUSE_LOT_CODE_1 0x20c
40#define FUSE_WAFER_ID 0x210
41#define FUSE_X_COORDINATE 0x214
42#define FUSE_Y_COORDINATE 0x218
43
32#define FUSE_SKU_INFO 0x110 44#define FUSE_SKU_INFO 0x110
33 45
34#define TEGRA20_FUSE_SPARE_BIT 0x200 46#define TEGRA20_FUSE_SPARE_BIT 0x200
@@ -112,21 +124,51 @@ u32 tegra_read_chipid(void)
112 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); 124 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113} 125}
114 126
115void tegra_init_fuse(void) 127static void __init tegra20_fuse_init_randomness(void)
128{
129 u32 randomness[2];
130
131 randomness[0] = tegra_fuse_readl(FUSE_UID_LOW);
132 randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH);
133
134 add_device_randomness(randomness, sizeof(randomness));
135}
136
137/* Applies to Tegra30 or later */
138static void __init tegra30_fuse_init_randomness(void)
139{
140 u32 randomness[7];
141
142 randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE);
143 randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE);
144 randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0);
145 randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1);
146 randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID);
147 randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE);
148 randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE);
149
150 add_device_randomness(randomness, sizeof(randomness));
151}
152
153void __init tegra_init_fuse(void)
116{ 154{
117 u32 id; 155 u32 id;
156 u32 randomness[5];
118 157
119 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); 158 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
120 reg |= 1 << 28; 159 reg |= 1 << 28;
121 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); 160 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
122 161
123 reg = tegra_fuse_readl(FUSE_SKU_INFO); 162 reg = tegra_fuse_readl(FUSE_SKU_INFO);
163 randomness[0] = reg;
124 tegra_sku_id = reg & 0xFF; 164 tegra_sku_id = reg & 0xFF;
125 165
126 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); 166 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
167 randomness[1] = reg;
127 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; 168 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
128 169
129 id = tegra_read_chipid(); 170 id = tegra_read_chipid();
171 randomness[2] = id;
130 tegra_chip_id = (id >> 8) & 0xff; 172 tegra_chip_id = (id >> 8) & 0xff;
131 173
132 switch (tegra_chip_id) { 174 switch (tegra_chip_id) {
@@ -149,6 +191,18 @@ void tegra_init_fuse(void)
149 191
150 tegra_revision = tegra_get_revision(id); 192 tegra_revision = tegra_get_revision(id);
151 tegra_init_speedo_data(); 193 tegra_init_speedo_data();
194 randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id;
195 randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id;
196
197 add_device_randomness(randomness, sizeof(randomness));
198 switch (tegra_chip_id) {
199 case TEGRA20:
200 tegra20_fuse_init_randomness();
201 case TEGRA30:
202 case TEGRA114:
203 default:
204 tegra30_fuse_init_randomness();
205 }
152 206
153 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", 207 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
154 tegra_revision_name[tegra_revision], 208 tegra_revision_name[tegra_revision],
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index def79683bef6..c01d04785d67 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -29,6 +29,7 @@
29#define TEGRA20 0x20 29#define TEGRA20 0x20
30#define TEGRA30 0x30 30#define TEGRA30 0x30
31#define TEGRA114 0x35 31#define TEGRA114 0x35
32#define TEGRA124 0x40
32 33
33#ifndef __ASSEMBLY__ 34#ifndef __ASSEMBLY__
34enum tegra_revision { 35enum tegra_revision {
diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h
deleted file mode 100644
index f28220a641b2..000000000000
--- a/arch/arm/mach-tegra/gpio-names.h
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/gpio-names.h
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __MACH_TEGRA_GPIO_NAMES_H
20#define __MACH_TEGRA_GPIO_NAMES_H
21
22#define TEGRA_GPIO_PA0 0
23#define TEGRA_GPIO_PA1 1
24#define TEGRA_GPIO_PA2 2
25#define TEGRA_GPIO_PA3 3
26#define TEGRA_GPIO_PA4 4
27#define TEGRA_GPIO_PA5 5
28#define TEGRA_GPIO_PA6 6
29#define TEGRA_GPIO_PA7 7
30#define TEGRA_GPIO_PB0 8
31#define TEGRA_GPIO_PB1 9
32#define TEGRA_GPIO_PB2 10
33#define TEGRA_GPIO_PB3 11
34#define TEGRA_GPIO_PB4 12
35#define TEGRA_GPIO_PB5 13
36#define TEGRA_GPIO_PB6 14
37#define TEGRA_GPIO_PB7 15
38#define TEGRA_GPIO_PC0 16
39#define TEGRA_GPIO_PC1 17
40#define TEGRA_GPIO_PC2 18
41#define TEGRA_GPIO_PC3 19
42#define TEGRA_GPIO_PC4 20
43#define TEGRA_GPIO_PC5 21
44#define TEGRA_GPIO_PC6 22
45#define TEGRA_GPIO_PC7 23
46#define TEGRA_GPIO_PD0 24
47#define TEGRA_GPIO_PD1 25
48#define TEGRA_GPIO_PD2 26
49#define TEGRA_GPIO_PD3 27
50#define TEGRA_GPIO_PD4 28
51#define TEGRA_GPIO_PD5 29
52#define TEGRA_GPIO_PD6 30
53#define TEGRA_GPIO_PD7 31
54#define TEGRA_GPIO_PE0 32
55#define TEGRA_GPIO_PE1 33
56#define TEGRA_GPIO_PE2 34
57#define TEGRA_GPIO_PE3 35
58#define TEGRA_GPIO_PE4 36
59#define TEGRA_GPIO_PE5 37
60#define TEGRA_GPIO_PE6 38
61#define TEGRA_GPIO_PE7 39
62#define TEGRA_GPIO_PF0 40
63#define TEGRA_GPIO_PF1 41
64#define TEGRA_GPIO_PF2 42
65#define TEGRA_GPIO_PF3 43
66#define TEGRA_GPIO_PF4 44
67#define TEGRA_GPIO_PF5 45
68#define TEGRA_GPIO_PF6 46
69#define TEGRA_GPIO_PF7 47
70#define TEGRA_GPIO_PG0 48
71#define TEGRA_GPIO_PG1 49
72#define TEGRA_GPIO_PG2 50
73#define TEGRA_GPIO_PG3 51
74#define TEGRA_GPIO_PG4 52
75#define TEGRA_GPIO_PG5 53
76#define TEGRA_GPIO_PG6 54
77#define TEGRA_GPIO_PG7 55
78#define TEGRA_GPIO_PH0 56
79#define TEGRA_GPIO_PH1 57
80#define TEGRA_GPIO_PH2 58
81#define TEGRA_GPIO_PH3 59
82#define TEGRA_GPIO_PH4 60
83#define TEGRA_GPIO_PH5 61
84#define TEGRA_GPIO_PH6 62
85#define TEGRA_GPIO_PH7 63
86#define TEGRA_GPIO_PI0 64
87#define TEGRA_GPIO_PI1 65
88#define TEGRA_GPIO_PI2 66
89#define TEGRA_GPIO_PI3 67
90#define TEGRA_GPIO_PI4 68
91#define TEGRA_GPIO_PI5 69
92#define TEGRA_GPIO_PI6 70
93#define TEGRA_GPIO_PI7 71
94#define TEGRA_GPIO_PJ0 72
95#define TEGRA_GPIO_PJ1 73
96#define TEGRA_GPIO_PJ2 74
97#define TEGRA_GPIO_PJ3 75
98#define TEGRA_GPIO_PJ4 76
99#define TEGRA_GPIO_PJ5 77
100#define TEGRA_GPIO_PJ6 78
101#define TEGRA_GPIO_PJ7 79
102#define TEGRA_GPIO_PK0 80
103#define TEGRA_GPIO_PK1 81
104#define TEGRA_GPIO_PK2 82
105#define TEGRA_GPIO_PK3 83
106#define TEGRA_GPIO_PK4 84
107#define TEGRA_GPIO_PK5 85
108#define TEGRA_GPIO_PK6 86
109#define TEGRA_GPIO_PK7 87
110#define TEGRA_GPIO_PL0 88
111#define TEGRA_GPIO_PL1 89
112#define TEGRA_GPIO_PL2 90
113#define TEGRA_GPIO_PL3 91
114#define TEGRA_GPIO_PL4 92
115#define TEGRA_GPIO_PL5 93
116#define TEGRA_GPIO_PL6 94
117#define TEGRA_GPIO_PL7 95
118#define TEGRA_GPIO_PM0 96
119#define TEGRA_GPIO_PM1 97
120#define TEGRA_GPIO_PM2 98
121#define TEGRA_GPIO_PM3 99
122#define TEGRA_GPIO_PM4 100
123#define TEGRA_GPIO_PM5 101
124#define TEGRA_GPIO_PM6 102
125#define TEGRA_GPIO_PM7 103
126#define TEGRA_GPIO_PN0 104
127#define TEGRA_GPIO_PN1 105
128#define TEGRA_GPIO_PN2 106
129#define TEGRA_GPIO_PN3 107
130#define TEGRA_GPIO_PN4 108
131#define TEGRA_GPIO_PN5 109
132#define TEGRA_GPIO_PN6 110
133#define TEGRA_GPIO_PN7 111
134#define TEGRA_GPIO_PO0 112
135#define TEGRA_GPIO_PO1 113
136#define TEGRA_GPIO_PO2 114
137#define TEGRA_GPIO_PO3 115
138#define TEGRA_GPIO_PO4 116
139#define TEGRA_GPIO_PO5 117
140#define TEGRA_GPIO_PO6 118
141#define TEGRA_GPIO_PO7 119
142#define TEGRA_GPIO_PP0 120
143#define TEGRA_GPIO_PP1 121
144#define TEGRA_GPIO_PP2 122
145#define TEGRA_GPIO_PP3 123
146#define TEGRA_GPIO_PP4 124
147#define TEGRA_GPIO_PP5 125
148#define TEGRA_GPIO_PP6 126
149#define TEGRA_GPIO_PP7 127
150#define TEGRA_GPIO_PQ0 128
151#define TEGRA_GPIO_PQ1 129
152#define TEGRA_GPIO_PQ2 130
153#define TEGRA_GPIO_PQ3 131
154#define TEGRA_GPIO_PQ4 132
155#define TEGRA_GPIO_PQ5 133
156#define TEGRA_GPIO_PQ6 134
157#define TEGRA_GPIO_PQ7 135
158#define TEGRA_GPIO_PR0 136
159#define TEGRA_GPIO_PR1 137
160#define TEGRA_GPIO_PR2 138
161#define TEGRA_GPIO_PR3 139
162#define TEGRA_GPIO_PR4 140
163#define TEGRA_GPIO_PR5 141
164#define TEGRA_GPIO_PR6 142
165#define TEGRA_GPIO_PR7 143
166#define TEGRA_GPIO_PS0 144
167#define TEGRA_GPIO_PS1 145
168#define TEGRA_GPIO_PS2 146
169#define TEGRA_GPIO_PS3 147
170#define TEGRA_GPIO_PS4 148
171#define TEGRA_GPIO_PS5 149
172#define TEGRA_GPIO_PS6 150
173#define TEGRA_GPIO_PS7 151
174#define TEGRA_GPIO_PT0 152
175#define TEGRA_GPIO_PT1 153
176#define TEGRA_GPIO_PT2 154
177#define TEGRA_GPIO_PT3 155
178#define TEGRA_GPIO_PT4 156
179#define TEGRA_GPIO_PT5 157
180#define TEGRA_GPIO_PT6 158
181#define TEGRA_GPIO_PT7 159
182#define TEGRA_GPIO_PU0 160
183#define TEGRA_GPIO_PU1 161
184#define TEGRA_GPIO_PU2 162
185#define TEGRA_GPIO_PU3 163
186#define TEGRA_GPIO_PU4 164
187#define TEGRA_GPIO_PU5 165
188#define TEGRA_GPIO_PU6 166
189#define TEGRA_GPIO_PU7 167
190#define TEGRA_GPIO_PV0 168
191#define TEGRA_GPIO_PV1 169
192#define TEGRA_GPIO_PV2 170
193#define TEGRA_GPIO_PV3 171
194#define TEGRA_GPIO_PV4 172
195#define TEGRA_GPIO_PV5 173
196#define TEGRA_GPIO_PV6 174
197#define TEGRA_GPIO_PV7 175
198#define TEGRA_GPIO_PW0 176
199#define TEGRA_GPIO_PW1 177
200#define TEGRA_GPIO_PW2 178
201#define TEGRA_GPIO_PW3 179
202#define TEGRA_GPIO_PW4 180
203#define TEGRA_GPIO_PW5 181
204#define TEGRA_GPIO_PW6 182
205#define TEGRA_GPIO_PW7 183
206#define TEGRA_GPIO_PX0 184
207#define TEGRA_GPIO_PX1 185
208#define TEGRA_GPIO_PX2 186
209#define TEGRA_GPIO_PX3 187
210#define TEGRA_GPIO_PX4 188
211#define TEGRA_GPIO_PX5 189
212#define TEGRA_GPIO_PX6 190
213#define TEGRA_GPIO_PX7 191
214#define TEGRA_GPIO_PY0 192
215#define TEGRA_GPIO_PY1 193
216#define TEGRA_GPIO_PY2 194
217#define TEGRA_GPIO_PY3 195
218#define TEGRA_GPIO_PY4 196
219#define TEGRA_GPIO_PY5 197
220#define TEGRA_GPIO_PY6 198
221#define TEGRA_GPIO_PY7 199
222#define TEGRA_GPIO_PZ0 200
223#define TEGRA_GPIO_PZ1 201
224#define TEGRA_GPIO_PZ2 202
225#define TEGRA_GPIO_PZ3 203
226#define TEGRA_GPIO_PZ4 204
227#define TEGRA_GPIO_PZ5 205
228#define TEGRA_GPIO_PZ6 206
229#define TEGRA_GPIO_PZ7 207
230#define TEGRA_GPIO_PAA0 208
231#define TEGRA_GPIO_PAA1 209
232#define TEGRA_GPIO_PAA2 210
233#define TEGRA_GPIO_PAA3 211
234#define TEGRA_GPIO_PAA4 212
235#define TEGRA_GPIO_PAA5 213
236#define TEGRA_GPIO_PAA6 214
237#define TEGRA_GPIO_PAA7 215
238#define TEGRA_GPIO_PBB0 216
239#define TEGRA_GPIO_PBB1 217
240#define TEGRA_GPIO_PBB2 218
241#define TEGRA_GPIO_PBB3 219
242#define TEGRA_GPIO_PBB4 220
243#define TEGRA_GPIO_PBB5 221
244#define TEGRA_GPIO_PBB6 222
245#define TEGRA_GPIO_PBB7 223
246
247#endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 04de2e860923..ff26af26bd0c 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -57,4 +57,6 @@ void __init tegra_hotplug_init(void)
57 tegra_hotplug_shutdown = tegra30_hotplug_shutdown; 57 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
58 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) 58 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
59 tegra_hotplug_shutdown = tegra30_hotplug_shutdown; 59 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
60 if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
61 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
60} 62}
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 3f5fa0749bde..26b1c2ad0ceb 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -24,44 +24,12 @@
24#define TEGRA_IRAM_BASE 0x40000000 24#define TEGRA_IRAM_BASE 0x40000000
25#define TEGRA_IRAM_SIZE SZ_256K 25#define TEGRA_IRAM_SIZE SZ_256K
26 26
27#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
28
29#define TEGRA_HOST1X_BASE 0x50000000
30#define TEGRA_HOST1X_SIZE 0x24000
31
32#define TEGRA_ARM_PERIF_BASE 0x50040000 27#define TEGRA_ARM_PERIF_BASE 0x50040000
33#define TEGRA_ARM_PERIF_SIZE SZ_8K 28#define TEGRA_ARM_PERIF_SIZE SZ_8K
34 29
35#define TEGRA_ARM_PL310_BASE 0x50043000
36#define TEGRA_ARM_PL310_SIZE SZ_4K
37
38#define TEGRA_ARM_INT_DIST_BASE 0x50041000 30#define TEGRA_ARM_INT_DIST_BASE 0x50041000
39#define TEGRA_ARM_INT_DIST_SIZE SZ_4K 31#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
40 32
41#define TEGRA_MPE_BASE 0x54040000
42#define TEGRA_MPE_SIZE SZ_256K
43
44#define TEGRA_VI_BASE 0x54080000
45#define TEGRA_VI_SIZE SZ_256K
46
47#define TEGRA_ISP_BASE 0x54100000
48#define TEGRA_ISP_SIZE SZ_256K
49
50#define TEGRA_DISPLAY_BASE 0x54200000
51#define TEGRA_DISPLAY_SIZE SZ_256K
52
53#define TEGRA_DISPLAY2_BASE 0x54240000
54#define TEGRA_DISPLAY2_SIZE SZ_256K
55
56#define TEGRA_HDMI_BASE 0x54280000
57#define TEGRA_HDMI_SIZE SZ_256K
58
59#define TEGRA_GART_BASE 0x58000000
60#define TEGRA_GART_SIZE SZ_32M
61
62#define TEGRA_RES_SEMA_BASE 0x60001000
63#define TEGRA_RES_SEMA_SIZE SZ_4K
64
65#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 33#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
66#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 34#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
67 35
@@ -98,51 +66,15 @@
98#define TEGRA_FLOW_CTRL_BASE 0x60007000 66#define TEGRA_FLOW_CTRL_BASE 0x60007000
99#define TEGRA_FLOW_CTRL_SIZE 20 67#define TEGRA_FLOW_CTRL_SIZE 20
100 68
101#define TEGRA_AHB_DMA_BASE 0x60008000
102#define TEGRA_AHB_DMA_SIZE SZ_4K
103
104#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
105#define TEGRA_AHB_DMA_CH0_SIZE 32
106
107#define TEGRA_APB_DMA_BASE 0x6000A000
108#define TEGRA_APB_DMA_SIZE SZ_4K
109
110#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
111#define TEGRA_APB_DMA_CH0_SIZE 32
112
113#define TEGRA_AHB_GIZMO_BASE 0x6000C004
114#define TEGRA_AHB_GIZMO_SIZE 0x10C
115
116#define TEGRA_SB_BASE 0x6000C200 69#define TEGRA_SB_BASE 0x6000C200
117#define TEGRA_SB_SIZE 256 70#define TEGRA_SB_SIZE 256
118 71
119#define TEGRA_STATMON_BASE 0x6000C400
120#define TEGRA_STATMON_SIZE SZ_1K
121
122#define TEGRA_GPIO_BASE 0x6000D000
123#define TEGRA_GPIO_SIZE SZ_4K
124
125#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 72#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
126#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 73#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
127 74
128#define TEGRA_APB_MISC_BASE 0x70000000 75#define TEGRA_APB_MISC_BASE 0x70000000
129#define TEGRA_APB_MISC_SIZE SZ_4K 76#define TEGRA_APB_MISC_SIZE SZ_4K
130 77
131#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
132#define TEGRA_APB_MISC_DAS_SIZE SZ_128
133
134#define TEGRA_AC97_BASE 0x70002000
135#define TEGRA_AC97_SIZE SZ_512
136
137#define TEGRA_SPDIF_BASE 0x70002400
138#define TEGRA_SPDIF_SIZE SZ_512
139
140#define TEGRA_I2S1_BASE 0x70002800
141#define TEGRA_I2S1_SIZE SZ_256
142
143#define TEGRA_I2S2_BASE 0x70002A00
144#define TEGRA_I2S2_SIZE SZ_256
145
146#define TEGRA_UARTA_BASE 0x70006000 78#define TEGRA_UARTA_BASE 0x70006000
147#define TEGRA_UARTA_SIZE SZ_64 79#define TEGRA_UARTA_SIZE SZ_64
148 80
@@ -158,108 +90,27 @@
158#define TEGRA_UARTE_BASE 0x70006400 90#define TEGRA_UARTE_BASE 0x70006400
159#define TEGRA_UARTE_SIZE SZ_256 91#define TEGRA_UARTE_SIZE SZ_256
160 92
161#define TEGRA_NAND_BASE 0x70008000
162#define TEGRA_NAND_SIZE SZ_256
163
164#define TEGRA_HSMMC_BASE 0x70008500
165#define TEGRA_HSMMC_SIZE SZ_256
166
167#define TEGRA_SNOR_BASE 0x70009000
168#define TEGRA_SNOR_SIZE SZ_4K
169
170#define TEGRA_PWFM_BASE 0x7000A000
171#define TEGRA_PWFM_SIZE SZ_256
172
173#define TEGRA_PWFM0_BASE 0x7000A000
174#define TEGRA_PWFM0_SIZE 4
175
176#define TEGRA_PWFM1_BASE 0x7000A010
177#define TEGRA_PWFM1_SIZE 4
178
179#define TEGRA_PWFM2_BASE 0x7000A020
180#define TEGRA_PWFM2_SIZE 4
181
182#define TEGRA_PWFM3_BASE 0x7000A030
183#define TEGRA_PWFM3_SIZE 4
184
185#define TEGRA_MIPI_BASE 0x7000B000
186#define TEGRA_MIPI_SIZE SZ_256
187
188#define TEGRA_I2C_BASE 0x7000C000
189#define TEGRA_I2C_SIZE SZ_256
190
191#define TEGRA_TWC_BASE 0x7000C100
192#define TEGRA_TWC_SIZE SZ_256
193
194#define TEGRA_SPI_BASE 0x7000C380
195#define TEGRA_SPI_SIZE 48
196
197#define TEGRA_I2C2_BASE 0x7000C400
198#define TEGRA_I2C2_SIZE SZ_256
199
200#define TEGRA_I2C3_BASE 0x7000C500
201#define TEGRA_I2C3_SIZE SZ_256
202
203#define TEGRA_OWR_BASE 0x7000C600
204#define TEGRA_OWR_SIZE 80
205
206#define TEGRA_DVC_BASE 0x7000D000
207#define TEGRA_DVC_SIZE SZ_512
208
209#define TEGRA_SPI1_BASE 0x7000D400
210#define TEGRA_SPI1_SIZE SZ_512
211
212#define TEGRA_SPI2_BASE 0x7000D600
213#define TEGRA_SPI2_SIZE SZ_512
214
215#define TEGRA_SPI3_BASE 0x7000D800
216#define TEGRA_SPI3_SIZE SZ_512
217
218#define TEGRA_SPI4_BASE 0x7000DA00
219#define TEGRA_SPI4_SIZE SZ_512
220
221#define TEGRA_RTC_BASE 0x7000E000
222#define TEGRA_RTC_SIZE SZ_256
223
224#define TEGRA_KBC_BASE 0x7000E200
225#define TEGRA_KBC_SIZE SZ_256
226
227#define TEGRA_PMC_BASE 0x7000E400 93#define TEGRA_PMC_BASE 0x7000E400
228#define TEGRA_PMC_SIZE SZ_256 94#define TEGRA_PMC_SIZE SZ_256
229 95
230#define TEGRA_MC_BASE 0x7000F000
231#define TEGRA_MC_SIZE SZ_1K
232
233#define TEGRA_EMC_BASE 0x7000F400 96#define TEGRA_EMC_BASE 0x7000F400
234#define TEGRA_EMC_SIZE SZ_1K 97#define TEGRA_EMC_SIZE SZ_1K
235 98
236#define TEGRA_FUSE_BASE 0x7000F800 99#define TEGRA_FUSE_BASE 0x7000F800
237#define TEGRA_FUSE_SIZE SZ_1K 100#define TEGRA_FUSE_SIZE SZ_1K
238 101
239#define TEGRA_KFUSE_BASE 0x7000FC00
240#define TEGRA_KFUSE_SIZE SZ_1K
241
242#define TEGRA_EMC0_BASE 0x7001A000 102#define TEGRA_EMC0_BASE 0x7001A000
243#define TEGRA_EMC0_SIZE SZ_2K 103#define TEGRA_EMC0_SIZE SZ_2K
244 104
245#define TEGRA_EMC1_BASE 0x7001A800 105#define TEGRA_EMC1_BASE 0x7001A800
246#define TEGRA_EMC1_SIZE SZ_2K 106#define TEGRA_EMC1_SIZE SZ_2K
247 107
108#define TEGRA124_EMC_BASE 0x7001B000
109#define TEGRA124_EMC_SIZE SZ_2K
110
248#define TEGRA_CSITE_BASE 0x70040000 111#define TEGRA_CSITE_BASE 0x70040000
249#define TEGRA_CSITE_SIZE SZ_256K 112#define TEGRA_CSITE_SIZE SZ_256K
250 113
251#define TEGRA_SDMMC1_BASE 0xC8000000
252#define TEGRA_SDMMC1_SIZE SZ_512
253
254#define TEGRA_SDMMC2_BASE 0xC8000200
255#define TEGRA_SDMMC2_SIZE SZ_512
256
257#define TEGRA_SDMMC3_BASE 0xC8000400
258#define TEGRA_SDMMC3_SIZE SZ_512
259
260#define TEGRA_SDMMC4_BASE 0xC8000600
261#define TEGRA_SDMMC4_SIZE SZ_512
262
263/* On TEGRA, many peripherals are very closely packed in 114/* On TEGRA, many peripherals are very closely packed in
264 * two 256MB io windows (that actually only use about 64KB 115 * two 256MB io windows (that actually only use about 64KB
265 * at the start of each). 116 * at the start of each).
diff --git a/arch/arm/mach-tegra/irammap.h b/arch/arm/mach-tegra/irammap.h
index 501952a84344..e32e1742c9a1 100644
--- a/arch/arm/mach-tegra/irammap.h
+++ b/arch/arm/mach-tegra/irammap.h
@@ -23,4 +23,10 @@
23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K 24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
25 25
26/*
27 * This area is used for LPx resume vector, only while LPx power state is
28 * active. At other times, the AVP may use this area for arbitrary purposes
29 */
30#define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K)
31
26#endif 32#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 2d0203627fbb..eb72ae709124 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -176,6 +176,8 @@ static int tegra_boot_secondary(unsigned int cpu,
176 return tegra30_boot_secondary(cpu, idle); 176 return tegra30_boot_secondary(cpu, idle);
177 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) 177 if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
178 return tegra114_boot_secondary(cpu, idle); 178 return tegra114_boot_secondary(cpu, idle);
179 if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124)
180 return tegra114_boot_secondary(cpu, idle);
179 181
180 return -EINVAL; 182 return -EINVAL;
181} 183}
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index ed294a04e1d3..4ae0286b468d 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -59,8 +59,10 @@ static void tegra_tear_down_cpu_init(void)
59 break; 59 break;
60 case TEGRA30: 60 case TEGRA30:
61 case TEGRA114: 61 case TEGRA114:
62 case TEGRA124:
62 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 63 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
63 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) 64 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
65 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
64 tegra_tear_down_cpu = tegra30_tear_down_cpu; 66 tegra_tear_down_cpu = tegra30_tear_down_cpu;
65 break; 67 break;
66 } 68 }
@@ -216,8 +218,10 @@ static bool tegra_lp1_iram_hook(void)
216 break; 218 break;
217 case TEGRA30: 219 case TEGRA30:
218 case TEGRA114: 220 case TEGRA114:
221 case TEGRA124:
219 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 222 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
220 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) 223 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
224 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
221 tegra30_lp1_iram_hook(); 225 tegra30_lp1_iram_hook();
222 break; 226 break;
223 default: 227 default:
@@ -244,8 +248,10 @@ static bool tegra_sleep_core_init(void)
244 break; 248 break;
245 case TEGRA30: 249 case TEGRA30:
246 case TEGRA114: 250 case TEGRA114:
251 case TEGRA124:
247 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || 252 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
248 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) 253 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
254 IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
249 tegra30_sleep_core_init(); 255 tegra30_sleep_core_init();
250 break; 256 break;
251 default: 257 default:
@@ -263,10 +269,10 @@ static void tegra_suspend_enter_lp1(void)
263 tegra_pmc_suspend(); 269 tegra_pmc_suspend();
264 270
265 /* copy the reset vector & SDRAM shutdown code into IRAM */ 271 /* copy the reset vector & SDRAM shutdown code into IRAM */
266 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA), 272 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
267 iram_save_size);
268 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
269 iram_save_size); 273 iram_save_size);
274 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
275 tegra_lp1_iram.start_addr, iram_save_size);
270 276
271 *((u32 *)tegra_cpu_lp1_mask) = 1; 277 *((u32 *)tegra_cpu_lp1_mask) = 1;
272} 278}
@@ -276,7 +282,7 @@ static void tegra_suspend_exit_lp1(void)
276 tegra_pmc_resume(); 282 tegra_pmc_resume();
277 283
278 /* restore IRAM */ 284 /* restore IRAM */
279 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr, 285 memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
280 iram_save_size); 286 iram_save_size);
281 287
282 *(u32 *)tegra_cpu_lp1_mask = 0; 288 *(u32 *)tegra_cpu_lp1_mask = 0;
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index fe204e5256e7..6e92a7c2ecbd 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -37,9 +37,6 @@ void tegra30_sleep_core_init(void);
37 37
38extern unsigned long l2x0_saved_regs_addr; 38extern unsigned long l2x0_saved_regs_addr;
39 39
40void save_cpu_arch_register(void);
41void restore_cpu_arch_register(void);
42
43void tegra_clear_cpu_in_lp2(void); 40void tegra_clear_cpu_in_lp2(void);
44bool tegra_set_cpu_in_lp2(void); 41bool tegra_set_cpu_in_lp2(void);
45 42
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 8acb881f7cfe..fb7920201ab4 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/tegra-powergate.h>
23 24
24#include "flowctrl.h" 25#include "flowctrl.h"
25#include "fuse.h" 26#include "fuse.h"
@@ -43,12 +44,6 @@
43#define PMC_CPUPWRGOOD_TIMER 0xc8 44#define PMC_CPUPWRGOOD_TIMER 0xc8
44#define PMC_CPUPWROFF_TIMER 0xcc 45#define PMC_CPUPWROFF_TIMER 0xcc
45 46
46#define TEGRA_POWERGATE_PCIE 3
47#define TEGRA_POWERGATE_VDEC 4
48#define TEGRA_POWERGATE_CPU1 9
49#define TEGRA_POWERGATE_CPU2 10
50#define TEGRA_POWERGATE_CPU3 11
51
52static u8 tegra_cpu_domains[] = { 47static u8 tegra_cpu_domains[] = {
53 0xFF, /* not available for CPU0 */ 48 0xFF, /* not available for CPU0 */
54 TEGRA_POWERGATE_CPU1, 49 TEGRA_POWERGATE_CPU1,
@@ -166,6 +161,15 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
166 return tegra_pmc_powergate_remove_clamping(id); 161 return tegra_pmc_powergate_remove_clamping(id);
167} 162}
168 163
164void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
165{
166 u32 val;
167
168 val = tegra_pmc_readl(0);
169 val |= 0x10;
170 tegra_pmc_writel(val, 0);
171}
172
169#ifdef CONFIG_PM_SLEEP 173#ifdef CONFIG_PM_SLEEP
170static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) 174static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
171{ 175{
@@ -279,19 +283,17 @@ void tegra_pmc_suspend_init(void)
279#endif 283#endif
280 284
281static const struct of_device_id matches[] __initconst = { 285static const struct of_device_id matches[] __initconst = {
286 { .compatible = "nvidia,tegra124-pmc" },
282 { .compatible = "nvidia,tegra114-pmc" }, 287 { .compatible = "nvidia,tegra114-pmc" },
283 { .compatible = "nvidia,tegra30-pmc" }, 288 { .compatible = "nvidia,tegra30-pmc" },
284 { .compatible = "nvidia,tegra20-pmc" }, 289 { .compatible = "nvidia,tegra20-pmc" },
285 { } 290 { }
286}; 291};
287 292
288static void __init tegra_pmc_parse_dt(void) 293void __init tegra_pmc_init_irq(void)
289{ 294{
290 struct device_node *np; 295 struct device_node *np;
291 u32 prop; 296 u32 val;
292 enum tegra_suspend_mode suspend_mode;
293 u32 core_good_time[2] = {0, 0};
294 u32 lp0_vec[2] = {0, 0};
295 297
296 np = of_find_matching_node(NULL, matches); 298 np = of_find_matching_node(NULL, matches);
297 BUG_ON(!np); 299 BUG_ON(!np);
@@ -300,6 +302,26 @@ static void __init tegra_pmc_parse_dt(void)
300 302
301 tegra_pmc_invert_interrupt = of_property_read_bool(np, 303 tegra_pmc_invert_interrupt = of_property_read_bool(np,
302 "nvidia,invert-interrupt"); 304 "nvidia,invert-interrupt");
305
306 val = tegra_pmc_readl(PMC_CTRL);
307 if (tegra_pmc_invert_interrupt)
308 val |= PMC_CTRL_INTR_LOW;
309 else
310 val &= ~PMC_CTRL_INTR_LOW;
311 tegra_pmc_writel(val, PMC_CTRL);
312}
313
314void __init tegra_pmc_init(void)
315{
316 struct device_node *np;
317 u32 prop;
318 enum tegra_suspend_mode suspend_mode;
319 u32 core_good_time[2] = {0, 0};
320 u32 lp0_vec[2] = {0, 0};
321
322 np = of_find_matching_node(NULL, matches);
323 BUG_ON(!np);
324
303 tegra_pclk = of_clk_get_by_name(np, "pclk"); 325 tegra_pclk = of_clk_get_by_name(np, "pclk");
304 WARN_ON(IS_ERR(tegra_pclk)); 326 WARN_ON(IS_ERR(tegra_pclk));
305 327
@@ -365,17 +387,3 @@ static void __init tegra_pmc_parse_dt(void)
365 387
366 pmc_pm_data.suspend_mode = suspend_mode; 388 pmc_pm_data.suspend_mode = suspend_mode;
367} 389}
368
369void __init tegra_pmc_init(void)
370{
371 u32 val;
372
373 tegra_pmc_parse_dt();
374
375 val = tegra_pmc_readl(PMC_CTRL);
376 if (tegra_pmc_invert_interrupt)
377 val |= PMC_CTRL_INTR_LOW;
378 else
379 val &= ~PMC_CTRL_INTR_LOW;
380 tegra_pmc_writel(val, PMC_CTRL);
381}
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 549f8c7b762c..59e19c344298 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,8 @@
18#ifndef __MACH_TEGRA_PMC_H 18#ifndef __MACH_TEGRA_PMC_H
19#define __MACH_TEGRA_PMC_H 19#define __MACH_TEGRA_PMC_H
20 20
21#include <linux/reboot.h>
22
21enum tegra_suspend_mode { 23enum tegra_suspend_mode {
22 TEGRA_SUSPEND_NONE = 0, 24 TEGRA_SUSPEND_NONE = 0,
23 TEGRA_SUSPEND_LP2, /* CPU voltage off */ 25 TEGRA_SUSPEND_LP2, /* CPU voltage off */
@@ -39,6 +41,9 @@ bool tegra_pmc_cpu_is_powered(int cpuid);
39int tegra_pmc_cpu_power_on(int cpuid); 41int tegra_pmc_cpu_power_on(int cpuid);
40int tegra_pmc_cpu_remove_clamping(int cpuid); 42int tegra_pmc_cpu_remove_clamping(int cpuid);
41 43
44void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
45
46void tegra_pmc_init_irq(void);
42void tegra_pmc_init(void); 47void tegra_pmc_init(void);
43 48
44#endif 49#endif
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f076f0f80fcd..85d28e756bb7 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -42,8 +42,16 @@
42 42
43static int tegra_num_powerdomains; 43static int tegra_num_powerdomains;
44static int tegra_num_cpu_domains; 44static int tegra_num_cpu_domains;
45static u8 *tegra_cpu_domains; 45static const u8 *tegra_cpu_domains;
46static u8 tegra30_cpu_domains[] = { 46
47static const u8 tegra30_cpu_domains[] = {
48 TEGRA_POWERGATE_CPU,
49 TEGRA_POWERGATE_CPU1,
50 TEGRA_POWERGATE_CPU2,
51 TEGRA_POWERGATE_CPU3,
52};
53
54static const u8 tegra114_cpu_domains[] = {
47 TEGRA_POWERGATE_CPU0, 55 TEGRA_POWERGATE_CPU0,
48 TEGRA_POWERGATE_CPU1, 56 TEGRA_POWERGATE_CPU1,
49 TEGRA_POWERGATE_CPU2, 57 TEGRA_POWERGATE_CPU2,
@@ -189,6 +197,11 @@ int __init tegra_powergate_init(void)
189 tegra_num_cpu_domains = 4; 197 tegra_num_cpu_domains = 4;
190 tegra_cpu_domains = tegra30_cpu_domains; 198 tegra_cpu_domains = tegra30_cpu_domains;
191 break; 199 break;
200 case TEGRA114:
201 tegra_num_powerdomains = 23;
202 tegra_num_cpu_domains = 4;
203 tegra_cpu_domains = tegra114_cpu_domains;
204 break;
192 default: 205 default:
193 /* Unknown Tegra variant. Disable powergating */ 206 /* Unknown Tegra variant. Disable powergating */
194 tegra_num_powerdomains = 0; 207 tegra_num_powerdomains = 0;
@@ -229,6 +242,27 @@ static const char * const powergate_name_t30[] = {
229 [TEGRA_POWERGATE_3D1] = "3d1", 242 [TEGRA_POWERGATE_3D1] = "3d1",
230}; 243};
231 244
245static const char * const powergate_name_t114[] = {
246 [TEGRA_POWERGATE_CPU] = "cpu0",
247 [TEGRA_POWERGATE_3D] = "3d",
248 [TEGRA_POWERGATE_VENC] = "venc",
249 [TEGRA_POWERGATE_VDEC] = "vdec",
250 [TEGRA_POWERGATE_MPE] = "mpe",
251 [TEGRA_POWERGATE_HEG] = "heg",
252 [TEGRA_POWERGATE_CPU1] = "cpu1",
253 [TEGRA_POWERGATE_CPU2] = "cpu2",
254 [TEGRA_POWERGATE_CPU3] = "cpu3",
255 [TEGRA_POWERGATE_CELP] = "celp",
256 [TEGRA_POWERGATE_CPU0] = "cpu0",
257 [TEGRA_POWERGATE_C0NC] = "c0nc",
258 [TEGRA_POWERGATE_C1NC] = "c1nc",
259 [TEGRA_POWERGATE_DIS] = "dis",
260 [TEGRA_POWERGATE_DISB] = "disb",
261 [TEGRA_POWERGATE_XUSBA] = "xusba",
262 [TEGRA_POWERGATE_XUSBB] = "xusbb",
263 [TEGRA_POWERGATE_XUSBC] = "xusbc",
264};
265
232static int powergate_show(struct seq_file *s, void *data) 266static int powergate_show(struct seq_file *s, void *data)
233{ 267{
234 int i; 268 int i;
@@ -236,9 +270,14 @@ static int powergate_show(struct seq_file *s, void *data)
236 seq_printf(s, " powergate powered\n"); 270 seq_printf(s, " powergate powered\n");
237 seq_printf(s, "------------------\n"); 271 seq_printf(s, "------------------\n");
238 272
239 for (i = 0; i < tegra_num_powerdomains; i++) 273 for (i = 0; i < tegra_num_powerdomains; i++) {
274 if (!powergate_name[i])
275 continue;
276
240 seq_printf(s, " %9s %7s\n", powergate_name[i], 277 seq_printf(s, " %9s %7s\n", powergate_name[i],
241 tegra_powergate_is_powered(i) ? "yes" : "no"); 278 tegra_powergate_is_powered(i) ? "yes" : "no");
279 }
280
242 return 0; 281 return 0;
243} 282}
244 283
@@ -265,6 +304,9 @@ int __init tegra_powergate_debugfs_init(void)
265 case TEGRA30: 304 case TEGRA30:
266 powergate_name = powergate_name_t30; 305 powergate_name = powergate_name_t30;
267 break; 306 break;
307 case TEGRA114:
308 powergate_name = powergate_name_t114;
309 break;
268 } 310 }
269 311
270 if (powergate_name) { 312 if (powergate_name) {
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index f527b2c2dea7..8c1ba4fea384 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -45,17 +45,11 @@
45ENTRY(tegra_resume) 45ENTRY(tegra_resume)
46 check_cpu_part_num 0xc09, r8, r9 46 check_cpu_part_num 0xc09, r8, r9
47 bleq v7_invalidate_l1 47 bleq v7_invalidate_l1
48 blne tegra_init_l2_for_a15
49 48
50 cpu_id r0 49 cpu_id r0
51 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
52 cmp r6, #TEGRA114
53 beq no_cpu0_chk
54
55 cmp r0, #0 @ CPU0? 50 cmp r0, #0 @ CPU0?
56 THUMB( it ne ) 51 THUMB( it ne )
57 bne cpu_resume @ no 52 bne cpu_resume @ no
58no_cpu0_chk:
59 53
60 /* Are we on Tegra20? */ 54 /* Are we on Tegra20? */
61 cmp r6, #TEGRA20 55 cmp r6, #TEGRA20
@@ -75,7 +69,7 @@ no_cpu0_chk:
75 69
76 mov32 r9, 0xc09 70 mov32 r9, 0xc09
77 cmp r8, r9 71 cmp r8, r9
78 bne not_ca9 72 bne end_ca9_scu_l2_resume
79#ifdef CONFIG_HAVE_ARM_SCU 73#ifdef CONFIG_HAVE_ARM_SCU
80 /* enable SCU */ 74 /* enable SCU */
81 mov32 r0, TEGRA_ARM_PERIF_BASE 75 mov32 r0, TEGRA_ARM_PERIF_BASE
@@ -86,7 +80,10 @@ no_cpu0_chk:
86 80
87 /* L2 cache resume & re-enable */ 81 /* L2 cache resume & re-enable */
88 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr 82 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
89not_ca9: 83end_ca9_scu_l2_resume:
84 mov32 r9, 0xc0f
85 cmp r8, r9
86 bleq tegra_init_l2_for_a15
90 87
91 b cpu_resume 88 b cpu_resume
92ENDPROC(tegra_resume) 89ENDPROC(tegra_resume)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index fd0bbf8a6c94..568f5bbf979d 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -82,7 +82,7 @@ void __init tegra_cpu_reset_handler_init(void)
82 82
83#ifdef CONFIG_PM_SLEEP 83#ifdef CONFIG_PM_SLEEP
84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = 84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
85 TEGRA_IRAM_CODE_AREA; 85 TEGRA_IRAM_LPx_RESUME_AREA;
86 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = 86 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
87 virt_to_phys((void *)tegra_resume); 87 virt_to_phys((void *)tegra_resume);
88#endif 88#endif
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 5c3bd11c9838..aaaf3abd2688 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -25,6 +25,7 @@
25#include <asm/cp15.h> 25#include <asm/cp15.h>
26#include <asm/cache.h> 26#include <asm/cache.h>
27 27
28#include "irammap.h"
28#include "sleep.h" 29#include "sleep.h"
29#include "flowctrl.h" 30#include "flowctrl.h"
30 31
@@ -235,7 +236,7 @@ ENTRY(tegra20_sleep_core_finish)
235 mov32 r0, tegra20_tear_down_core 236 mov32 r0, tegra20_tear_down_core
236 mov32 r1, tegra20_iram_start 237 mov32 r1, tegra20_iram_start
237 sub r0, r0, r1 238 sub r0, r0, r1
238 mov32 r1, TEGRA_IRAM_CODE_AREA 239 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
239 add r0, r0, r1 240 add r0, r0, r1
240 241
241 mov pc, r3 242 mov pc, r3
@@ -328,7 +329,7 @@ tegra20_iram_start:
328 * The physical address of tegra_resume expected to be stored in 329 * The physical address of tegra_resume expected to be stored in
329 * PMC_SCRATCH41. 330 * PMC_SCRATCH41.
330 * 331 *
331 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. 332 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
332 */ 333 */
333ENTRY(tegra20_lp1_reset) 334ENTRY(tegra20_lp1_reset)
334 /* 335 /*
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index 63fa91b5fafb..b16d4a57fa59 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -20,6 +20,7 @@
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/cache.h> 21#include <asm/cache.h>
22 22
23#include "irammap.h"
23#include "fuse.h" 24#include "fuse.h"
24#include "sleep.h" 25#include "sleep.h"
25#include "flowctrl.h" 26#include "flowctrl.h"
@@ -262,7 +263,7 @@ ENTRY(tegra30_sleep_core_finish)
262 mov32 r0, tegra30_tear_down_core 263 mov32 r0, tegra30_tear_down_core
263 mov32 r1, tegra30_iram_start 264 mov32 r1, tegra30_iram_start
264 sub r0, r0, r1 265 sub r0, r0, r1
265 mov32 r1, TEGRA_IRAM_CODE_AREA 266 mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
266 add r0, r0, r1 267 add r0, r0, r1
267 268
268 mov pc, r3 269 mov pc, r3
@@ -314,7 +315,7 @@ tegra30_iram_start:
314 * The physical address of tegra_resume expected to be stored in 315 * The physical address of tegra_resume expected to be stored in
315 * PMC_SCRATCH41. 316 * PMC_SCRATCH41.
316 * 317 *
317 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA. 318 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
318 */ 319 */
319ENTRY(tegra30_lp1_reset) 320ENTRY(tegra30_lp1_reset)
320 /* 321 /*
@@ -382,7 +383,7 @@ _pll_m_c_x_done:
382 add r1, r1, #LOCK_DELAY 383 add r1, r1, #LOCK_DELAY
383 wait_until r1, r7, r3 384 wait_until r1, r7, r3
384 385
385 adr r5, tegra30_sdram_pad_save 386 adr r5, tegra_sdram_pad_save
386 387
387 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT 388 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
388 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT] 389 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
@@ -407,8 +408,12 @@ _pll_m_c_x_done:
407 cmp r10, #TEGRA30 408 cmp r10, #TEGRA30
408 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base 409 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
409 movteq r0, #:upper16:TEGRA_EMC_BASE 410 movteq r0, #:upper16:TEGRA_EMC_BASE
410 movwne r0, #:lower16:TEGRA_EMC0_BASE 411 cmp r10, #TEGRA114
411 movtne r0, #:upper16:TEGRA_EMC0_BASE 412 movweq r0, #:lower16:TEGRA_EMC0_BASE
413 movteq r0, #:upper16:TEGRA_EMC0_BASE
414 cmp r10, #TEGRA124
415 movweq r0, #:lower16:TEGRA124_EMC_BASE
416 movteq r0, #:upper16:TEGRA124_EMC_BASE
412 417
413exit_self_refresh: 418exit_self_refresh:
414 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL 419 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
@@ -537,6 +542,7 @@ tegra30_sdram_pad_address:
537 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14 542 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
538 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18 543 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
539 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c 544 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
545tegra30_sdram_pad_address_end:
540 546
541tegra114_sdram_pad_address: 547tegra114_sdram_pad_address:
542 .word TEGRA_EMC0_BASE + EMC_CFG @0x0 548 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
@@ -552,16 +558,28 @@ tegra114_sdram_pad_address:
552 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28 558 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
553 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c 559 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
554 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30 560 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
561tegra114_sdram_pad_adress_end:
562
563tegra124_sdram_pad_address:
564 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
565 .word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
566 .word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
567 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
568 .word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
569 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
570 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
571 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
572tegra124_sdram_pad_address_end:
555 573
556tegra30_sdram_pad_size: 574tegra30_sdram_pad_size:
557 .word tegra114_sdram_pad_address - tegra30_sdram_pad_address 575 .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
558 576
559tegra114_sdram_pad_size: 577tegra114_sdram_pad_size:
560 .word tegra30_sdram_pad_size - tegra114_sdram_pad_address 578 .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
561 579
562 .type tegra30_sdram_pad_save, %object 580 .type tegra_sdram_pad_save, %object
563tegra30_sdram_pad_save: 581tegra_sdram_pad_save:
564 .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4 582 .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
565 .long 0 583 .long 0
566 .endr 584 .endr
567 585
@@ -692,13 +710,18 @@ halted:
692 */ 710 */
693tegra30_sdram_self_refresh: 711tegra30_sdram_self_refresh:
694 712
695 adr r8, tegra30_sdram_pad_save 713 adr r8, tegra_sdram_pad_save
696 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10 714 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
697 cmp r10, #TEGRA30 715 cmp r10, #TEGRA30
698 adreq r2, tegra30_sdram_pad_address 716 adreq r2, tegra30_sdram_pad_address
699 ldreq r3, tegra30_sdram_pad_size 717 ldreq r3, tegra30_sdram_pad_size
700 adrne r2, tegra114_sdram_pad_address 718 cmp r10, #TEGRA114
701 ldrne r3, tegra114_sdram_pad_size 719 adreq r2, tegra114_sdram_pad_address
720 ldreq r3, tegra114_sdram_pad_size
721 cmp r10, #TEGRA124
722 adreq r2, tegra124_sdram_pad_address
723 ldreq r3, tegra30_sdram_pad_size
724
702 mov r9, #0 725 mov r9, #0
703 726
704padsave: 727padsave:
@@ -716,7 +739,10 @@ padsave_done:
716 739
717 cmp r10, #TEGRA30 740 cmp r10, #TEGRA30
718 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr 741 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
719 ldrne r0, =TEGRA_EMC0_BASE 742 cmp r10, #TEGRA114
743 ldreq r0, =TEGRA_EMC0_BASE
744 cmp r10, #TEGRA124
745 ldreq r0, =TEGRA124_EMC_BASE
720 746
721enter_self_refresh: 747enter_self_refresh:
722 cmp r10, #TEGRA30 748 cmp r10, #TEGRA30
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 5b8605547a09..ce553d557c31 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -16,7 +16,6 @@
16 * 16 *
17 */ 17 */
18 18
19#include <linux/clocksource.h>
20#include <linux/kernel.h> 19#include <linux/kernel.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -34,16 +33,78 @@
34#include <linux/sys_soc.h> 33#include <linux/sys_soc.h>
35#include <linux/usb/tegra_usb_phy.h> 34#include <linux/usb/tegra_usb_phy.h>
36#include <linux/clk/tegra.h> 35#include <linux/clk/tegra.h>
36#include <linux/irqchip.h>
37 37
38#include <asm/hardware/cache-l2x0.h>
38#include <asm/mach-types.h> 39#include <asm/mach-types.h>
39#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 41#include <asm/mach/time.h>
41#include <asm/setup.h> 42#include <asm/setup.h>
42 43
44#include "apbio.h"
43#include "board.h" 45#include "board.h"
44#include "common.h" 46#include "common.h"
47#include "cpuidle.h"
45#include "fuse.h" 48#include "fuse.h"
46#include "iomap.h" 49#include "iomap.h"
50#include "irq.h"
51#include "pmc.h"
52#include "pm.h"
53#include "reset.h"
54#include "sleep.h"
55
56/*
57 * Storage for debug-macro.S's state.
58 *
59 * This must be in .data not .bss so that it gets initialized each time the
60 * kernel is loaded. The data is declared here rather than debug-macro.S so
61 * that multiple inclusions of debug-macro.S point at the same data.
62 */
63u32 tegra_uart_config[4] = {
64 /* Debug UART initialization required */
65 1,
66 /* Debug UART physical address */
67 0,
68 /* Debug UART virtual address */
69 0,
70 /* Scratch space for debug macro */
71 0,
72};
73
74static void __init tegra_init_cache(void)
75{
76#ifdef CONFIG_CACHE_L2X0
77 int ret;
78 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
79 u32 aux_ctrl, cache_type;
80
81 cache_type = readl(p + L2X0_CACHE_TYPE);
82 aux_ctrl = (cache_type & 0x700) << (17-8);
83 aux_ctrl |= 0x7C400001;
84
85 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
86 if (!ret)
87 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
88#endif
89}
90
91static void __init tegra_init_early(void)
92{
93 tegra_cpu_reset_handler_init();
94 tegra_apb_io_init();
95 tegra_init_fuse();
96 tegra_init_cache();
97 tegra_powergate_init();
98 tegra_hotplug_init();
99}
100
101static void __init tegra_dt_init_irq(void)
102{
103 tegra_pmc_init_irq();
104 tegra_init_irq();
105 irqchip_init();
106 tegra_legacy_irq_syscore_init();
107}
47 108
48static void __init tegra_dt_init(void) 109static void __init tegra_dt_init(void)
49{ 110{
@@ -51,6 +112,8 @@ static void __init tegra_dt_init(void)
51 struct soc_device *soc_dev; 112 struct soc_device *soc_dev;
52 struct device *parent = NULL; 113 struct device *parent = NULL;
53 114
115 tegra_pmc_init();
116
54 tegra_clocks_apply_init_table(); 117 tegra_clocks_apply_init_table();
55 118
56 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); 119 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
@@ -97,7 +160,9 @@ static void __init tegra_dt_init_late(void)
97{ 160{
98 int i; 161 int i;
99 162
100 tegra_init_late(); 163 tegra_init_suspend();
164 tegra_cpuidle_init();
165 tegra_powergate_debugfs_init();
101 166
102 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { 167 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
103 if (of_machine_is_compatible(board_init_funcs[i].machine)) { 168 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
@@ -108,6 +173,7 @@ static void __init tegra_dt_init_late(void)
108} 173}
109 174
110static const char * const tegra_dt_board_compat[] = { 175static const char * const tegra_dt_board_compat[] = {
176 "nvidia,tegra124",
111 "nvidia,tegra114", 177 "nvidia,tegra114",
112 "nvidia,tegra30", 178 "nvidia,tegra30",
113 "nvidia,tegra20", 179 "nvidia,tegra20",
@@ -119,9 +185,8 @@ DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
119 .smp = smp_ops(tegra_smp_ops), 185 .smp = smp_ops(tegra_smp_ops),
120 .init_early = tegra_init_early, 186 .init_early = tegra_init_early,
121 .init_irq = tegra_dt_init_irq, 187 .init_irq = tegra_dt_init_irq,
122 .init_time = clocksource_of_init,
123 .init_machine = tegra_dt_init, 188 .init_machine = tegra_dt_init,
124 .init_late = tegra_dt_init_late, 189 .init_late = tegra_dt_init_late,
125 .restart = tegra_assert_system_reset, 190 .restart = tegra_pmc_restart,
126 .dt_compat = tegra_dt_board_compat, 191 .dt_compat = tegra_dt_board_compat,
127MACHINE_END 192MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 11:21:50 -0400