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-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c27
-rw-r--r--arch/arm/mach-tegra/board-pinmux.c87
-rw-r--r--arch/arm/mach-tegra/board-pinmux.h54
-rw-r--r--arch/arm/mach-tegra/devices.c701
-rw-r--r--arch/arm/mach-tegra/devices.h60
-rw-r--r--arch/arm/mach-tegra/include/mach/gpio-tegra.h28
-rw-r--r--arch/arm/mach-tegra/include/mach/pinconf-tegra.h63
-rw-r--r--arch/arm/mach-tegra/include/mach/suspend.h38
-rw-r--r--arch/arm/mach-tegra/include/mach/usb_phy.h86
-rw-r--r--arch/arm/mach-tegra/pcie.c12
-rw-r--r--arch/arm/mach-tegra/powergate.c43
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c21
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c15
-rw-r--r--arch/arm/mach-tegra/timer.c1
-rw-r--r--arch/arm/mach-tegra/usb_phy.c817
17 files changed, 81 insertions, 1976 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 04eb74e3f601..9aa653b3eb32 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,4 @@
1obj-y += board-pinmux.o
2obj-y += common.o 1obj-y += common.o
3obj-y += devices.o
4obj-y += io.o 2obj-y += io.o
5obj-y += irq.o 3obj-y += irq.o
6obj-y += clock.o 4obj-y += clock.o
@@ -24,7 +22,6 @@ obj-$(CONFIG_SMP) += reset.o
24obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 22obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
25obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o 23obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
26obj-$(CONFIG_TEGRA_PCI) += pcie.o 24obj-$(CONFIG_TEGRA_PCI) += pcie.o
27obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
28 25
29obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o 26obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
30obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o 27obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 5d8c8fb060b0..57e235f4ac74 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -28,9 +28,11 @@
28#include <linux/of_irq.h> 28#include <linux/of_irq.h>
29#include <linux/of_platform.h> 29#include <linux/of_platform.h>
30#include <linux/pda_power.h> 30#include <linux/pda_power.h>
31#include <linux/platform_data/tegra_usb.h>
31#include <linux/io.h> 32#include <linux/io.h>
32#include <linux/i2c.h> 33#include <linux/i2c.h>
33#include <linux/i2c-tegra.h> 34#include <linux/i2c-tegra.h>
35#include <linux/usb/tegra_usb_phy.h>
34 36
35#include <asm/hardware/gic.h> 37#include <asm/hardware/gic.h>
36#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -43,9 +45,32 @@
43 45
44#include "board.h" 46#include "board.h"
45#include "clock.h" 47#include "clock.h"
46#include "devices.h"
47#include "common.h" 48#include "common.h"
48 49
50struct tegra_ehci_platform_data tegra_ehci1_pdata = {
51 .operating_mode = TEGRA_USB_OTG,
52 .power_down_on_bus_suspend = 1,
53 .vbus_gpio = -1,
54};
55
56struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
57 .reset_gpio = -1,
58 .clk = "cdev2",
59};
60
61struct tegra_ehci_platform_data tegra_ehci2_pdata = {
62 .phy_config = &tegra_ehci2_ulpi_phy_config,
63 .operating_mode = TEGRA_USB_HOST,
64 .power_down_on_bus_suspend = 1,
65 .vbus_gpio = -1,
66};
67
68struct tegra_ehci_platform_data tegra_ehci3_pdata = {
69 .operating_mode = TEGRA_USB_HOST,
70 .power_down_on_bus_suspend = 1,
71 .vbus_gpio = -1,
72};
73
49struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 74struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
50 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 75 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
51 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), 76 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
deleted file mode 100644
index a5574c71b931..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/device.h>
16#include <linux/kernel.h>
17#include <linux/notifier.h>
18#include <linux/string.h>
19
20#include "board-pinmux.h"
21#include "devices.h"
22
23unsigned long tegra_pincfg_pullnone_driven[2] = {
24 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
25 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
26};
27
28unsigned long tegra_pincfg_pullnone_tristate[2] = {
29 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
30 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
31};
32
33unsigned long tegra_pincfg_pullnone_na[1] = {
34 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
35};
36
37unsigned long tegra_pincfg_pullup_driven[2] = {
38 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
39 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
40};
41
42unsigned long tegra_pincfg_pullup_tristate[2] = {
43 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
44 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
45};
46
47unsigned long tegra_pincfg_pullup_na[1] = {
48 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
49};
50
51unsigned long tegra_pincfg_pulldown_driven[2] = {
52 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
53 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
54};
55
56unsigned long tegra_pincfg_pulldown_tristate[2] = {
57 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
58 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
59};
60
61unsigned long tegra_pincfg_pulldown_na[1] = {
62 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
63};
64
65unsigned long tegra_pincfg_pullna_driven[1] = {
66 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
67};
68
69unsigned long tegra_pincfg_pullna_tristate[1] = {
70 TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
71};
72
73static struct platform_device *devices[] = {
74 &tegra_gpio_device,
75 &tegra_pinmux_device,
76};
77
78void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
79 struct tegra_board_pinmux_conf *conf_b)
80{
81 if (conf_a)
82 pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
83 if (conf_b)
84 pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
85
86 platform_add_devices(devices, ARRAY_SIZE(devices));
87}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
deleted file mode 100644
index c5f3f3381e86..000000000000
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef __MACH_TEGRA_BOARD_PINMUX_H
16#define __MACH_TEGRA_BOARD_PINMUX_H
17
18#include <linux/pinctrl/machine.h>
19
20#include <mach/pinconf-tegra.h>
21
22#define PINMUX_DEV "tegra20-pinctrl"
23
24#define TEGRA_MAP_MUX(_group_, _function_) \
25 PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
26
27#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
28 PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
29
30#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
31 TEGRA_MAP_MUX(_group_, _function_), \
32 TEGRA_MAP_CONF(_group_, _pull_, _drive_)
33
34extern unsigned long tegra_pincfg_pullnone_driven[2];
35extern unsigned long tegra_pincfg_pullnone_tristate[2];
36extern unsigned long tegra_pincfg_pullnone_na[1];
37extern unsigned long tegra_pincfg_pullup_driven[2];
38extern unsigned long tegra_pincfg_pullup_tristate[2];
39extern unsigned long tegra_pincfg_pullup_na[1];
40extern unsigned long tegra_pincfg_pulldown_driven[2];
41extern unsigned long tegra_pincfg_pulldown_tristate[2];
42extern unsigned long tegra_pincfg_pulldown_na[1];
43extern unsigned long tegra_pincfg_pullna_driven[1];
44extern unsigned long tegra_pincfg_pullna_tristate[1];
45
46struct tegra_board_pinmux_conf {
47 struct pinctrl_map *maps;
48 int map_count;
49};
50
51void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
52 struct tegra_board_pinmux_conf *conf_b);
53
54#endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
deleted file mode 100644
index 61e9603744a7..000000000000
--- a/arch/arm/mach-tegra/devices.c
+++ /dev/null
@@ -1,701 +0,0 @@
1/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19
20#include <linux/resource.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/fsl_devices.h>
24#include <linux/serial_8250.h>
25#include <linux/i2c-tegra.h>
26#include <mach/irqs.h>
27#include <mach/iomap.h>
28#include <mach/dma.h>
29#include <mach/usb_phy.h>
30
31#include "gpio-names.h"
32#include "devices.h"
33
34static struct resource gpio_resource[] = {
35 [0] = {
36 .start = TEGRA_GPIO_BASE,
37 .end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = INT_GPIO1,
42 .end = INT_GPIO1,
43 .flags = IORESOURCE_IRQ,
44 },
45 [2] = {
46 .start = INT_GPIO2,
47 .end = INT_GPIO2,
48 .flags = IORESOURCE_IRQ,
49 },
50 [3] = {
51 .start = INT_GPIO3,
52 .end = INT_GPIO3,
53 .flags = IORESOURCE_IRQ,
54 },
55 [4] = {
56 .start = INT_GPIO4,
57 .end = INT_GPIO4,
58 .flags = IORESOURCE_IRQ,
59 },
60 [5] = {
61 .start = INT_GPIO5,
62 .end = INT_GPIO5,
63 .flags = IORESOURCE_IRQ,
64 },
65 [6] = {
66 .start = INT_GPIO6,
67 .end = INT_GPIO6,
68 .flags = IORESOURCE_IRQ,
69 },
70 [7] = {
71 .start = INT_GPIO7,
72 .end = INT_GPIO7,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77struct platform_device tegra_gpio_device = {
78 .name = "tegra-gpio",
79 .id = -1,
80 .resource = gpio_resource,
81 .num_resources = ARRAY_SIZE(gpio_resource),
82};
83
84static struct resource pinmux_resource[] = {
85 [0] = {
86 /* Tri-state registers */
87 .start = TEGRA_APB_MISC_BASE + 0x14,
88 .end = TEGRA_APB_MISC_BASE + 0x20 + 3,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 /* Mux registers */
93 .start = TEGRA_APB_MISC_BASE + 0x80,
94 .end = TEGRA_APB_MISC_BASE + 0x9c + 3,
95 .flags = IORESOURCE_MEM,
96 },
97 [2] = {
98 /* Pull-up/down registers */
99 .start = TEGRA_APB_MISC_BASE + 0xa0,
100 .end = TEGRA_APB_MISC_BASE + 0xb0 + 3,
101 .flags = IORESOURCE_MEM,
102 },
103 [3] = {
104 /* Pad control registers */
105 .start = TEGRA_APB_MISC_BASE + 0x868,
106 .end = TEGRA_APB_MISC_BASE + 0x90c + 3,
107 .flags = IORESOURCE_MEM,
108 },
109};
110
111struct platform_device tegra_pinmux_device = {
112 .name = "tegra20-pinctrl",
113 .id = -1,
114 .resource = pinmux_resource,
115 .num_resources = ARRAY_SIZE(pinmux_resource),
116};
117
118static struct resource i2c_resource1[] = {
119 [0] = {
120 .start = INT_I2C,
121 .end = INT_I2C,
122 .flags = IORESOURCE_IRQ,
123 },
124 [1] = {
125 .start = TEGRA_I2C_BASE,
126 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
127 .flags = IORESOURCE_MEM,
128 },
129};
130
131static struct resource i2c_resource2[] = {
132 [0] = {
133 .start = INT_I2C2,
134 .end = INT_I2C2,
135 .flags = IORESOURCE_IRQ,
136 },
137 [1] = {
138 .start = TEGRA_I2C2_BASE,
139 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
140 .flags = IORESOURCE_MEM,
141 },
142};
143
144static struct resource i2c_resource3[] = {
145 [0] = {
146 .start = INT_I2C3,
147 .end = INT_I2C3,
148 .flags = IORESOURCE_IRQ,
149 },
150 [1] = {
151 .start = TEGRA_I2C3_BASE,
152 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
153 .flags = IORESOURCE_MEM,
154 },
155};
156
157static struct resource i2c_resource4[] = {
158 [0] = {
159 .start = INT_DVC,
160 .end = INT_DVC,
161 .flags = IORESOURCE_IRQ,
162 },
163 [1] = {
164 .start = TEGRA_DVC_BASE,
165 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
166 .flags = IORESOURCE_MEM,
167 },
168};
169
170static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
171 .bus_clk_rate = 400000,
172};
173
174static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
175 .bus_clk_rate = 400000,
176};
177
178static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
179 .bus_clk_rate = 400000,
180};
181
182static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
183 .bus_clk_rate = 400000,
184};
185
186struct platform_device tegra_i2c_device1 = {
187 .name = "tegra-i2c",
188 .id = 0,
189 .resource = i2c_resource1,
190 .num_resources = ARRAY_SIZE(i2c_resource1),
191 .dev = {
192 .platform_data = &tegra_i2c1_platform_data,
193 },
194};
195
196struct platform_device tegra_i2c_device2 = {
197 .name = "tegra-i2c",
198 .id = 1,
199 .resource = i2c_resource2,
200 .num_resources = ARRAY_SIZE(i2c_resource2),
201 .dev = {
202 .platform_data = &tegra_i2c2_platform_data,
203 },
204};
205
206struct platform_device tegra_i2c_device3 = {
207 .name = "tegra-i2c",
208 .id = 2,
209 .resource = i2c_resource3,
210 .num_resources = ARRAY_SIZE(i2c_resource3),
211 .dev = {
212 .platform_data = &tegra_i2c3_platform_data,
213 },
214};
215
216struct platform_device tegra_i2c_device4 = {
217 .name = "tegra-i2c",
218 .id = 3,
219 .resource = i2c_resource4,
220 .num_resources = ARRAY_SIZE(i2c_resource4),
221 .dev = {
222 .platform_data = &tegra_dvc_platform_data,
223 },
224};
225
226static struct resource spi_resource1[] = {
227 [0] = {
228 .start = INT_S_LINK1,
229 .end = INT_S_LINK1,
230 .flags = IORESOURCE_IRQ,
231 },
232 [1] = {
233 .start = TEGRA_SPI1_BASE,
234 .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
235 .flags = IORESOURCE_MEM,
236 },
237};
238
239static struct resource spi_resource2[] = {
240 [0] = {
241 .start = INT_SPI_2,
242 .end = INT_SPI_2,
243 .flags = IORESOURCE_IRQ,
244 },
245 [1] = {
246 .start = TEGRA_SPI2_BASE,
247 .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
248 .flags = IORESOURCE_MEM,
249 },
250};
251
252static struct resource spi_resource3[] = {
253 [0] = {
254 .start = INT_SPI_3,
255 .end = INT_SPI_3,
256 .flags = IORESOURCE_IRQ,
257 },
258 [1] = {
259 .start = TEGRA_SPI3_BASE,
260 .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
261 .flags = IORESOURCE_MEM,
262 },
263};
264
265static struct resource spi_resource4[] = {
266 [0] = {
267 .start = INT_SPI_4,
268 .end = INT_SPI_4,
269 .flags = IORESOURCE_IRQ,
270 },
271 [1] = {
272 .start = TEGRA_SPI4_BASE,
273 .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
274 .flags = IORESOURCE_MEM,
275 },
276};
277
278struct platform_device tegra_spi_device1 = {
279 .name = "spi_tegra",
280 .id = 0,
281 .resource = spi_resource1,
282 .num_resources = ARRAY_SIZE(spi_resource1),
283 .dev = {
284 .coherent_dma_mask = 0xffffffff,
285 },
286};
287
288struct platform_device tegra_spi_device2 = {
289 .name = "spi_tegra",
290 .id = 1,
291 .resource = spi_resource2,
292 .num_resources = ARRAY_SIZE(spi_resource2),
293 .dev = {
294 .coherent_dma_mask = 0xffffffff,
295 },
296};
297
298struct platform_device tegra_spi_device3 = {
299 .name = "spi_tegra",
300 .id = 2,
301 .resource = spi_resource3,
302 .num_resources = ARRAY_SIZE(spi_resource3),
303 .dev = {
304 .coherent_dma_mask = 0xffffffff,
305 },
306};
307
308struct platform_device tegra_spi_device4 = {
309 .name = "spi_tegra",
310 .id = 3,
311 .resource = spi_resource4,
312 .num_resources = ARRAY_SIZE(spi_resource4),
313 .dev = {
314 .coherent_dma_mask = 0xffffffff,
315 },
316};
317
318
319static struct resource sdhci_resource1[] = {
320 [0] = {
321 .start = INT_SDMMC1,
322 .end = INT_SDMMC1,
323 .flags = IORESOURCE_IRQ,
324 },
325 [1] = {
326 .start = TEGRA_SDMMC1_BASE,
327 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
328 .flags = IORESOURCE_MEM,
329 },
330};
331
332static struct resource sdhci_resource2[] = {
333 [0] = {
334 .start = INT_SDMMC2,
335 .end = INT_SDMMC2,
336 .flags = IORESOURCE_IRQ,
337 },
338 [1] = {
339 .start = TEGRA_SDMMC2_BASE,
340 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct resource sdhci_resource3[] = {
346 [0] = {
347 .start = INT_SDMMC3,
348 .end = INT_SDMMC3,
349 .flags = IORESOURCE_IRQ,
350 },
351 [1] = {
352 .start = TEGRA_SDMMC3_BASE,
353 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
354 .flags = IORESOURCE_MEM,
355 },
356};
357
358static struct resource sdhci_resource4[] = {
359 [0] = {
360 .start = INT_SDMMC4,
361 .end = INT_SDMMC4,
362 .flags = IORESOURCE_IRQ,
363 },
364 [1] = {
365 .start = TEGRA_SDMMC4_BASE,
366 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371/* board files should fill in platform_data register the devices themselvs.
372 * See board-harmony.c for an example
373 */
374struct platform_device tegra_sdhci_device1 = {
375 .name = "sdhci-tegra",
376 .id = 0,
377 .resource = sdhci_resource1,
378 .num_resources = ARRAY_SIZE(sdhci_resource1),
379};
380
381struct platform_device tegra_sdhci_device2 = {
382 .name = "sdhci-tegra",
383 .id = 1,
384 .resource = sdhci_resource2,
385 .num_resources = ARRAY_SIZE(sdhci_resource2),
386};
387
388struct platform_device tegra_sdhci_device3 = {
389 .name = "sdhci-tegra",
390 .id = 2,
391 .resource = sdhci_resource3,
392 .num_resources = ARRAY_SIZE(sdhci_resource3),
393};
394
395struct platform_device tegra_sdhci_device4 = {
396 .name = "sdhci-tegra",
397 .id = 3,
398 .resource = sdhci_resource4,
399 .num_resources = ARRAY_SIZE(sdhci_resource4),
400};
401
402static struct resource tegra_usb1_resources[] = {
403 [0] = {
404 .start = TEGRA_USB_BASE,
405 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = INT_USB,
410 .end = INT_USB,
411 .flags = IORESOURCE_IRQ,
412 },
413};
414
415static struct resource tegra_usb2_resources[] = {
416 [0] = {
417 .start = TEGRA_USB2_BASE,
418 .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
419 .flags = IORESOURCE_MEM,
420 },
421 [1] = {
422 .start = INT_USB2,
423 .end = INT_USB2,
424 .flags = IORESOURCE_IRQ,
425 },
426};
427
428static struct resource tegra_usb3_resources[] = {
429 [0] = {
430 .start = TEGRA_USB3_BASE,
431 .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = INT_USB3,
436 .end = INT_USB3,
437 .flags = IORESOURCE_IRQ,
438 },
439};
440
441struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
442 .reset_gpio = -1,
443 .clk = "cdev2",
444};
445
446struct tegra_ehci_platform_data tegra_ehci1_pdata = {
447 .operating_mode = TEGRA_USB_OTG,
448 .power_down_on_bus_suspend = 1,
449 .vbus_gpio = -1,
450};
451
452struct tegra_ehci_platform_data tegra_ehci2_pdata = {
453 .phy_config = &tegra_ehci2_ulpi_phy_config,
454 .operating_mode = TEGRA_USB_HOST,
455 .power_down_on_bus_suspend = 1,
456 .vbus_gpio = -1,
457};
458
459struct tegra_ehci_platform_data tegra_ehci3_pdata = {
460 .operating_mode = TEGRA_USB_HOST,
461 .power_down_on_bus_suspend = 1,
462 .vbus_gpio = -1,
463};
464
465static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
466
467struct platform_device tegra_ehci1_device = {
468 .name = "tegra-ehci",
469 .id = 0,
470 .dev = {
471 .dma_mask = &tegra_ehci_dmamask,
472 .coherent_dma_mask = DMA_BIT_MASK(32),
473 .platform_data = &tegra_ehci1_pdata,
474 },
475 .resource = tegra_usb1_resources,
476 .num_resources = ARRAY_SIZE(tegra_usb1_resources),
477};
478
479struct platform_device tegra_ehci2_device = {
480 .name = "tegra-ehci",
481 .id = 1,
482 .dev = {
483 .dma_mask = &tegra_ehci_dmamask,
484 .coherent_dma_mask = DMA_BIT_MASK(32),
485 .platform_data = &tegra_ehci2_pdata,
486 },
487 .resource = tegra_usb2_resources,
488 .num_resources = ARRAY_SIZE(tegra_usb2_resources),
489};
490
491struct platform_device tegra_ehci3_device = {
492 .name = "tegra-ehci",
493 .id = 2,
494 .dev = {
495 .dma_mask = &tegra_ehci_dmamask,
496 .coherent_dma_mask = DMA_BIT_MASK(32),
497 .platform_data = &tegra_ehci3_pdata,
498 },
499 .resource = tegra_usb3_resources,
500 .num_resources = ARRAY_SIZE(tegra_usb3_resources),
501};
502
503static struct resource tegra_pmu_resources[] = {
504 [0] = {
505 .start = INT_CPU0_PMU_INTR,
506 .end = INT_CPU0_PMU_INTR,
507 .flags = IORESOURCE_IRQ,
508 },
509 [1] = {
510 .start = INT_CPU1_PMU_INTR,
511 .end = INT_CPU1_PMU_INTR,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516struct platform_device tegra_pmu_device = {
517 .name = "arm-pmu",
518 .id = -1,
519 .num_resources = ARRAY_SIZE(tegra_pmu_resources),
520 .resource = tegra_pmu_resources,
521};
522
523static struct resource tegra_uarta_resources[] = {
524 [0] = {
525 .start = TEGRA_UARTA_BASE,
526 .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
527 .flags = IORESOURCE_MEM,
528 },
529 [1] = {
530 .start = INT_UARTA,
531 .end = INT_UARTA,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static struct resource tegra_uartb_resources[] = {
537 [0] = {
538 .start = TEGRA_UARTB_BASE,
539 .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
543 .start = INT_UARTB,
544 .end = INT_UARTB,
545 .flags = IORESOURCE_IRQ,
546 },
547};
548
549static struct resource tegra_uartc_resources[] = {
550 [0] = {
551 .start = TEGRA_UARTC_BASE,
552 .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
553 .flags = IORESOURCE_MEM,
554 },
555 [1] = {
556 .start = INT_UARTC,
557 .end = INT_UARTC,
558 .flags = IORESOURCE_IRQ,
559 },
560};
561
562static struct resource tegra_uartd_resources[] = {
563 [0] = {
564 .start = TEGRA_UARTD_BASE,
565 .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
569 .start = INT_UARTD,
570 .end = INT_UARTD,
571 .flags = IORESOURCE_IRQ,
572 },
573};
574
575static struct resource tegra_uarte_resources[] = {
576 [0] = {
577 .start = TEGRA_UARTE_BASE,
578 .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
579 .flags = IORESOURCE_MEM,
580 },
581 [1] = {
582 .start = INT_UARTE,
583 .end = INT_UARTE,
584 .flags = IORESOURCE_IRQ,
585 },
586};
587
588struct platform_device tegra_uarta_device = {
589 .name = "tegra_uart",
590 .id = 0,
591 .num_resources = ARRAY_SIZE(tegra_uarta_resources),
592 .resource = tegra_uarta_resources,
593 .dev = {
594 .coherent_dma_mask = DMA_BIT_MASK(32),
595 },
596};
597
598struct platform_device tegra_uartb_device = {
599 .name = "tegra_uart",
600 .id = 1,
601 .num_resources = ARRAY_SIZE(tegra_uartb_resources),
602 .resource = tegra_uartb_resources,
603 .dev = {
604 .coherent_dma_mask = DMA_BIT_MASK(32),
605 },
606};
607
608struct platform_device tegra_uartc_device = {
609 .name = "tegra_uart",
610 .id = 2,
611 .num_resources = ARRAY_SIZE(tegra_uartc_resources),
612 .resource = tegra_uartc_resources,
613 .dev = {
614 .coherent_dma_mask = DMA_BIT_MASK(32),
615 },
616};
617
618struct platform_device tegra_uartd_device = {
619 .name = "tegra_uart",
620 .id = 3,
621 .num_resources = ARRAY_SIZE(tegra_uartd_resources),
622 .resource = tegra_uartd_resources,
623 .dev = {
624 .coherent_dma_mask = DMA_BIT_MASK(32),
625 },
626};
627
628struct platform_device tegra_uarte_device = {
629 .name = "tegra_uart",
630 .id = 4,
631 .num_resources = ARRAY_SIZE(tegra_uarte_resources),
632 .resource = tegra_uarte_resources,
633 .dev = {
634 .coherent_dma_mask = DMA_BIT_MASK(32),
635 },
636};
637
638static struct resource i2s_resource1[] = {
639 [0] = {
640 .start = INT_I2S1,
641 .end = INT_I2S1,
642 .flags = IORESOURCE_IRQ
643 },
644 [1] = {
645 .start = TEGRA_DMA_REQ_SEL_I2S_1,
646 .end = TEGRA_DMA_REQ_SEL_I2S_1,
647 .flags = IORESOURCE_DMA
648 },
649 [2] = {
650 .start = TEGRA_I2S1_BASE,
651 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
652 .flags = IORESOURCE_MEM
653 }
654};
655
656static struct resource i2s_resource2[] = {
657 [0] = {
658 .start = INT_I2S2,
659 .end = INT_I2S2,
660 .flags = IORESOURCE_IRQ
661 },
662 [1] = {
663 .start = TEGRA_DMA_REQ_SEL_I2S2_1,
664 .end = TEGRA_DMA_REQ_SEL_I2S2_1,
665 .flags = IORESOURCE_DMA
666 },
667 [2] = {
668 .start = TEGRA_I2S2_BASE,
669 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
670 .flags = IORESOURCE_MEM
671 }
672};
673
674struct platform_device tegra_i2s_device1 = {
675 .name = "tegra20-i2s",
676 .id = 0,
677 .resource = i2s_resource1,
678 .num_resources = ARRAY_SIZE(i2s_resource1),
679};
680
681struct platform_device tegra_i2s_device2 = {
682 .name = "tegra20-i2s",
683 .id = 1,
684 .resource = i2s_resource2,
685 .num_resources = ARRAY_SIZE(i2s_resource2),
686};
687
688static struct resource tegra_das_resources[] = {
689 [0] = {
690 .start = TEGRA_APB_MISC_DAS_BASE,
691 .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
692 .flags = IORESOURCE_MEM,
693 },
694};
695
696struct platform_device tegra_das_device = {
697 .name = "tegra20-das",
698 .id = -1,
699 .num_resources = ARRAY_SIZE(tegra_das_resources),
700 .resource = tegra_das_resources,
701};
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
deleted file mode 100644
index 4f5052726495..000000000000
--- a/arch/arm/mach-tegra/devices.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef __MACH_TEGRA_DEVICES_H
20#define __MACH_TEGRA_DEVICES_H
21
22#include <linux/platform_device.h>
23#include <linux/platform_data/tegra_usb.h>
24
25#include <mach/usb_phy.h>
26
27extern struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config;
28
29extern struct tegra_ehci_platform_data tegra_ehci1_pdata;
30extern struct tegra_ehci_platform_data tegra_ehci2_pdata;
31extern struct tegra_ehci_platform_data tegra_ehci3_pdata;
32
33extern struct platform_device tegra_gpio_device;
34extern struct platform_device tegra_pinmux_device;
35extern struct platform_device tegra_sdhci_device1;
36extern struct platform_device tegra_sdhci_device2;
37extern struct platform_device tegra_sdhci_device3;
38extern struct platform_device tegra_sdhci_device4;
39extern struct platform_device tegra_i2c_device1;
40extern struct platform_device tegra_i2c_device2;
41extern struct platform_device tegra_i2c_device3;
42extern struct platform_device tegra_i2c_device4;
43extern struct platform_device tegra_spi_device1;
44extern struct platform_device tegra_spi_device2;
45extern struct platform_device tegra_spi_device3;
46extern struct platform_device tegra_spi_device4;
47extern struct platform_device tegra_ehci1_device;
48extern struct platform_device tegra_ehci2_device;
49extern struct platform_device tegra_ehci3_device;
50extern struct platform_device tegra_uarta_device;
51extern struct platform_device tegra_uartb_device;
52extern struct platform_device tegra_uartc_device;
53extern struct platform_device tegra_uartd_device;
54extern struct platform_device tegra_uarte_device;
55extern struct platform_device tegra_pmu_device;
56extern struct platform_device tegra_i2s_device1;
57extern struct platform_device tegra_i2s_device2;
58extern struct platform_device tegra_das_device;
59
60#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
deleted file mode 100644
index a978b3cc3a8d..000000000000
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/gpio.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_TEGRA_GPIO_TEGRA_H
21#define __MACH_TEGRA_GPIO_TEGRA_H
22
23#include <linux/types.h>
24#include <mach/irqs.h>
25
26#define TEGRA_NR_GPIOS INT_GPIO_NR
27
28#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h b/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
deleted file mode 100644
index 1f24d304921e..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinconf-tegra.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * pinctrl configuration definitions for the NVIDIA Tegra pinmux
3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __PINCONF_TEGRA_H__
17#define __PINCONF_TEGRA_H__
18
19enum tegra_pinconf_param {
20 /* argument: tegra_pinconf_pull */
21 TEGRA_PINCONF_PARAM_PULL,
22 /* argument: tegra_pinconf_tristate */
23 TEGRA_PINCONF_PARAM_TRISTATE,
24 /* argument: Boolean */
25 TEGRA_PINCONF_PARAM_ENABLE_INPUT,
26 /* argument: Boolean */
27 TEGRA_PINCONF_PARAM_OPEN_DRAIN,
28 /* argument: Boolean */
29 TEGRA_PINCONF_PARAM_LOCK,
30 /* argument: Boolean */
31 TEGRA_PINCONF_PARAM_IORESET,
32 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
34 /* argument: Boolean */
35 TEGRA_PINCONF_PARAM_SCHMITT,
36 /* argument: Boolean */
37 TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
38 /* argument: Integer, range is HW-dependant */
39 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
40 /* argument: Integer, range is HW-dependant */
41 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
42 /* argument: Integer, range is HW-dependant */
43 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
44 /* argument: Integer, range is HW-dependant */
45 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
46};
47
48enum tegra_pinconf_pull {
49 TEGRA_PINCONFIG_PULL_NONE,
50 TEGRA_PINCONFIG_PULL_DOWN,
51 TEGRA_PINCONFIG_PULL_UP,
52};
53
54enum tegra_pinconf_tristate {
55 TEGRA_PINCONFIG_DRIVEN,
56 TEGRA_PINCONFIG_TRISTATE,
57};
58
59#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
60#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
61#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
62
63#endif
diff --git a/arch/arm/mach-tegra/include/mach/suspend.h b/arch/arm/mach-tegra/include/mach/suspend.h
deleted file mode 100644
index 5af8715d2e1e..000000000000
--- a/arch/arm/mach-tegra/include/mach/suspend.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/suspend.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20
21#ifndef _MACH_TEGRA_SUSPEND_H_
22#define _MACH_TEGRA_SUSPEND_H_
23
24void tegra_pinmux_suspend(void);
25void tegra_irq_suspend(void);
26void tegra_gpio_suspend(void);
27void tegra_clk_suspend(void);
28void tegra_dma_suspend(void);
29void tegra_timer_suspend(void);
30
31void tegra_pinmux_resume(void);
32void tegra_irq_resume(void);
33void tegra_gpio_resume(void);
34void tegra_clk_resume(void);
35void tegra_dma_resume(void);
36void tegra_timer_resume(void);
37
38#endif /* _MACH_TEGRA_SUSPEND_H_ */
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
deleted file mode 100644
index 935ce9f65590..000000000000
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/usb_phy.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __MACH_USB_PHY_H
18#define __MACH_USB_PHY_H
19
20#include <linux/clk.h>
21#include <linux/usb/otg.h>
22
23struct tegra_utmip_config {
24 u8 hssync_start_delay;
25 u8 elastic_limit;
26 u8 idle_wait_delay;
27 u8 term_range_adj;
28 u8 xcvr_setup;
29 u8 xcvr_lsfslew;
30 u8 xcvr_lsrslew;
31};
32
33struct tegra_ulpi_config {
34 int reset_gpio;
35 const char *clk;
36};
37
38enum tegra_usb_phy_port_speed {
39 TEGRA_USB_PHY_PORT_SPEED_FULL = 0,
40 TEGRA_USB_PHY_PORT_SPEED_LOW,
41 TEGRA_USB_PHY_PORT_SPEED_HIGH,
42};
43
44enum tegra_usb_phy_mode {
45 TEGRA_USB_PHY_MODE_DEVICE,
46 TEGRA_USB_PHY_MODE_HOST,
47};
48
49struct tegra_xtal_freq;
50
51struct tegra_usb_phy {
52 int instance;
53 const struct tegra_xtal_freq *freq;
54 void __iomem *regs;
55 void __iomem *pad_regs;
56 struct clk *clk;
57 struct clk *pll_u;
58 struct clk *pad_clk;
59 enum tegra_usb_phy_mode mode;
60 void *config;
61 struct usb_phy *ulpi;
62};
63
64struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
65 void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode);
66
67int tegra_usb_phy_power_on(struct tegra_usb_phy *phy);
68
69void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy);
70
71void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy);
72
73void tegra_usb_phy_power_off(struct tegra_usb_phy *phy);
74
75void tegra_usb_phy_preresume(struct tegra_usb_phy *phy);
76
77void tegra_usb_phy_postresume(struct tegra_usb_phy *phy);
78
79void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
80 enum tegra_usb_phy_port_speed port_speed);
81
82void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy);
83
84void tegra_usb_phy_close(struct tegra_usb_phy *phy);
85
86#endif /* __MACH_USB_PHY_H */
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 3463fb5b79c7..a8dba6489c9b 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -352,17 +352,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
352/* Tegra PCIE requires relaxed ordering */ 352/* Tegra PCIE requires relaxed ordering */
353static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) 353static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev)
354{ 354{
355 u16 val16; 355 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
356 int pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
357
358 if (pos <= 0) {
359 dev_err(&dev->dev, "skipping relaxed ordering fixup\n");
360 return;
361 }
362
363 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &val16);
364 val16 |= PCI_EXP_DEVCTL_RELAX_EN;
365 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, val16);
366} 356}
367DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); 357DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
368 358
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 15d506501ccc..de0662de28a0 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -199,7 +199,9 @@ int __init tegra_powergate_init(void)
199 199
200#ifdef CONFIG_DEBUG_FS 200#ifdef CONFIG_DEBUG_FS
201 201
202static const char * const powergate_name[] = { 202static const char * const *powergate_name;
203
204static const char * const powergate_name_t20[] = {
203 [TEGRA_POWERGATE_CPU] = "cpu", 205 [TEGRA_POWERGATE_CPU] = "cpu",
204 [TEGRA_POWERGATE_3D] = "3d", 206 [TEGRA_POWERGATE_3D] = "3d",
205 [TEGRA_POWERGATE_VENC] = "venc", 207 [TEGRA_POWERGATE_VENC] = "venc",
@@ -209,6 +211,23 @@ static const char * const powergate_name[] = {
209 [TEGRA_POWERGATE_MPE] = "mpe", 211 [TEGRA_POWERGATE_MPE] = "mpe",
210}; 212};
211 213
214static const char * const powergate_name_t30[] = {
215 [TEGRA_POWERGATE_CPU] = "cpu0",
216 [TEGRA_POWERGATE_3D] = "3d0",
217 [TEGRA_POWERGATE_VENC] = "venc",
218 [TEGRA_POWERGATE_VDEC] = "vdec",
219 [TEGRA_POWERGATE_PCIE] = "pcie",
220 [TEGRA_POWERGATE_L2] = "l2",
221 [TEGRA_POWERGATE_MPE] = "mpe",
222 [TEGRA_POWERGATE_HEG] = "heg",
223 [TEGRA_POWERGATE_SATA] = "sata",
224 [TEGRA_POWERGATE_CPU1] = "cpu1",
225 [TEGRA_POWERGATE_CPU2] = "cpu2",
226 [TEGRA_POWERGATE_CPU3] = "cpu3",
227 [TEGRA_POWERGATE_CELP] = "celp",
228 [TEGRA_POWERGATE_3D1] = "3d1",
229};
230
212static int powergate_show(struct seq_file *s, void *data) 231static int powergate_show(struct seq_file *s, void *data)
213{ 232{
214 int i; 233 int i;
@@ -237,14 +256,24 @@ static const struct file_operations powergate_fops = {
237int __init tegra_powergate_debugfs_init(void) 256int __init tegra_powergate_debugfs_init(void)
238{ 257{
239 struct dentry *d; 258 struct dentry *d;
240 int err = -ENOMEM;
241 259
242 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 260 switch (tegra_chip_id) {
243 &powergate_fops); 261 case TEGRA20:
244 if (!d) 262 powergate_name = powergate_name_t20;
245 return -ENOMEM; 263 break;
264 case TEGRA30:
265 powergate_name = powergate_name_t30;
266 break;
267 }
268
269 if (powergate_name) {
270 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
271 &powergate_fops);
272 if (!d)
273 return -ENOMEM;
274 }
246 275
247 return err; 276 return 0;
248} 277}
249 278
250#endif 279#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
index 9273b0dffc66..deb873fb12b6 100644
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -28,7 +28,6 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30#include <mach/iomap.h> 30#include <mach/iomap.h>
31#include <mach/suspend.h>
32 31
33#include "clock.h" 32#include "clock.h"
34#include "fuse.h" 33#include "fuse.h"
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
index e81dcd239c95..cc9b5fd8c3d3 100644
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -28,7 +28,6 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29 29
30#include <mach/iomap.h> 30#include <mach/iomap.h>
31#include <mach/suspend.h>
32 31
33#include "clock.h" 32#include "clock.h"
34#include "fuse.h" 33#include "fuse.h"
@@ -918,14 +917,10 @@ PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX
918PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); 917PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
919PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ 918PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
920PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */ 919PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
921PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); 920PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
922PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); 921PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
923PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); 922PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16); 923PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
925PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
926PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
927PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
928PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
929PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX); 924PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX); 925PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX); 926PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
@@ -990,10 +985,6 @@ static struct clk *tegra_list_clks[] = {
990 &tegra_i2c2, 985 &tegra_i2c2,
991 &tegra_i2c3, 986 &tegra_i2c3,
992 &tegra_dvc, 987 &tegra_dvc,
993 &tegra_i2c1_i2c,
994 &tegra_i2c2_i2c,
995 &tegra_i2c3_i2c,
996 &tegra_dvc_i2c,
997 &tegra_uarta, 988 &tegra_uarta,
998 &tegra_uartb, 989 &tegra_uartb,
999 &tegra_uartc, 990 &tegra_uartc,
@@ -1057,6 +1048,10 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
1057 CLK_DUPLICATE("vde", "tegra-aes", "vde"), 1048 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1058 CLK_DUPLICATE("cclk", NULL, "cpu"), 1049 CLK_DUPLICATE("cclk", NULL, "cpu"),
1059 CLK_DUPLICATE("twd", "smp_twd", NULL), 1050 CLK_DUPLICATE("twd", "smp_twd", NULL),
1051 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1052 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1060}; 1055};
1061 1056
1062#define CLK(dev, con, ck) \ 1057#define CLK(dev, con, ck) \
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
index c10449603df0..d92cb556ae35 100644
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -1071,11 +1071,11 @@ PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX
1071PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); 1071PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1072PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */ 1072PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1073PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */ 1073PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1074PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); 1074PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1075PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); 1075PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1076PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); 1076PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1077PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); 1077PERIPH_CLK(i2c4, "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1078PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB); 1078PERIPH_CLK(i2c5, "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1079PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); 1079PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1080PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); 1080PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1081PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB); 1081PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
@@ -1287,6 +1287,11 @@ struct clk_duplicate tegra_clk_duplicates[] = {
1287 CLK_DUPLICATE("dam1", NULL, "dam1"), 1287 CLK_DUPLICATE("dam1", NULL, "dam1"),
1288 CLK_DUPLICATE("dam2", NULL, "dam2"), 1288 CLK_DUPLICATE("dam2", NULL, "dam2"),
1289 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"), 1289 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1290 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1291 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1292 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1293 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1294 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
1290}; 1295};
1291 1296
1292struct clk *tegra_ptr_clks[] = { 1297struct clk *tegra_ptr_clks[] = {
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 57b5bdc13b9b..eccdce983043 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -33,7 +33,6 @@
33 33
34#include <mach/iomap.h> 34#include <mach/iomap.h>
35#include <mach/irqs.h> 35#include <mach/irqs.h>
36#include <mach/suspend.h>
37 36
38#include "board.h" 37#include "board.h"
39#include "clock.h" 38#include "clock.h"
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
deleted file mode 100644
index 022b33a05c3a..000000000000
--- a/arch/arm/mach-tegra/usb_phy.c
+++ /dev/null
@@ -1,817 +0,0 @@
1/*
2 * arch/arm/mach-tegra/usb_phy.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/resource.h>
22#include <linux/delay.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/export.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/of_gpio.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <asm/mach-types.h>
33#include <mach/gpio-tegra.h>
34#include <mach/usb_phy.h>
35#include <mach/iomap.h>
36
37#define ULPI_VIEWPORT 0x170
38
39#define USB_PORTSC1 0x184
40#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
41#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
42#define USB_PORTSC1_PHCD (1 << 23)
43#define USB_PORTSC1_WKOC (1 << 22)
44#define USB_PORTSC1_WKDS (1 << 21)
45#define USB_PORTSC1_WKCN (1 << 20)
46#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
47#define USB_PORTSC1_PP (1 << 12)
48#define USB_PORTSC1_SUSP (1 << 7)
49#define USB_PORTSC1_PE (1 << 2)
50#define USB_PORTSC1_CCS (1 << 0)
51
52#define USB_SUSP_CTRL 0x400
53#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
54#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
55#define USB_SUSP_CLR (1 << 5)
56#define USB_PHY_CLK_VALID (1 << 7)
57#define UTMIP_RESET (1 << 11)
58#define UHSIC_RESET (1 << 11)
59#define UTMIP_PHY_ENABLE (1 << 12)
60#define ULPI_PHY_ENABLE (1 << 13)
61#define USB_SUSP_SET (1 << 14)
62#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
63
64#define USB1_LEGACY_CTRL 0x410
65#define USB1_NO_LEGACY_MODE (1 << 0)
66#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
67#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
68#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
69 (1 << 1)
70#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
71#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
72
73#define ULPI_TIMING_CTRL_0 0x424
74#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
75#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
76
77#define ULPI_TIMING_CTRL_1 0x428
78#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
79#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
80#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
81#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
82#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
83#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
84
85#define UTMIP_PLL_CFG1 0x804
86#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
87#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
88
89#define UTMIP_XCVR_CFG0 0x808
90#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
91#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
92#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
93#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
94#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
95#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
96#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
97
98#define UTMIP_BIAS_CFG0 0x80c
99#define UTMIP_OTGPD (1 << 11)
100#define UTMIP_BIASPD (1 << 10)
101
102#define UTMIP_HSRX_CFG0 0x810
103#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
105
106#define UTMIP_HSRX_CFG1 0x814
107#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
108
109#define UTMIP_TX_CFG0 0x820
110#define UTMIP_FS_PREABMLE_J (1 << 19)
111#define UTMIP_HS_DISCON_DISABLE (1 << 8)
112
113#define UTMIP_MISC_CFG0 0x824
114#define UTMIP_DPDM_OBSERVE (1 << 26)
115#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
121
122#define UTMIP_MISC_CFG1 0x828
123#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
125
126#define UTMIP_DEBOUNCE_CFG0 0x82c
127#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
128
129#define UTMIP_BAT_CHRG_CFG0 0x830
130#define UTMIP_PD_CHRG (1 << 0)
131
132#define UTMIP_SPARE_CFG0 0x834
133#define FUSE_SETUP_SEL (1 << 3)
134
135#define UTMIP_XCVR_CFG1 0x838
136#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
140
141#define UTMIP_BIAS_CFG1 0x83c
142#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
143
144static DEFINE_SPINLOCK(utmip_pad_lock);
145static int utmip_pad_count;
146
147struct tegra_xtal_freq {
148 int freq;
149 u8 enable_delay;
150 u8 stable_count;
151 u8 active_delay;
152 u8 xtal_freq_count;
153 u16 debounce;
154};
155
156static const struct tegra_xtal_freq tegra_freq_table[] = {
157 {
158 .freq = 12000000,
159 .enable_delay = 0x02,
160 .stable_count = 0x2F,
161 .active_delay = 0x04,
162 .xtal_freq_count = 0x76,
163 .debounce = 0x7530,
164 },
165 {
166 .freq = 13000000,
167 .enable_delay = 0x02,
168 .stable_count = 0x33,
169 .active_delay = 0x05,
170 .xtal_freq_count = 0x7F,
171 .debounce = 0x7EF4,
172 },
173 {
174 .freq = 19200000,
175 .enable_delay = 0x03,
176 .stable_count = 0x4B,
177 .active_delay = 0x06,
178 .xtal_freq_count = 0xBB,
179 .debounce = 0xBB80,
180 },
181 {
182 .freq = 26000000,
183 .enable_delay = 0x04,
184 .stable_count = 0x66,
185 .active_delay = 0x09,
186 .xtal_freq_count = 0xFE,
187 .debounce = 0xFDE8,
188 },
189};
190
191static struct tegra_utmip_config utmip_default[] = {
192 [0] = {
193 .hssync_start_delay = 9,
194 .idle_wait_delay = 17,
195 .elastic_limit = 16,
196 .term_range_adj = 6,
197 .xcvr_setup = 9,
198 .xcvr_lsfslew = 1,
199 .xcvr_lsrslew = 1,
200 },
201 [2] = {
202 .hssync_start_delay = 9,
203 .idle_wait_delay = 17,
204 .elastic_limit = 16,
205 .term_range_adj = 6,
206 .xcvr_setup = 9,
207 .xcvr_lsfslew = 2,
208 .xcvr_lsrslew = 2,
209 },
210};
211
212static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
213{
214 return (phy->instance == 1);
215}
216
217static int utmip_pad_open(struct tegra_usb_phy *phy)
218{
219 phy->pad_clk = clk_get_sys("utmip-pad", NULL);
220 if (IS_ERR(phy->pad_clk)) {
221 pr_err("%s: can't get utmip pad clock\n", __func__);
222 return PTR_ERR(phy->pad_clk);
223 }
224
225 if (phy->instance == 0) {
226 phy->pad_regs = phy->regs;
227 } else {
228 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
229 if (!phy->pad_regs) {
230 pr_err("%s: can't remap usb registers\n", __func__);
231 clk_put(phy->pad_clk);
232 return -ENOMEM;
233 }
234 }
235 return 0;
236}
237
238static void utmip_pad_close(struct tegra_usb_phy *phy)
239{
240 if (phy->instance != 0)
241 iounmap(phy->pad_regs);
242 clk_put(phy->pad_clk);
243}
244
245static void utmip_pad_power_on(struct tegra_usb_phy *phy)
246{
247 unsigned long val, flags;
248 void __iomem *base = phy->pad_regs;
249
250 clk_prepare_enable(phy->pad_clk);
251
252 spin_lock_irqsave(&utmip_pad_lock, flags);
253
254 if (utmip_pad_count++ == 0) {
255 val = readl(base + UTMIP_BIAS_CFG0);
256 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
257 writel(val, base + UTMIP_BIAS_CFG0);
258 }
259
260 spin_unlock_irqrestore(&utmip_pad_lock, flags);
261
262 clk_disable_unprepare(phy->pad_clk);
263}
264
265static int utmip_pad_power_off(struct tegra_usb_phy *phy)
266{
267 unsigned long val, flags;
268 void __iomem *base = phy->pad_regs;
269
270 if (!utmip_pad_count) {
271 pr_err("%s: utmip pad already powered off\n", __func__);
272 return -EINVAL;
273 }
274
275 clk_prepare_enable(phy->pad_clk);
276
277 spin_lock_irqsave(&utmip_pad_lock, flags);
278
279 if (--utmip_pad_count == 0) {
280 val = readl(base + UTMIP_BIAS_CFG0);
281 val |= UTMIP_OTGPD | UTMIP_BIASPD;
282 writel(val, base + UTMIP_BIAS_CFG0);
283 }
284
285 spin_unlock_irqrestore(&utmip_pad_lock, flags);
286
287 clk_disable_unprepare(phy->pad_clk);
288
289 return 0;
290}
291
292static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
293{
294 unsigned long timeout = 2000;
295 do {
296 if ((readl(reg) & mask) == result)
297 return 0;
298 udelay(1);
299 timeout--;
300 } while (timeout);
301 return -1;
302}
303
304static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
305{
306 unsigned long val;
307 void __iomem *base = phy->regs;
308
309 if (phy->instance == 0) {
310 val = readl(base + USB_SUSP_CTRL);
311 val |= USB_SUSP_SET;
312 writel(val, base + USB_SUSP_CTRL);
313
314 udelay(10);
315
316 val = readl(base + USB_SUSP_CTRL);
317 val &= ~USB_SUSP_SET;
318 writel(val, base + USB_SUSP_CTRL);
319 }
320
321 if (phy->instance == 2) {
322 val = readl(base + USB_PORTSC1);
323 val |= USB_PORTSC1_PHCD;
324 writel(val, base + USB_PORTSC1);
325 }
326
327 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
328 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
329}
330
331static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
332{
333 unsigned long val;
334 void __iomem *base = phy->regs;
335
336 if (phy->instance == 0) {
337 val = readl(base + USB_SUSP_CTRL);
338 val |= USB_SUSP_CLR;
339 writel(val, base + USB_SUSP_CTRL);
340
341 udelay(10);
342
343 val = readl(base + USB_SUSP_CTRL);
344 val &= ~USB_SUSP_CLR;
345 writel(val, base + USB_SUSP_CTRL);
346 }
347
348 if (phy->instance == 2) {
349 val = readl(base + USB_PORTSC1);
350 val &= ~USB_PORTSC1_PHCD;
351 writel(val, base + USB_PORTSC1);
352 }
353
354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
355 USB_PHY_CLK_VALID))
356 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
357}
358
359static int utmi_phy_power_on(struct tegra_usb_phy *phy)
360{
361 unsigned long val;
362 void __iomem *base = phy->regs;
363 struct tegra_utmip_config *config = phy->config;
364
365 val = readl(base + USB_SUSP_CTRL);
366 val |= UTMIP_RESET;
367 writel(val, base + USB_SUSP_CTRL);
368
369 if (phy->instance == 0) {
370 val = readl(base + USB1_LEGACY_CTRL);
371 val |= USB1_NO_LEGACY_MODE;
372 writel(val, base + USB1_LEGACY_CTRL);
373 }
374
375 val = readl(base + UTMIP_TX_CFG0);
376 val &= ~UTMIP_FS_PREABMLE_J;
377 writel(val, base + UTMIP_TX_CFG0);
378
379 val = readl(base + UTMIP_HSRX_CFG0);
380 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
381 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
382 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
383 writel(val, base + UTMIP_HSRX_CFG0);
384
385 val = readl(base + UTMIP_HSRX_CFG1);
386 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
387 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
388 writel(val, base + UTMIP_HSRX_CFG1);
389
390 val = readl(base + UTMIP_DEBOUNCE_CFG0);
391 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
392 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
393 writel(val, base + UTMIP_DEBOUNCE_CFG0);
394
395 val = readl(base + UTMIP_MISC_CFG0);
396 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
397 writel(val, base + UTMIP_MISC_CFG0);
398
399 val = readl(base + UTMIP_MISC_CFG1);
400 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
401 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
402 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
403 writel(val, base + UTMIP_MISC_CFG1);
404
405 val = readl(base + UTMIP_PLL_CFG1);
406 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
407 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
408 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
409 writel(val, base + UTMIP_PLL_CFG1);
410
411 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
412 val = readl(base + USB_SUSP_CTRL);
413 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
414 writel(val, base + USB_SUSP_CTRL);
415 }
416
417 utmip_pad_power_on(phy);
418
419 val = readl(base + UTMIP_XCVR_CFG0);
420 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
421 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
422 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
423 UTMIP_XCVR_HSSLEW_MSB(~0));
424 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
425 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
426 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
427 writel(val, base + UTMIP_XCVR_CFG0);
428
429 val = readl(base + UTMIP_XCVR_CFG1);
430 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
431 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
432 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
433 writel(val, base + UTMIP_XCVR_CFG1);
434
435 val = readl(base + UTMIP_BAT_CHRG_CFG0);
436 val &= ~UTMIP_PD_CHRG;
437 writel(val, base + UTMIP_BAT_CHRG_CFG0);
438
439 val = readl(base + UTMIP_BIAS_CFG1);
440 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
441 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
442 writel(val, base + UTMIP_BIAS_CFG1);
443
444 if (phy->instance == 0) {
445 val = readl(base + UTMIP_SPARE_CFG0);
446 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
447 val &= ~FUSE_SETUP_SEL;
448 else
449 val |= FUSE_SETUP_SEL;
450 writel(val, base + UTMIP_SPARE_CFG0);
451 }
452
453 if (phy->instance == 2) {
454 val = readl(base + USB_SUSP_CTRL);
455 val |= UTMIP_PHY_ENABLE;
456 writel(val, base + USB_SUSP_CTRL);
457 }
458
459 val = readl(base + USB_SUSP_CTRL);
460 val &= ~UTMIP_RESET;
461 writel(val, base + USB_SUSP_CTRL);
462
463 if (phy->instance == 0) {
464 val = readl(base + USB1_LEGACY_CTRL);
465 val &= ~USB1_VBUS_SENSE_CTL_MASK;
466 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
467 writel(val, base + USB1_LEGACY_CTRL);
468
469 val = readl(base + USB_SUSP_CTRL);
470 val &= ~USB_SUSP_SET;
471 writel(val, base + USB_SUSP_CTRL);
472 }
473
474 utmi_phy_clk_enable(phy);
475
476 if (phy->instance == 2) {
477 val = readl(base + USB_PORTSC1);
478 val &= ~USB_PORTSC1_PTS(~0);
479 writel(val, base + USB_PORTSC1);
480 }
481
482 return 0;
483}
484
485static void utmi_phy_power_off(struct tegra_usb_phy *phy)
486{
487 unsigned long val;
488 void __iomem *base = phy->regs;
489
490 utmi_phy_clk_disable(phy);
491
492 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
493 val = readl(base + USB_SUSP_CTRL);
494 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
495 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
496 writel(val, base + USB_SUSP_CTRL);
497 }
498
499 val = readl(base + USB_SUSP_CTRL);
500 val |= UTMIP_RESET;
501 writel(val, base + USB_SUSP_CTRL);
502
503 val = readl(base + UTMIP_BAT_CHRG_CFG0);
504 val |= UTMIP_PD_CHRG;
505 writel(val, base + UTMIP_BAT_CHRG_CFG0);
506
507 val = readl(base + UTMIP_XCVR_CFG0);
508 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
509 UTMIP_FORCE_PDZI_POWERDOWN;
510 writel(val, base + UTMIP_XCVR_CFG0);
511
512 val = readl(base + UTMIP_XCVR_CFG1);
513 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
514 UTMIP_FORCE_PDDR_POWERDOWN;
515 writel(val, base + UTMIP_XCVR_CFG1);
516
517 utmip_pad_power_off(phy);
518}
519
520static void utmi_phy_preresume(struct tegra_usb_phy *phy)
521{
522 unsigned long val;
523 void __iomem *base = phy->regs;
524
525 val = readl(base + UTMIP_TX_CFG0);
526 val |= UTMIP_HS_DISCON_DISABLE;
527 writel(val, base + UTMIP_TX_CFG0);
528}
529
530static void utmi_phy_postresume(struct tegra_usb_phy *phy)
531{
532 unsigned long val;
533 void __iomem *base = phy->regs;
534
535 val = readl(base + UTMIP_TX_CFG0);
536 val &= ~UTMIP_HS_DISCON_DISABLE;
537 writel(val, base + UTMIP_TX_CFG0);
538}
539
540static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
541 enum tegra_usb_phy_port_speed port_speed)
542{
543 unsigned long val;
544 void __iomem *base = phy->regs;
545
546 val = readl(base + UTMIP_MISC_CFG0);
547 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
548 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
549 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
550 else
551 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
552 writel(val, base + UTMIP_MISC_CFG0);
553 udelay(1);
554
555 val = readl(base + UTMIP_MISC_CFG0);
556 val |= UTMIP_DPDM_OBSERVE;
557 writel(val, base + UTMIP_MISC_CFG0);
558 udelay(10);
559}
560
561static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
562{
563 unsigned long val;
564 void __iomem *base = phy->regs;
565
566 val = readl(base + UTMIP_MISC_CFG0);
567 val &= ~UTMIP_DPDM_OBSERVE;
568 writel(val, base + UTMIP_MISC_CFG0);
569 udelay(10);
570}
571
572static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
573{
574 int ret;
575 unsigned long val;
576 void __iomem *base = phy->regs;
577 struct tegra_ulpi_config *config = phy->config;
578
579 gpio_direction_output(config->reset_gpio, 0);
580 msleep(5);
581 gpio_direction_output(config->reset_gpio, 1);
582
583 clk_prepare_enable(phy->clk);
584 msleep(1);
585
586 val = readl(base + USB_SUSP_CTRL);
587 val |= UHSIC_RESET;
588 writel(val, base + USB_SUSP_CTRL);
589
590 val = readl(base + ULPI_TIMING_CTRL_0);
591 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
592 writel(val, base + ULPI_TIMING_CTRL_0);
593
594 val = readl(base + USB_SUSP_CTRL);
595 val |= ULPI_PHY_ENABLE;
596 writel(val, base + USB_SUSP_CTRL);
597
598 val = 0;
599 writel(val, base + ULPI_TIMING_CTRL_1);
600
601 val |= ULPI_DATA_TRIMMER_SEL(4);
602 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
603 val |= ULPI_DIR_TRIMMER_SEL(4);
604 writel(val, base + ULPI_TIMING_CTRL_1);
605 udelay(10);
606
607 val |= ULPI_DATA_TRIMMER_LOAD;
608 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
609 val |= ULPI_DIR_TRIMMER_LOAD;
610 writel(val, base + ULPI_TIMING_CTRL_1);
611
612 /* Fix VbusInvalid due to floating VBUS */
613 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
614 if (ret) {
615 pr_err("%s: ulpi write failed\n", __func__);
616 return ret;
617 }
618
619 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
620 if (ret) {
621 pr_err("%s: ulpi write failed\n", __func__);
622 return ret;
623 }
624
625 val = readl(base + USB_PORTSC1);
626 val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
627 writel(val, base + USB_PORTSC1);
628
629 val = readl(base + USB_SUSP_CTRL);
630 val |= USB_SUSP_CLR;
631 writel(val, base + USB_SUSP_CTRL);
632 udelay(100);
633
634 val = readl(base + USB_SUSP_CTRL);
635 val &= ~USB_SUSP_CLR;
636 writel(val, base + USB_SUSP_CTRL);
637
638 return 0;
639}
640
641static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
642{
643 unsigned long val;
644 void __iomem *base = phy->regs;
645 struct tegra_ulpi_config *config = phy->config;
646
647 /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
648 * Controller to immediately bring the ULPI PHY out of low power
649 */
650 val = readl(base + USB_PORTSC1);
651 val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
652 writel(val, base + USB_PORTSC1);
653
654 gpio_direction_output(config->reset_gpio, 0);
655 clk_disable(phy->clk);
656}
657
658struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
659 void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
660{
661 struct tegra_usb_phy *phy;
662 struct tegra_ulpi_config *ulpi_config;
663 unsigned long parent_rate;
664 int i;
665 int err;
666
667 phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
668 if (!phy)
669 return ERR_PTR(-ENOMEM);
670
671 phy->instance = instance;
672 phy->regs = regs;
673 phy->config = config;
674 phy->mode = phy_mode;
675
676 if (!phy->config) {
677 if (phy_is_ulpi(phy)) {
678 pr_err("%s: ulpi phy configuration missing", __func__);
679 err = -EINVAL;
680 goto err0;
681 } else {
682 phy->config = &utmip_default[instance];
683 }
684 }
685
686 phy->pll_u = clk_get_sys(NULL, "pll_u");
687 if (IS_ERR(phy->pll_u)) {
688 pr_err("Can't get pll_u clock\n");
689 err = PTR_ERR(phy->pll_u);
690 goto err0;
691 }
692 clk_prepare_enable(phy->pll_u);
693
694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
696 if (tegra_freq_table[i].freq == parent_rate) {
697 phy->freq = &tegra_freq_table[i];
698 break;
699 }
700 }
701 if (!phy->freq) {
702 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
703 err = -EINVAL;
704 goto err1;
705 }
706
707 if (phy_is_ulpi(phy)) {
708 ulpi_config = config;
709 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
710 if (IS_ERR(phy->clk)) {
711 pr_err("%s: can't get ulpi clock\n", __func__);
712 err = -ENXIO;
713 goto err1;
714 }
715 if (!gpio_is_valid(ulpi_config->reset_gpio))
716 ulpi_config->reset_gpio =
717 of_get_named_gpio(dev->of_node,
718 "nvidia,phy-reset-gpio", 0);
719 if (!gpio_is_valid(ulpi_config->reset_gpio)) {
720 pr_err("%s: invalid reset gpio: %d\n", __func__,
721 ulpi_config->reset_gpio);
722 err = -EINVAL;
723 goto err1;
724 }
725 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
726 gpio_direction_output(ulpi_config->reset_gpio, 0);
727 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
728 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
729 } else {
730 err = utmip_pad_open(phy);
731 if (err < 0)
732 goto err1;
733 }
734
735 return phy;
736
737err1:
738 clk_disable_unprepare(phy->pll_u);
739 clk_put(phy->pll_u);
740err0:
741 kfree(phy);
742 return ERR_PTR(err);
743}
744EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
745
746int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
747{
748 if (phy_is_ulpi(phy))
749 return ulpi_phy_power_on(phy);
750 else
751 return utmi_phy_power_on(phy);
752}
753EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
754
755void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
756{
757 if (phy_is_ulpi(phy))
758 ulpi_phy_power_off(phy);
759 else
760 utmi_phy_power_off(phy);
761}
762EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
763
764void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
765{
766 if (!phy_is_ulpi(phy))
767 utmi_phy_preresume(phy);
768}
769EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
770
771void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
772{
773 if (!phy_is_ulpi(phy))
774 utmi_phy_postresume(phy);
775}
776EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
777
778void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
779 enum tegra_usb_phy_port_speed port_speed)
780{
781 if (!phy_is_ulpi(phy))
782 utmi_phy_restore_start(phy, port_speed);
783}
784EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
785
786void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
787{
788 if (!phy_is_ulpi(phy))
789 utmi_phy_restore_end(phy);
790}
791EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
792
793void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
794{
795 if (!phy_is_ulpi(phy))
796 utmi_phy_clk_disable(phy);
797}
798EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
799
800void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
801{
802 if (!phy_is_ulpi(phy))
803 utmi_phy_clk_enable(phy);
804}
805EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
806
807void tegra_usb_phy_close(struct tegra_usb_phy *phy)
808{
809 if (phy_is_ulpi(phy))
810 clk_put(phy->clk);
811 else
812 utmip_pad_close(phy);
813 clk_disable_unprepare(phy->pll_u);
814 clk_put(phy->pll_u);
815 kfree(phy);
816}
817EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 21:23:09 -0500