15 files changed, 532 insertions, 64 deletions

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c1970005f805..b78f0d71b328 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f0315c95c76d..eb1f3c8c74cc 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
+#include "irq.h"
 #include "pmc.h"
 #include "apbio.h"
 #include "sleep.h"
@@ -61,8 +62,10 @@ u32 tegra_uart_config[4] = {
 void __init tegra_dt_init_irq(void)
 {
         tegra_clocks_init();
+        tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
+        tegra_legacy_irq_syscore_init();
 }
 #endif
 
@@ -100,12 +103,12 @@ void __init tegra_init_early(void)
         tegra_apb_io_init();
         tegra_init_fuse();
         tegra_init_cache();
-        tegra_pmc_init();
         tegra_powergate_init();
         tegra_hotplug_init();
 }
 
 void __init tegra_init_late(void)
 {
+        tegra_init_suspend();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 590ec25855dd..0cdba8de8c77 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -131,10 +131,6 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         while (tegra20_cpu_is_resettable_soon())
                 cpu_relax();
 
@@ -143,7 +139,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 9387daeeadc8..3cf9aca5f3ea 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -69,10 +69,6 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
                                            struct cpuidle_driver *drv,
                                            int index)
 {
-        struct cpuidle_state *state = &drv->states[index];
-        u32 cpu_on_time = state->exit_latency;
-        u32 cpu_off_time = state->target_residency - state->exit_latency;
-
         /* All CPUs entering LP2 is not working.
          * Don't let CPU0 enter LP2 when any secondary CPU is online.
          */
@@ -83,7 +79,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
 
-        tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
+        tegra_idle_lp2_last();
 
         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
 
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f7db0782a6b6..e035cd284a6e 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -2,6 +2,7 @@
  * arch/arm/mach-tegra/fuse.c
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -137,6 +138,9 @@ void tegra_init_fuse(void)
                 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
                 tegra_init_speedo_data = &tegra30_init_speedo_data;
                 break;
+        case TEGRA114:
+                tegra_init_speedo_data = &tegra114_init_speedo_data;
+                break;
         default:
                 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
                 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index da78434678c7..aacc00d05980 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * Author:
  *      Colin Cross <ccross@android.com>
@@ -66,4 +67,10 @@ void tegra30_init_speedo_data(void);
 static inline void tegra30_init_speedo_data(void) {}
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+void tegra114_init_speedo_data(void);
+#else
+static inline void tegra114_init_speedo_data(void) {}
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 1952e82797cc..0de4eed1493d 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -4,7 +4,7 @@
  * Author:
  *      Colin Cross <ccross@android.com>
  *
- * Copyright (C) 2010, NVIDIA Corporation
+ * Copyright (C) 2010,2013, NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/syscore_ops.h>
 
 #include "board.h"
 #include "iomap.h"
@@ -43,6 +44,7 @@
 #define ICTLR_COP_IEP_CLASS     0x3c
 
 #define FIRST_LEGACY_IRQ 32
+#define TEGRA_MAX_NUM_ICTLRS    5
 
 #define SGI_MASK 0xFFFF
 
@@ -56,6 +58,15 @@ static void __iomem *ictlr_reg_base[] = {
         IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE),
 };
 
+#ifdef CONFIG_PM_SLEEP
+static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
+static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
+
+static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
+#endif
+
 bool tegra_pending_sgi(void)
 {
         u32 pending_set;
@@ -125,6 +136,87 @@ static int tegra_retrigger(struct irq_data *d)
         return 1;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int tegra_set_wake(struct irq_data *d, unsigned int enable)
+{
+        u32 irq = d->irq;
+        u32 index, mask;
+
+        if (irq < FIRST_LEGACY_IRQ ||
+                irq >= FIRST_LEGACY_IRQ + num_ictlrs * 32)
+                return -EINVAL;
+
+        index = ((irq - FIRST_LEGACY_IRQ) / 32);
+        mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
+        if (enable)
+                ictlr_wake_mask[index] |= mask;
+        else
+                ictlr_wake_mask[index] &= ~mask;
+
+        return 0;
+}
+
+static int tegra_legacy_irq_suspend(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                /* Save interrupt state */
+                cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
+                cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
+                cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
+                cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
+
+                /* Disable COP interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+
+                /* Disable CPU interrupts */
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+
+                /* Enable the wakeup sources of ictlr */
+                writel_relaxed(ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
+        }
+        local_irq_restore(flags);
+
+        return 0;
+}
+
+static void tegra_legacy_irq_resume(void)
+{
+        unsigned long flags;
+        int i;
+
+        local_irq_save(flags);
+        for (i = 0; i < num_ictlrs; i++) {
+                void __iomem *ictlr = ictlr_reg_base[i];
+                writel_relaxed(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+                writel_relaxed(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
+                writel_relaxed(cop_iep[i], ictlr + ICTLR_COP_IEP_CLASS);
+                writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+                writel_relaxed(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
+        }
+        local_irq_restore(flags);
+}
+
+static struct syscore_ops tegra_legacy_irq_syscore_ops = {
+        .suspend = tegra_legacy_irq_suspend,
+        .resume = tegra_legacy_irq_resume,
+};
+
+int tegra_legacy_irq_syscore_init(void)
+{
+        register_syscore_ops(&tegra_legacy_irq_syscore_ops);
+
+        return 0;
+}
+#else
+#define tegra_set_wake NULL
+#endif
+
 void __init tegra_init_irq(void)
 {
         int i;
@@ -150,6 +242,8 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_mask = tegra_mask;
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
+        gic_arch_extn.irq_set_wake = tegra_set_wake;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND;
 
         /*
          * Check if there is a devicetree present, since the GIC will be
diff --git a/arch/arm/mach-tegra/irq.h b/arch/arm/mach-tegra/irq.h
index 5142649bba05..bc05ce5613fb 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/arch/arm/mach-tegra/irq.h
@@ -19,4 +19,10 @@
 
 bool tegra_pending_sgi(void);
 
+#ifdef CONFIG_PM_SLEEP
+int tegra_legacy_irq_syscore_init(void);
+#else
+static inline int tegra_legacy_irq_syscore_init(void) { return 0; }
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index c31db797e199..0c4963bd4b44 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -138,6 +138,12 @@ remove_clamps:
         return 0;
 }
 
+static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        cpu = cpu_logical_map(cpu);
+        return tegra_pmc_cpu_power_on(cpu);
+}
+
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
                                           struct task_struct *idle)
 {
@@ -145,6 +151,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu,
                 return tegra20_boot_secondary(cpu, idle);
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
                 return tegra30_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                return tegra114_boot_secondary(cpu, idle);
 
         return -EINVAL;
 }
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 891fb70d0aa7..45cf52c7e528 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -22,7 +22,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/cpu_pm.h>
-#include <linux/clk.h>
+#include <linux/suspend.h>
 #include <linux/err.h>
 #include <linux/clk/tegra.h>
 
@@ -37,52 +37,13 @@
 #include "reset.h"
 #include "flowctrl.h"
 #include "fuse.h"
+#include "pmc.h"
 #include "sleep.h"
 
-#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
-
-#define PMC_CTRL                0x0
-#define PMC_CPUPWRGOOD_TIMER    0xc8
-#define PMC_CPUPWROFF_TIMER     0xcc
-
 #ifdef CONFIG_PM_SLEEP
 static DEFINE_SPINLOCK(tegra_lp2_lock);
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
-static struct clk *tegra_pclk;
 void (*tegra_tear_down_cpu)(void);
 
-static void set_power_timers(unsigned long us_on, unsigned long us_off)
-{
-        unsigned long long ticks;
-        unsigned long long pclk;
-        unsigned long rate;
-        static unsigned long tegra_last_pclk;
-
-        if (tegra_pclk == NULL) {
-                tegra_pclk = clk_get_sys(NULL, "pclk");
-                WARN_ON(IS_ERR(tegra_pclk));
-        }
-
-        rate = clk_get_rate(tegra_pclk);
-
-        if (WARN_ON_ONCE(rate <= 0))
-                pclk = 100000000;
-        else
-                pclk = rate;
-
-        if ((rate != tegra_last_pclk)) {
-                ticks = (us_on * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
-
-                ticks = (us_off * pclk) + 999999ull;
-                do_div(ticks, 1000000);
-                writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
-                wmb();
-        }
-        tegra_last_pclk = pclk;
-}
-
 /*
  * restore_cpu_complex
  *
@@ -178,16 +139,9 @@ static int tegra_sleep_cpu(unsigned long v2p)
         return 0;
 }
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
+void tegra_idle_lp2_last(void)
 {
-        u32 mode;
-
-        /* Only the last cpu down does the final suspend steps */
-        mode = readl(pmc + PMC_CTRL);
-        mode |= TEGRA_POWER_CPU_PWRREQ_OE;
-        writel(mode, pmc + PMC_CTRL);
-
-        set_power_timers(cpu_on_time, cpu_off_time);
+        tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
 
         cpu_cluster_pm_enter();
         suspend_cpu_complex();
@@ -197,4 +151,81 @@ void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
+
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        /* Tegra114 didn't support any suspending mode yet. */
+        if (tegra_chip_id == TEGRA114)
+                return TEGRA_SUSPEND_NONE;
+
+        /*
+         * The Tegra devices only support suspending to LP2 currently.
+         */
+        if (mode > TEGRA_SUSPEND_LP2)
+                return TEGRA_SUSPEND_LP2;
+
+        return mode;
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+        [TEGRA_SUSPEND_NONE] = "none",
+        [TEGRA_SUSPEND_LP2] = "LP2",
+        [TEGRA_SUSPEND_LP1] = "LP1",
+        [TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int __cpuinit tegra_suspend_enter(suspend_state_t state)
+{
+        enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
+
+        if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
+                    mode >= TEGRA_MAX_SUSPEND_MODE))
+                return -EINVAL;
+
+        pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+        tegra_pmc_pm_set(mode);
+
+        local_fiq_disable();
+
+        suspend_cpu_complex();
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_set_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+
+        cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                tegra_clear_cpu_in_lp2(0);
+                break;
+        default:
+                break;
+        }
+        restore_cpu_complex();
+
+        local_fiq_enable();
+
+        return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+        .valid          = suspend_valid_only_mem,
+        .enter          = tegra_suspend_enter,
+};
+
+void __init tegra_init_suspend(void)
+{
+        if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
+                return;
+
+        tegra_pmc_suspend_init();
+
+        suspend_set_ops(&tegra_suspend_ops);
+}
 #endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 787335cc964c..778a4aa7c3fa 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -21,6 +21,8 @@
 #ifndef _MACH_TEGRA_PM_H_
 #define _MACH_TEGRA_PM_H_
 
+#include "pmc.h"
+
 extern unsigned long l2x0_saved_regs_addr;
 
 void save_cpu_arch_register(void);
@@ -29,7 +31,20 @@ void restore_cpu_arch_register(void);
 void tegra_clear_cpu_in_lp2(int phy_cpu_id);
 bool tegra_set_cpu_in_lp2(int phy_cpu_id);
 
-void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
+void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
 
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode);
+void tegra_init_suspend(void);
+#else
+static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
+                                enum tegra_suspend_mode mode)
+{
+        return TEGRA_SUSPEND_NONE;
+}
+static inline void tegra_init_suspend(void) {}
+#endif
+
 #endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index b30e921cc3a9..32360e540ce6 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -16,10 +16,20 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 
+#include "fuse.h"
+#include "pm.h"
+#include "pmc.h"
+#include "sleep.h"
+
+#define TEGRA_POWER_EFFECT_LP0          (1 << 14)  /* LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU pwr req polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE       (1 << 16)  /* CPU pwr req enable */
+
 #define PMC_CTRL                        0x0
 #define PMC_CTRL_INTR_LOW               (1 << 17)
 #define PMC_PWRGATE_TOGGLE              0x30
@@ -27,6 +37,9 @@
 #define PMC_REMOVE_CLAMPING             0x34
 #define PMC_PWRGATE_STATUS              0x38
 
+#define PMC_CPUPWRGOOD_TIMER    0xc8
+#define PMC_CPUPWROFF_TIMER     0xcc
+
 #define TEGRA_POWERGATE_PCIE    3
 #define TEGRA_POWERGATE_VDEC    4
 #define TEGRA_POWERGATE_CPU1    9
@@ -43,6 +56,23 @@ static DEFINE_SPINLOCK(tegra_powergate_lock);
 
 static void __iomem *tegra_pmc_base;
 static bool tegra_pmc_invert_interrupt;
+static struct clk *tegra_pclk;
+
+struct pmc_pm_data {
+        u32 cpu_good_time;      /* CPU power good time in uS */
+        u32 cpu_off_time;       /* CPU power off time in uS */
+        u32 core_osc_time;      /* Core power good osc time in uS */
+        u32 core_pmu_time;      /* Core power good pmu time in uS */
+        u32 core_off_time;      /* Core power off time in uS */
+        bool corereq_high;      /* Core power request active-high */
+        bool sysclkreq_high;    /* System clock request active-high */
+        bool combined_req;      /* Combined pwr req for CPU & Core */
+        bool cpu_pwr_good_en;   /* CPU power good signal is enabled */
+        u32 lp0_vec_phy_addr;   /* The phy addr of LP0 warm boot code */
+        u32 lp0_vec_size;       /* The size of LP0 warm boot code */
+        enum tegra_suspend_mode suspend_mode;
+};
+static struct pmc_pm_data pmc_pm_data;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
@@ -133,6 +163,70 @@ int tegra_pmc_cpu_remove_clamping(int cpuid)
         return tegra_pmc_powergate_remove_clamping(id);
 }
 
+#ifdef CONFIG_PM_SLEEP
+static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate)
+{
+        unsigned long long ticks;
+        unsigned long long pclk;
+        static unsigned long tegra_last_pclk;
+
+        if (WARN_ON_ONCE(rate <= 0))
+                pclk = 100000000;
+        else
+                pclk = rate;
+
+        if ((rate != tegra_last_pclk)) {
+                ticks = (us_on * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER);
+
+                ticks = (us_off * pclk) + 999999ull;
+                do_div(ticks, 1000000);
+                tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER);
+                wmb();
+        }
+        tegra_last_pclk = pclk;
+}
+
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
+{
+        return pmc_pm_data.suspend_mode;
+}
+
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
+{
+        u32 reg;
+        unsigned long rate = 0;
+
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+        switch (mode) {
+        case TEGRA_SUSPEND_LP2:
+                rate = clk_get_rate(tegra_pclk);
+                break;
+        default:
+                break;
+        }
+
+        set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time,
+                         rate);
+
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+
+void tegra_pmc_suspend_init(void)
+{
+        u32 reg;
+
+        /* Always enable CPU power request */
+        reg = tegra_pmc_readl(PMC_CTRL);
+        reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+        tegra_pmc_writel(reg, PMC_CTRL);
+}
+#endif
+
 static const struct of_device_id matches[] __initconst = {
         { .compatible = "nvidia,tegra114-pmc" },
         { .compatible = "nvidia,tegra30-pmc" },
@@ -143,6 +237,10 @@ static const struct of_device_id matches[] __initconst = {
 static void tegra_pmc_parse_dt(void)
 {
         struct device_node *np;
+        u32 prop;
+        enum tegra_suspend_mode suspend_mode;
+        u32 core_good_time[2] = {0, 0};
+        u32 lp0_vec[2] = {0, 0};
 
         np = of_find_matching_node(NULL, matches);
         BUG_ON(!np);
@@ -151,6 +249,70 @@ static void tegra_pmc_parse_dt(void)
 
         tegra_pmc_invert_interrupt = of_property_read_bool(np,
                                      "nvidia,invert-interrupt");
+        tegra_pclk = of_clk_get_by_name(np, "pclk");
+        WARN_ON(IS_ERR(tegra_pclk));
+
+        /* Grabbing the power management configurations */
+        if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) {
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        } else {
+                switch (prop) {
+                case 0:
+                        suspend_mode = TEGRA_SUSPEND_LP0;
+                        break;
+                case 1:
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+                        break;
+                case 2:
+                        suspend_mode = TEGRA_SUSPEND_LP2;
+                        break;
+                default:
+                        suspend_mode = TEGRA_SUSPEND_NONE;
+                        break;
+                }
+        }
+        suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode);
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_good_time = prop;
+
+        if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.cpu_off_time = prop;
+
+        if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
+                        core_good_time, ARRAY_SIZE(core_good_time)))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_osc_time = core_good_time[0];
+        pmc_pm_data.core_pmu_time = core_good_time[1];
+
+        if (of_property_read_u32(np, "nvidia,core-pwr-off-time",
+                                 &prop))
+                suspend_mode = TEGRA_SUSPEND_NONE;
+        pmc_pm_data.core_off_time = prop;
+
+        pmc_pm_data.corereq_high = of_property_read_bool(np,
+                                "nvidia,core-power-req-active-high");
+
+        pmc_pm_data.sysclkreq_high = of_property_read_bool(np,
+                                "nvidia,sys-clock-req-active-high");
+
+        pmc_pm_data.combined_req = of_property_read_bool(np,
+                                "nvidia,combined-power-req");
+
+        pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np,
+                                "nvidia,cpu-pwr-good-en");
+
+        if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec,
+                                       ARRAY_SIZE(lp0_vec)))
+                if (suspend_mode == TEGRA_SUSPEND_LP0)
+                        suspend_mode = TEGRA_SUSPEND_LP1;
+
+        pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0];
+        pmc_pm_data.lp0_vec_size = lp0_vec[1];
+
+        pmc_pm_data.suspend_mode = suspend_mode;
 }
 
 void __init tegra_pmc_init(void)
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 7d44710368be..e1c2df272f7d 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,20 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+enum tegra_suspend_mode {
+        TEGRA_SUSPEND_NONE = 0,
+        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
+        TEGRA_SUSPEND_LP1,      /* CPU voltage off, DRAM self-refresh */
+        TEGRA_SUSPEND_LP0,      /* CPU + core voltage off, DRAM self-refresh */
+        TEGRA_MAX_SUSPEND_MODE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
+void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
+void tegra_pmc_suspend_init(void);
+#endif
+
 bool tegra_pmc_cpu_is_powered(int cpuid);
 int tegra_pmc_cpu_power_on(int cpuid);
 int tegra_pmc_cpu_remove_clamping(int cpuid);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 27232c901a22..84deeab23ee7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -33,6 +33,8 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
 
 #include <asm/mach-types.h>
@@ -42,6 +44,7 @@
 
 #include "board.h"
 #include "common.h"
+#include "fuse.h"
 #include "iomap.h"
 
 static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
@@ -80,12 +83,36 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
 
 static void __init tegra_dt_init(void)
 {
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id);
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
          */
+out:
         of_platform_populate(NULL, of_default_bus_match_table,
-                                tegra20_auxdata_lookup, NULL);
+                                tegra20_auxdata_lookup, parent);
 }
 
 static void __init trimslice_init(void)
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c
new file mode 100644
index 000000000000..5218d4853cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra114_speedo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bug.h>
+
+#include "fuse.h"
+
+#define CORE_PROCESS_CORNERS_NUM        2
+#define CPU_PROCESS_CORNERS_NUM         2
+
+enum {
+        THRESHOLD_INDEX_0,
+        THRESHOLD_INDEX_1,
+        THRESHOLD_INDEX_COUNT,
+};
+
+static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
+        {1123,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
+        {1695,     UINT_MAX},
+        {0,        UINT_MAX},
+};
+
+static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
+{
+        u32 tmp;
+
+        switch (sku) {
+        case 0x00:
+        case 0x10:
+        case 0x05:
+        case 0x06:
+                tegra_cpu_speedo_id = 1;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+
+        case 0x03:
+        case 0x04:
+                tegra_cpu_speedo_id = 2;
+                tegra_soc_speedo_id = 1;
+                *threshold = THRESHOLD_INDEX_1;
+                break;
+
+        default:
+                pr_err("Tegra114 Unknown SKU %d\n", sku);
+                tegra_cpu_speedo_id = 0;
+                tegra_soc_speedo_id = 0;
+                *threshold = THRESHOLD_INDEX_0;
+                break;
+        }
+
+        if (rev == TEGRA_REVISION_A01) {
+                tmp = tegra_fuse_readl(0x270) << 1;
+                tmp |= tegra_fuse_readl(0x26c);
+                if (!tmp)
+                        tegra_cpu_speedo_id = 0;
+        }
+}
+
+void tegra114_init_speedo_data(void)
+{
+        u32 cpu_speedo_val;
+        u32 core_speedo_val;
+        int threshold;
+        int i;
+
+        BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+        BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
+                        THRESHOLD_INDEX_COUNT);
+
+        rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
+
+        cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
+        core_speedo_val = tegra_fuse_readl(0x134);
+
+        for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
+                if (cpu_speedo_val < cpu_process_speedos[threshold][i])
+                        break;
+        tegra_cpu_process_id = i;
+
+        for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
+                if (core_speedo_val < core_process_speedos[threshold][i])
+                        break;
+        tegra_core_process_id = i;
+}