39 files changed, 1414 insertions, 422 deletions

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 91aff7cb8284..373652d76b90 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,11 +2,8 @@ if ARCH_TEGRA
 
 comment "NVIDIA Tegra options"
 
-choice
-        prompt "Select Tegra processor family for target system"
-
 config ARCH_TEGRA_2x_SOC
-        bool "Tegra 2 family"
+        bool "Enable support for Tegra20 family"
         select CPU_V7
         select ARM_GIC
         select ARCH_REQUIRE_GPIOLIB
@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
           Support for NVIDIA Tegra AP20 and T20 processors, based on the
           ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
-endchoice
+config ARCH_TEGRA_3x_SOC
+        bool "Enable support for Tegra30 family"
+        select CPU_V7
+        select ARM_GIC
+        select ARCH_REQUIRE_GPIOLIB
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
+        select USB_ULPI if USB_SUPPORT
+        select USB_ULPI_VIEWPORT if USB_SUPPORT
+        select USE_OF
+        help
+          Support for NVIDIA Tegra T30 processor family, based on the
+          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
 
 config TEGRA_PCI
         bool "PCI Express support"
+        depends on ARCH_TEGRA_2x_SOC
         select PCI
 
 comment "Tegra board type"
 
 config MACH_HARMONY
        bool "Harmony board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Harmony development platform
 
 config MACH_KAEN
        bool "Kaen board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
@@ -40,11 +51,13 @@ config MACH_KAEN
 
 config MACH_PAZ00
        bool "Paz00 board"
+       depends on ARCH_TEGRA_2x_SOC
        help
          Support for the Toshiba AC100/Dynabook AZ netbook
 
 config MACH_SEABOARD
        bool "Seaboard board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Seaboard development platform. It will
@@ -52,25 +65,29 @@ config MACH_SEABOARD
          have large similarities with the seaboard design.
 
 config MACH_TEGRA_DT
-        bool "Generic Tegra board (FDT support)"
+        bool "Generic Tegra20 board (FDT support)"
+        depends on ARCH_TEGRA_2x_SOC
         select USE_OF
         help
-          Support for generic nVidia Tegra boards using Flattened Device Tree
+          Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
 
 config MACH_TRIMSLICE
        bool "TrimSlice board"
+       depends on ARCH_TEGRA_2x_SOC
        select TEGRA_PCI
        help
          Support for CompuLab TrimSlice platform
 
 config MACH_WARIO
        bool "Wario board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
        help
          Support for the Wario version of Seaboard
 
 config MACH_VENTANA
        bool "Ventana board"
+       depends on ARCH_TEGRA_2x_SOC
        select MACH_TEGRA_DT
        help
          Support for the nVidia Ventana development platform
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 91a07e187208..e120ff54f663 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,4 @@
+obj-y                                   += board-pinmux.o
 obj-y                                   += common.o
 obj-y                                   += devices.o
 obj-y                                   += io.o
@@ -5,12 +6,13 @@ obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
-obj-y                                   += powergate.o
 obj-y                                   += fuse.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-t2-tables.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
@@ -18,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 
-obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-pcie.o
-obj-${CONFIG_MACH_HARMONY}              += board-harmony-power.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
+obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
 
-obj-${CONFIG_MACH_PAZ00}                += board-paz00.o
-obj-${CONFIG_MACH_PAZ00}                += board-paz00-pinmux.o
+obj-$(CONFIG_MACH_PAZ00)                += board-paz00.o
+obj-$(CONFIG_MACH_PAZ00)                += board-paz00-pinmux.o
 
-obj-${CONFIG_MACH_SEABOARD}             += board-seaboard.o
-obj-${CONFIG_MACH_SEABOARD}             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard.o
+obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard-pinmux.o
 
-obj-${CONFIG_MACH_TEGRA_DT}             += board-dt.o
-obj-${CONFIG_MACH_TEGRA_DT}             += board-harmony-pinmux.o
-obj-${CONFIG_MACH_TEGRA_DT}             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-dt-tegra20.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-harmony-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-seaboard-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-paz00-pinmux.o
+obj-$(CONFIG_MACH_TEGRA_DT)             += board-trimslice-pinmux.o
 
-obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice.o
-obj-${CONFIG_MACH_TRIMSLICE}            += board-trimslice-pinmux.o
+obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
+obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index bd12c9fb81e8..9a82094092d7 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
 dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
+dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
 dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
+dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
 dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 74743ad3d2d3..7a95e0bc4aba 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -32,10 +32,12 @@
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -46,10 +48,14 @@
 #include "devices.h"
 
 void harmony_pinmux_init(void);
+void paz00_pinmux_init(void);
 void seaboard_pinmux_init(void);
+void trimslice_pinmux_init(void);
 void ventana_pinmux_init(void);
 
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -57,16 +63,30 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
+                       &tegra_ehci1_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
+                       &tegra_ehci2_device.dev.platform_data),
+        OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
+                       &tegra_ehci3_device.dev.platform_data),
         {}
 };
 
 static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "uartd",      "pll_p",        216000000,      true },
+        { "usbd",       "clk_m",        12000000,       false },
+        { "usb2",       "clk_m",        12000000,       false },
+        { "usb3",       "clk_m",        12000000,       false },
+        { "pll_a",      "pll_p_out1",   56448000,       true },
+        { "pll_a_out0", "pll_a",        11289600,       true },
+        { "cdev1",      NULL,           0,              true },
+        { "i2s1",       "pll_a_out0",   11289600,       false},
+        { "i2s2",       "pll_a_out0",   11289600,       false},
         { NULL,         NULL,           0,              0},
 };
 
@@ -75,39 +95,23 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
         {}
 };
 
-static struct of_device_id tegra_dt_gic_match[] __initdata = {
-        { .compatible = "nvidia,tegra20-gic", },
-        {}
-};
-
 static struct {
         char *machine;
         void (*init)(void);
 } pinmux_configs[] = {
+        { "compulab,trimslice", trimslice_pinmux_init },
         { "nvidia,harmony", harmony_pinmux_init },
+        { "compal,paz00", paz00_pinmux_init },
         { "nvidia,seaboard", seaboard_pinmux_init },
         { "nvidia,ventana", ventana_pinmux_init },
 };
 
 static void __init tegra_dt_init(void)
 {
-        struct device_node *node;
         int i;
 
-        node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
-                                                TEGRA_ARM_INT_DIST_BASE);
-        if (node)
-                irq_domain_add_simple(node, INT_GIC_BASE);
-
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-        /*
-         * Finished with the static registrations now; fill in the missing
-         * devices
-         */
-        of_platform_populate(NULL, tegra_dt_match_table,
-                                tegra20_auxdata_lookup, NULL);
-
         for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
                 if (of_machine_is_compatible(pinmux_configs[i].machine)) {
                         pinmux_configs[i].init();
@@ -117,20 +121,31 @@ static void __init tegra_dt_init(void)
 
         WARN(i == ARRAY_SIZE(pinmux_configs),
                 "Unknown platform! Pinmuxing not initialized\n");
+
+        /*
+         * Finished with the static registrations now; fill in the missing
+         * devices
+         */
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                tegra20_auxdata_lookup, NULL);
 }
 
-static const char * tegra_dt_board_compat[] = {
+static const char *tegra20_dt_board_compat[] = {
+        "compulab,trimslice",
         "nvidia,harmony",
+        "compal,paz00",
         "nvidia,seaboard",
         "nvidia,ventana",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
-        .init_irq       = tegra_init_irq,
+        .init_early     = tegra20_init_early,
+        .init_irq       = tegra_dt_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_dt_init,
-        .dt_compat      = tegra_dt_board_compat,
+        .restart        = tegra_assert_system_reset,
+        .dt_compat      = tegra20_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
new file mode 100644
index 000000000000..3c197e2440b7
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-tegra/board-dt-tegra30.c
+ *
+ * NVIDIA Tegra30 device tree board support
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * Derived from:
+ *
+ * arch/arm/mach-tegra/board-dt-tegra20.c
+ *
+ * Copyright (C) 2010 Secret Lab Technologies, Ltd.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include "board.h"
+
+static struct of_device_id tegra_dt_match_table[] __initdata = {
+        { .compatible = "simple-bus", },
+        {}
+};
+
+static void __init tegra30_dt_init(void)
+{
+        of_platform_populate(NULL, tegra_dt_match_table,
+                                NULL, NULL);
+}
+
+static const char *tegra30_dt_board_compat[] = {
+        "nvidia,cardhu",
+        NULL
+};
+
+DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
+        .map_io         = tegra_map_common_io,
+        .init_early     = tegra30_init_early,
+        .init_irq       = tegra_dt_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .timer          = &tegra_timer,
+        .init_machine   = tegra30_dt_init,
+        .restart        = tegra_assert_system_reset,
+        .dt_compat      = tegra30_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 6db7d699ef1c..33c4fedab840 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -22,7 +22,6 @@
 
 #include <asm/mach-types.h>
 
-#include <mach/pinmux.h>
 #include "board.h"
 #include "board-harmony.h"
 
@@ -48,10 +47,6 @@ static int __init harmony_pcie_init(void)
 
         regulator_enable(regulator);
 
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_NORMAL);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
-
         err = tegra_pcie_init(true, true);
         if (err)
                 goto err_pcie;
@@ -59,10 +54,6 @@ static int __init harmony_pcie_init(void)
         return 0;
 
 err_pcie:
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPV, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXA, TEGRA_TRI_TRISTATE);
-        tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
-
         regulator_disable(regulator);
         regulator_put(regulator);
 err_reg:
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 7a4a26d5174c..465808c8ac0b 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-harmony.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config harmony_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
@@ -161,13 +157,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_EXT_MIC_EN,        .enable = true  },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = harmony_pinmux,
+        .pg_count = ARRAY_SIZE(harmony_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void harmony_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index f0bdc5e3fe52..a0f9634f6727 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <asm/setup.h>
 
 #include <mach/tegra_wm8903_pdata.h>
@@ -185,8 +186,10 @@ MACHINE_START(HARMONY, "harmony")
         .atag_offset    = 0x100,
         .fixup          = tegra_harmony_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_harmony_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index be30e215f4b7..c775572dcea4 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -19,10 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
 #include "board-paz00.h"
-#include "devices.h"
+#include "board-pinmux.h"
 
 static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -30,7 +31,7 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -143,11 +144,6 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
         { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
@@ -158,13 +154,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TEGRA_WIFI_LED,       .enable = true },
 };
 
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = paz00_pinmux,
+        .pg_count = ARRAY_SIZE(paz00_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
 void paz00_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-
-        tegra_pinmux_config_table(paz00_pinmux, ARRAY_SIZE(paz00_pinmux));
-
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 55c55ba89f1e..fcf4f377b1dc 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -23,12 +23,15 @@
 #include <linux/serial_8250.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
+#include <linux/gpio_keys.h>
 #include <linux/pda_power.h>
 #include <linux/io.h>
+#include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -114,12 +117,37 @@ static struct platform_device leds_gpio = {
         },
 };
 
+static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = TEGRA_GPIO_POWERKEY,
+                .active_low     = 1,
+                .desc           = "Power",
+                .type           = EV_KEY,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data paz00_gpio_keys = {
+        .buttons        = paz00_gpio_keys_buttons,
+        .nbuttons       = ARRAY_SIZE(paz00_gpio_keys_buttons),
+};
+
+static struct platform_device gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &paz00_gpio_keys,
+        },
+};
+
 static struct platform_device *paz00_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device4,
         &tegra_sdhci_device1,
         &wifi_rfkill_device,
         &leds_gpio,
+        &gpio_keys_device,
 };
 
 static void paz00_i2c_init(void)
@@ -188,8 +216,10 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
         .atag_offset    = 0x100,
         .fixup          = tegra_paz00_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_paz00_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 8aff06eb58c3..ffa83f580db6 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -32,6 +32,9 @@
 #define TEGRA_WIFI_RST                  TEGRA_GPIO_PD1
 #define TEGRA_WIFI_LED                  TEGRA_GPIO_PD0
 
+/* WakeUp */
+#define TEGRA_GPIO_POWERKEY     TEGRA_GPIO_PJ7
+
 void paz00_pinmux_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
new file mode 100644
index 000000000000..adc3efe979b3
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/notifier.h>
+#include <linux/of.h>
+#include <linux/string.h>
+
+#include <mach/gpio-tegra.h>
+#include <mach/pinmux.h>
+
+#include "board-pinmux.h"
+#include "devices.h"
+
+struct tegra_board_pinmux_conf *confs[2];
+
+static void tegra_board_pinmux_setup_gpios(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
+        }
+}
+
+static void tegra_board_pinmux_setup_pinmux(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+                if (!confs[i])
+                        continue;
+
+                tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+
+                if (confs[i]->drives)
+                        tegra_drive_pinmux_config_table(confs[i]->drives,
+                                                        confs[i]->drive_count);
+        }
+}
+
+static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
+                                         unsigned long event, void *vdev)
+{
+        static bool had_gpio;
+        static bool had_pinmux;
+
+        struct device *dev = vdev;
+        const char *devname;
+
+        if (event != BUS_NOTIFY_BOUND_DRIVER)
+                return NOTIFY_DONE;
+
+        devname = dev_name(dev);
+
+        if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
+                tegra_board_pinmux_setup_gpios();
+                had_gpio = true;
+        } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
+                tegra_board_pinmux_setup_pinmux();
+                had_pinmux = true;
+        }
+
+        if (had_gpio && had_pinmux)
+                return NOTIFY_STOP_MASK;
+        else
+                return NOTIFY_DONE;
+}
+
+static struct notifier_block nb = {
+        .notifier_call = tegra_board_pinmux_bus_notify,
+};
+
+static struct platform_device *devices[] = {
+        &tegra_gpio_device,
+        &tegra_pinmux_device,
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b)
+{
+        confs[0] = conf_a;
+        confs[1] = conf_b;
+
+        bus_register_notifier(&platform_bus_type, &nb);
+
+        if (!of_machine_is_compatible("nvidia,tegra20"))
+                platform_add_devices(devices, ARRAY_SIZE(devices));
+}
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
new file mode 100644
index 000000000000..4aac73546f54
--- /dev/null
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_BOARD_PINMUX_H
+#define __MACH_TEGRA_BOARD_PINMUX_H
+
+#define GPIO_DEV "tegra-gpio"
+#define PINMUX_DEV "tegra-pinmux"
+
+struct tegra_pingroup_config;
+struct tegra_gpio_table;
+
+struct tegra_board_pinmux_conf {
+        struct tegra_pingroup_config *pgs;
+        int pg_count;
+
+        struct tegra_drive_pingroup_config *drives;
+        int drive_count;
+
+        struct tegra_gpio_table *gpios;
+        int gpio_count;
+};
+
+void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
+                             struct tegra_board_pinmux_conf *conf_b);
+
+#endif
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index b1c2972f62fe..55e7e43a14ad 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -19,11 +19,11 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
-#include <mach/pinmux-t2.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-seaboard.h"
-#include "devices.h"
 
 #define DEFAULT_DRIVE(_name)                                    \
         {                                                       \
@@ -37,11 +37,11 @@
                 .slew_falling = TEGRA_SLEW_SLOWEST,             \
         }
 
-static __initdata struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
+static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
         DEFAULT_DRIVE(SDIO1),
 };
 
-static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
+static struct tegra_pingroup_config common_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -55,7 +55,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
@@ -65,7 +64,6 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -108,13 +106,8 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
@@ -122,25 +115,19 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
@@ -160,13 +147,24 @@ static __initdata struct tegra_pingroup_config seaboard_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 };
 
-static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
-        {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+static struct tegra_pingroup_config seaboard_pinmux[] = {
+        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+};
+
+static struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTD,  TEGRA_MUX_VI,       TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
@@ -181,65 +179,59 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
         {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table common_gpio_table[] = {
         { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
         { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
+        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+};
+
+static struct tegra_gpio_table seaboard_gpio_table[] = {
         { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
         { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
         { .gpio = TEGRA_GPIO_HP_DET,            .enable = true },
         { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
         { .gpio = TEGRA_GPIO_USB1,              .enable = true },
 };
 
-static void __init update_pinmux(struct tegra_pingroup_config *newtbl, int size)
-{
-        int i, j;
-        struct tegra_pingroup_config *new_pingroup, *base_pingroup;
-
-        /* Update base seaboard pinmux table with secondary board
-         * specific pinmux table table.
-         */
-        for (i = 0; i < size; i++) {
-                new_pingroup = &newtbl[i];
-                for (j = 0; j < ARRAY_SIZE(seaboard_pinmux); j++) {
-                        base_pingroup = &seaboard_pinmux[j];
-                        if (new_pingroup->pingroup == base_pingroup->pingroup) {
-                                *base_pingroup = *new_pingroup;
-                                break;
-                        }
-                }
-        }
-}
-
-void __init seaboard_common_pinmux_init(void)
-{
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
+static struct tegra_gpio_table ventana_gpio_table[] = {
+        /* hp_det */
+        { .gpio = TEGRA_GPIO_PW2,               .enable = true },
+        /* int_mic_en */
+        { .gpio = TEGRA_GPIO_PX0,               .enable = true },
+        /* ext_mic_en */
+        { .gpio = TEGRA_GPIO_PX1,               .enable = true },
+};
 
-        tegra_pinmux_config_table(seaboard_pinmux, ARRAY_SIZE(seaboard_pinmux));
+static struct tegra_board_pinmux_conf common_conf = {
+        .pgs = common_pinmux,
+        .pg_count = ARRAY_SIZE(common_pinmux),
+        .gpios = common_gpio_table,
+        .gpio_count = ARRAY_SIZE(common_gpio_table),
+};
 
-        tegra_drive_pinmux_config_table(seaboard_drive_pinmux,
-                                        ARRAY_SIZE(seaboard_drive_pinmux));
+static struct tegra_board_pinmux_conf seaboard_conf = {
+        .pgs = seaboard_pinmux,
+        .pg_count = ARRAY_SIZE(seaboard_pinmux),
+        .drives = seaboard_drive_pinmux,
+        .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
+        .gpios = seaboard_gpio_table,
+        .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
+};
 
-        tegra_gpio_config(common_gpio_table, ARRAY_SIZE(common_gpio_table));
-}
+static struct tegra_board_pinmux_conf ventana_conf = {
+        .pgs = ventana_pinmux,
+        .pg_count = ARRAY_SIZE(ventana_pinmux),
+        .gpios = ventana_gpio_table,
+        .gpio_count = ARRAY_SIZE(ventana_gpio_table),
+};
 
-void __init seaboard_pinmux_init(void)
+void seaboard_pinmux_init(void)
 {
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &seaboard_conf);
 }
 
-void __init ventana_pinmux_init(void)
+void ventana_pinmux_init(void)
 {
-        update_pinmux(ventana_pinmux, ARRAY_SIZE(ventana_pinmux));
-        seaboard_common_pinmux_init();
+        tegra_board_pinmux_init(&common_conf, &ventana_conf);
 }
-
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index bf13ea355efc..cfc74d46a09e 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -34,6 +34,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include "board.h"
 #include "board-seaboard.h"
@@ -282,26 +283,32 @@ static void __init tegra_wario_init(void)
 MACHINE_START(SEABOARD, "seaboard")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_seaboard_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
 
 MACHINE_START(KAEN, "kaen")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_kaen_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
 
 MACHINE_START(WARIO, "wario")
         .atag_offset    = 0x100,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_wario_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index 7ab719d46da0..a21a2be57cb6 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -19,12 +19,13 @@
 #include <linux/of.h>
 
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 
 #include "gpio-names.h"
+#include "board-pinmux.h"
 #include "board-trimslice.h"
-#include "devices.h"
 
-static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
+static struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
@@ -105,7 +106,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_RSVD3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
         {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
         {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
@@ -143,11 +144,6 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
         {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
 };
 
-static struct platform_device *pinmux_devices[] = {
-        &tegra_gpio_device,
-        &tegra_pinmux_device,
-};
-
 static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
         { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
@@ -156,11 +152,14 @@ static struct tegra_gpio_table gpio_table[] = {
         { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
 };
 
-void __init trimslice_pinmux_init(void)
+static struct tegra_board_pinmux_conf conf = {
+        .pgs = trimslice_pinmux,
+        .pg_count = ARRAY_SIZE(trimslice_pinmux),
+        .gpios = gpio_table,
+        .gpio_count = ARRAY_SIZE(gpio_table),
+};
+
+void trimslice_pinmux_init(void)
 {
-        if (!of_machine_is_compatible("nvidia,tegra20"))
-                platform_add_devices(pinmux_devices,
-                                        ARRAY_SIZE(pinmux_devices));
-        tegra_pinmux_config_table(trimslice_pinmux, ARRAY_SIZE(trimslice_pinmux));
-        tegra_gpio_config(gpio_table, ARRAY_SIZE(gpio_table));
+        tegra_board_pinmux_init(&conf, NULL);
 }
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 1a6617b7806f..cd52820a3e37 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -26,6 +26,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
@@ -174,8 +175,10 @@ MACHINE_START(TRIMSLICE, "trimslice")
         .atag_offset    = 0x100,
         .fixup          = tegra_trimslice_fixup,
         .map_io         = tegra_map_common_io,
-        .init_early     = tegra_init_early,
+        .init_early     = tegra20_init_early,
         .init_irq       = tegra_init_irq,
+        .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_trimslice_init,
+        .restart        = tegra_assert_system_reset,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1d14df7eb7de..75d1543d77c0 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,10 +25,11 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra_init_early(void);
+void __init tegra20_init_early(void);
+void __init tegra30_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
-void __init tegra_init_clock(void);
+void __init tegra_dt_init_irq(void);
 int __init tegra_pcie_init(bool init_port0, bool init_port1);
 
 extern struct sys_timer tegra_timer;
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca9..8337068a4abe 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-        tegra2_periph_reset_deassert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-        tegra2_periph_reset_assert(c);
+        BUG_ON(!c->ops->reset);
+        c->ops->reset(c, true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
-void __init tegra_init_clock(void)
-{
-        tegra2_init_clocks();
-}
-
-/*
- * The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB.
- */
-void tegra_sdmmc_tap_delay(struct clk *c, int delay)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&c->spinlock, flags);
-        tegra2_sdmmc_tap_delay(c, delay);
-        spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 688316abc64e..5c44106616c5 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -146,15 +146,11 @@ struct tegra_clk_init_table {
 };
 
 void tegra2_init_clocks(void);
-void tegra2_periph_reset_deassert(struct clk *c);
-void tegra2_periph_reset_assert(struct clk *c);
 void clk_init(struct clk *clk);
 struct clk *tegra_get_clock_by_name(const char *name);
-unsigned long clk_measure_input_freq(void);
 int clk_reparent(struct clk *c, struct clk *parent);
 void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
 unsigned long clk_get_rate_locked(struct clk *c);
 int clk_set_rate_locked(struct clk *c, unsigned long rate);
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 690b888be506..a2eb90169aed 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-tegra/board-harmony.c
+ * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -21,8 +21,10 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/of_irq.h>
 
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/iomap.h>
 #include <mach/system.h>
@@ -31,20 +33,31 @@
 #include "clock.h"
 #include "fuse.h"
 
-void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
+#ifdef CONFIG_OF
+static const struct of_device_id tegra_dt_irq_match[] __initconst = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
+        { }
+};
+
+void __init tegra_dt_init_irq(void)
+{
+        tegra_init_irq();
+        of_irq_init(tegra_dt_irq_match);
+}
+#endif
 
 void tegra_assert_system_reset(char mode, const char *cmd)
 {
-        void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+        void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
         u32 reg;
 
-        /* use *_related to avoid spinlock since caches are off */
         reg = readl_relaxed(reset);
-        reg |= 0x04;
+        reg |= 0x10;
         writel_relaxed(reg, reset);
 }
 
-static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
         /* name         parent          rate            enabled */
         { "clk_m",      NULL,           0,              true },
         { "pll_p",      "clk_m",        216000000,      true },
@@ -60,24 +73,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
         { "cpu",        NULL,           0,              true },
         { NULL,         NULL,           0,              0},
 };
+#endif
 
-static void __init tegra_init_cache(void)
+static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 {
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+        u32 aux_ctrl, cache_type;
 
-        writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
-        writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
+        writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
 
-        l2x0_init(p, 0x6C080001, 0x8200c3fe);
+        cache_type = readl(p + L2X0_CACHE_TYPE);
+        aux_ctrl = (cache_type & 0x700) << (17-8);
+        aux_ctrl |= 0x6C000001;
+
+        l2x0_init(p, aux_ctrl, 0x8200c3fe);
 #endif
 
 }
 
-void __init tegra_init_early(void)
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+void __init tegra20_init_early(void)
 {
         tegra_init_fuse();
-        tegra_init_clock();
-        tegra_clk_init_from_table(common_clk_init_table);
-        tegra_init_cache();
+        tegra2_init_clocks();
+        tegra_clk_init_from_table(tegra20_clk_init_table);
+        tegra_init_cache(0x331, 0x441);
 }
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+void __init tegra30_init_early(void)
+{
+        tegra_init_cache(0x441, 0x551);
+}
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index c8baf8f80d23..fc3ecb66de08 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
 void tegra_periph_reset_assert(struct clk *c);
 
 unsigned long clk_get_rate_all_locked(struct clk *c);
-void tegra_sdmmc_tap_delay(struct clk *c, int delay);
+void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c53889d..e577cfe27e72 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -12,45 +12,9 @@
  * GNU General Public License for more details.
  *
  */
-#include <mach/iomap.h>
-#include <mach/io.h>
 
-#if defined(CONFIG_ARM_GIC)
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
-        /* Uses the GIC interrupt controller built into the cpu */
-#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        movw \base, #(ICTRL_BASE & 0x0000ffff)
-        movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-#else
-        /* legacy interrupt controller for AP16 */
         .macro  disable_fiq
         .endm
 
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        @ EVP base at 0xf010f000
-        mov \base, #0xf0000000
-        orr \base, #0x00100000
-        orr \base, #0x0000f000
-        .endm
-
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr \irqnr, [\base, #0x20]      @ EVT_IRQ_STS
-        cmp \irqnr, #0x80
-        .endm
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 35a011fbc42d..f15defffb5d2 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -71,12 +71,6 @@
 
 #ifndef __ASSEMBLER__
 
-#define __arch_ioremap          tegra_ioremap
-#define __arch_iounmap          tegra_iounmap
-
-void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
-void tegra_iounmap(volatile void __iomem *addr);
-
 #define IO_ADDRESS(n) (IO_TO_VIRT(n))
 
 #ifdef CONFIG_TEGRA_PCI
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 73265af4dda3..a2146cd6867d 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,7 +25,6 @@
 
 #define IRQ_LOCALTIMER                  29
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
 /* Primary Interrupt Controller */
 #define INT_PRI_BASE                    (INT_GIC_BASE + 32)
 #define INT_TMR1                        (INT_PRI_BASE + 0)
@@ -178,6 +177,5 @@
 #define NR_BOARD_IRQS                   32
 
 #define NR_IRQS                         (INT_BOARD_BASE + NR_BOARD_IRQS)
-#endif
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 4f3572a1c684..20bb0545f992 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -53,6 +53,7 @@ struct tegra_kbc_platform_data {
         struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
         const struct matrix_keymap_data *keymap_data;
 
+        u32 wakeup_key;
         bool wakeup;
         bool use_fn_map;
         bool use_ghost_filter;
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
index 4c2626347263..6a40c1dbab17 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
@@ -1,5 +1,5 @@
 /*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
  *
  * Copyright (C) 2010 Google, Inc.
  *
@@ -14,8 +14,8 @@
  *
  */
 
-#ifndef __MACH_TEGRA_PINMUX_T2_H
-#define __MACH_TEGRA_PINMUX_T2_H
+#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
+#define __MACH_TEGRA_PINMUX_TEGRA20_H
 
 enum tegra_pingroup {
         TEGRA_PINGROUP_ATA = 0,
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
new file mode 100644
index 000000000000..c1aee3eb2df1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
@@ -0,0 +1,320 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
+#define __MACH_TEGRA_PINMUX_TEGRA30_H
+
+enum tegra_pingroup {
+        TEGRA_PINGROUP_ULPI_DATA0 = 0,
+        TEGRA_PINGROUP_ULPI_DATA1,
+        TEGRA_PINGROUP_ULPI_DATA2,
+        TEGRA_PINGROUP_ULPI_DATA3,
+        TEGRA_PINGROUP_ULPI_DATA4,
+        TEGRA_PINGROUP_ULPI_DATA5,
+        TEGRA_PINGROUP_ULPI_DATA6,
+        TEGRA_PINGROUP_ULPI_DATA7,
+        TEGRA_PINGROUP_ULPI_CLK,
+        TEGRA_PINGROUP_ULPI_DIR,
+        TEGRA_PINGROUP_ULPI_NXT,
+        TEGRA_PINGROUP_ULPI_STP,
+        TEGRA_PINGROUP_DAP3_FS,
+        TEGRA_PINGROUP_DAP3_DIN,
+        TEGRA_PINGROUP_DAP3_DOUT,
+        TEGRA_PINGROUP_DAP3_SCLK,
+        TEGRA_PINGROUP_GPIO_PV0,
+        TEGRA_PINGROUP_GPIO_PV1,
+        TEGRA_PINGROUP_SDMMC1_CLK,
+        TEGRA_PINGROUP_SDMMC1_CMD,
+        TEGRA_PINGROUP_SDMMC1_DAT3,
+        TEGRA_PINGROUP_SDMMC1_DAT2,
+        TEGRA_PINGROUP_SDMMC1_DAT1,
+        TEGRA_PINGROUP_SDMMC1_DAT0,
+        TEGRA_PINGROUP_GPIO_PV2,
+        TEGRA_PINGROUP_GPIO_PV3,
+        TEGRA_PINGROUP_CLK2_OUT,
+        TEGRA_PINGROUP_CLK2_REQ,
+        TEGRA_PINGROUP_LCD_PWR1,
+        TEGRA_PINGROUP_LCD_PWR2,
+        TEGRA_PINGROUP_LCD_SDIN,
+        TEGRA_PINGROUP_LCD_SDOUT,
+        TEGRA_PINGROUP_LCD_WR_N,
+        TEGRA_PINGROUP_LCD_CS0_N,
+        TEGRA_PINGROUP_LCD_DC0,
+        TEGRA_PINGROUP_LCD_SCK,
+        TEGRA_PINGROUP_LCD_PWR0,
+        TEGRA_PINGROUP_LCD_PCLK,
+        TEGRA_PINGROUP_LCD_DE,
+        TEGRA_PINGROUP_LCD_HSYNC,
+        TEGRA_PINGROUP_LCD_VSYNC,
+        TEGRA_PINGROUP_LCD_D0,
+        TEGRA_PINGROUP_LCD_D1,
+        TEGRA_PINGROUP_LCD_D2,
+        TEGRA_PINGROUP_LCD_D3,
+        TEGRA_PINGROUP_LCD_D4,
+        TEGRA_PINGROUP_LCD_D5,
+        TEGRA_PINGROUP_LCD_D6,
+        TEGRA_PINGROUP_LCD_D7,
+        TEGRA_PINGROUP_LCD_D8,
+        TEGRA_PINGROUP_LCD_D9,
+        TEGRA_PINGROUP_LCD_D10,
+        TEGRA_PINGROUP_LCD_D11,
+        TEGRA_PINGROUP_LCD_D12,
+        TEGRA_PINGROUP_LCD_D13,
+        TEGRA_PINGROUP_LCD_D14,
+        TEGRA_PINGROUP_LCD_D15,
+        TEGRA_PINGROUP_LCD_D16,
+        TEGRA_PINGROUP_LCD_D17,
+        TEGRA_PINGROUP_LCD_D18,
+        TEGRA_PINGROUP_LCD_D19,
+        TEGRA_PINGROUP_LCD_D20,
+        TEGRA_PINGROUP_LCD_D21,
+        TEGRA_PINGROUP_LCD_D22,
+        TEGRA_PINGROUP_LCD_D23,
+        TEGRA_PINGROUP_LCD_CS1_N,
+        TEGRA_PINGROUP_LCD_M1,
+        TEGRA_PINGROUP_LCD_DC1,
+        TEGRA_PINGROUP_HDMI_INT,
+        TEGRA_PINGROUP_DDC_SCL,
+        TEGRA_PINGROUP_DDC_SDA,
+        TEGRA_PINGROUP_CRT_HSYNC,
+        TEGRA_PINGROUP_CRT_VSYNC,
+        TEGRA_PINGROUP_VI_D0,
+        TEGRA_PINGROUP_VI_D1,
+        TEGRA_PINGROUP_VI_D2,
+        TEGRA_PINGROUP_VI_D3,
+        TEGRA_PINGROUP_VI_D4,
+        TEGRA_PINGROUP_VI_D5,
+        TEGRA_PINGROUP_VI_D6,
+        TEGRA_PINGROUP_VI_D7,
+        TEGRA_PINGROUP_VI_D8,
+        TEGRA_PINGROUP_VI_D9,
+        TEGRA_PINGROUP_VI_D10,
+        TEGRA_PINGROUP_VI_D11,
+        TEGRA_PINGROUP_VI_PCLK,
+        TEGRA_PINGROUP_VI_MCLK,
+        TEGRA_PINGROUP_VI_VSYNC,
+        TEGRA_PINGROUP_VI_HSYNC,
+        TEGRA_PINGROUP_UART2_RXD,
+        TEGRA_PINGROUP_UART2_TXD,
+        TEGRA_PINGROUP_UART2_RTS_N,
+        TEGRA_PINGROUP_UART2_CTS_N,
+        TEGRA_PINGROUP_UART3_TXD,
+        TEGRA_PINGROUP_UART3_RXD,
+        TEGRA_PINGROUP_UART3_CTS_N,
+        TEGRA_PINGROUP_UART3_RTS_N,
+        TEGRA_PINGROUP_GPIO_PU0,
+        TEGRA_PINGROUP_GPIO_PU1,
+        TEGRA_PINGROUP_GPIO_PU2,
+        TEGRA_PINGROUP_GPIO_PU3,
+        TEGRA_PINGROUP_GPIO_PU4,
+        TEGRA_PINGROUP_GPIO_PU5,
+        TEGRA_PINGROUP_GPIO_PU6,
+        TEGRA_PINGROUP_GEN1_I2C_SDA,
+        TEGRA_PINGROUP_GEN1_I2C_SCL,
+        TEGRA_PINGROUP_DAP4_FS,
+        TEGRA_PINGROUP_DAP4_DIN,
+        TEGRA_PINGROUP_DAP4_DOUT,
+        TEGRA_PINGROUP_DAP4_SCLK,
+        TEGRA_PINGROUP_CLK3_OUT,
+        TEGRA_PINGROUP_CLK3_REQ,
+        TEGRA_PINGROUP_GMI_WP_N,
+        TEGRA_PINGROUP_GMI_IORDY,
+        TEGRA_PINGROUP_GMI_WAIT,
+        TEGRA_PINGROUP_GMI_ADV_N,
+        TEGRA_PINGROUP_GMI_CLK,
+        TEGRA_PINGROUP_GMI_CS0_N,
+        TEGRA_PINGROUP_GMI_CS1_N,
+        TEGRA_PINGROUP_GMI_CS2_N,
+        TEGRA_PINGROUP_GMI_CS3_N,
+        TEGRA_PINGROUP_GMI_CS4_N,
+        TEGRA_PINGROUP_GMI_CS6_N,
+        TEGRA_PINGROUP_GMI_CS7_N,
+        TEGRA_PINGROUP_GMI_AD0,
+        TEGRA_PINGROUP_GMI_AD1,
+        TEGRA_PINGROUP_GMI_AD2,
+        TEGRA_PINGROUP_GMI_AD3,
+        TEGRA_PINGROUP_GMI_AD4,
+        TEGRA_PINGROUP_GMI_AD5,
+        TEGRA_PINGROUP_GMI_AD6,
+        TEGRA_PINGROUP_GMI_AD7,
+        TEGRA_PINGROUP_GMI_AD8,
+        TEGRA_PINGROUP_GMI_AD9,
+        TEGRA_PINGROUP_GMI_AD10,
+        TEGRA_PINGROUP_GMI_AD11,
+        TEGRA_PINGROUP_GMI_AD12,
+        TEGRA_PINGROUP_GMI_AD13,
+        TEGRA_PINGROUP_GMI_AD14,
+        TEGRA_PINGROUP_GMI_AD15,
+        TEGRA_PINGROUP_GMI_A16,
+        TEGRA_PINGROUP_GMI_A17,
+        TEGRA_PINGROUP_GMI_A18,
+        TEGRA_PINGROUP_GMI_A19,
+        TEGRA_PINGROUP_GMI_WR_N,
+        TEGRA_PINGROUP_GMI_OE_N,
+        TEGRA_PINGROUP_GMI_DQS,
+        TEGRA_PINGROUP_GMI_RST_N,
+        TEGRA_PINGROUP_GEN2_I2C_SCL,
+        TEGRA_PINGROUP_GEN2_I2C_SDA,
+        TEGRA_PINGROUP_SDMMC4_CLK,
+        TEGRA_PINGROUP_SDMMC4_CMD,
+        TEGRA_PINGROUP_SDMMC4_DAT0,
+        TEGRA_PINGROUP_SDMMC4_DAT1,
+        TEGRA_PINGROUP_SDMMC4_DAT2,
+        TEGRA_PINGROUP_SDMMC4_DAT3,
+        TEGRA_PINGROUP_SDMMC4_DAT4,
+        TEGRA_PINGROUP_SDMMC4_DAT5,
+        TEGRA_PINGROUP_SDMMC4_DAT6,
+        TEGRA_PINGROUP_SDMMC4_DAT7,
+        TEGRA_PINGROUP_SDMMC4_RST_N,
+        TEGRA_PINGROUP_CAM_MCLK,
+        TEGRA_PINGROUP_GPIO_PCC1,
+        TEGRA_PINGROUP_GPIO_PBB0,
+        TEGRA_PINGROUP_CAM_I2C_SCL,
+        TEGRA_PINGROUP_CAM_I2C_SDA,
+        TEGRA_PINGROUP_GPIO_PBB3,
+        TEGRA_PINGROUP_GPIO_PBB4,
+        TEGRA_PINGROUP_GPIO_PBB5,
+        TEGRA_PINGROUP_GPIO_PBB6,
+        TEGRA_PINGROUP_GPIO_PBB7,
+        TEGRA_PINGROUP_GPIO_PCC2,
+        TEGRA_PINGROUP_JTAG_RTCK,
+        TEGRA_PINGROUP_PWR_I2C_SCL,
+        TEGRA_PINGROUP_PWR_I2C_SDA,
+        TEGRA_PINGROUP_KB_ROW0,
+        TEGRA_PINGROUP_KB_ROW1,
+        TEGRA_PINGROUP_KB_ROW2,
+        TEGRA_PINGROUP_KB_ROW3,
+        TEGRA_PINGROUP_KB_ROW4,
+        TEGRA_PINGROUP_KB_ROW5,
+        TEGRA_PINGROUP_KB_ROW6,
+        TEGRA_PINGROUP_KB_ROW7,
+        TEGRA_PINGROUP_KB_ROW8,
+        TEGRA_PINGROUP_KB_ROW9,
+        TEGRA_PINGROUP_KB_ROW10,
+        TEGRA_PINGROUP_KB_ROW11,
+        TEGRA_PINGROUP_KB_ROW12,
+        TEGRA_PINGROUP_KB_ROW13,
+        TEGRA_PINGROUP_KB_ROW14,
+        TEGRA_PINGROUP_KB_ROW15,
+        TEGRA_PINGROUP_KB_COL0,
+        TEGRA_PINGROUP_KB_COL1,
+        TEGRA_PINGROUP_KB_COL2,
+        TEGRA_PINGROUP_KB_COL3,
+        TEGRA_PINGROUP_KB_COL4,
+        TEGRA_PINGROUP_KB_COL5,
+        TEGRA_PINGROUP_KB_COL6,
+        TEGRA_PINGROUP_KB_COL7,
+        TEGRA_PINGROUP_CLK_32K_OUT,
+        TEGRA_PINGROUP_SYS_CLK_REQ,
+        TEGRA_PINGROUP_CORE_PWR_REQ,
+        TEGRA_PINGROUP_CPU_PWR_REQ,
+        TEGRA_PINGROUP_PWR_INT_N,
+        TEGRA_PINGROUP_CLK_32K_IN,
+        TEGRA_PINGROUP_OWR,
+        TEGRA_PINGROUP_DAP1_FS,
+        TEGRA_PINGROUP_DAP1_DIN,
+        TEGRA_PINGROUP_DAP1_DOUT,
+        TEGRA_PINGROUP_DAP1_SCLK,
+        TEGRA_PINGROUP_CLK1_REQ,
+        TEGRA_PINGROUP_CLK1_OUT,
+        TEGRA_PINGROUP_SPDIF_IN,
+        TEGRA_PINGROUP_SPDIF_OUT,
+        TEGRA_PINGROUP_DAP2_FS,
+        TEGRA_PINGROUP_DAP2_DIN,
+        TEGRA_PINGROUP_DAP2_DOUT,
+        TEGRA_PINGROUP_DAP2_SCLK,
+        TEGRA_PINGROUP_SPI2_MOSI,
+        TEGRA_PINGROUP_SPI2_MISO,
+        TEGRA_PINGROUP_SPI2_CS0_N,
+        TEGRA_PINGROUP_SPI2_SCK,
+        TEGRA_PINGROUP_SPI1_MOSI,
+        TEGRA_PINGROUP_SPI1_SCK,
+        TEGRA_PINGROUP_SPI1_CS0_N,
+        TEGRA_PINGROUP_SPI1_MISO,
+        TEGRA_PINGROUP_SPI2_CS1_N,
+        TEGRA_PINGROUP_SPI2_CS2_N,
+        TEGRA_PINGROUP_SDMMC3_CLK,
+        TEGRA_PINGROUP_SDMMC3_CMD,
+        TEGRA_PINGROUP_SDMMC3_DAT0,
+        TEGRA_PINGROUP_SDMMC3_DAT1,
+        TEGRA_PINGROUP_SDMMC3_DAT2,
+        TEGRA_PINGROUP_SDMMC3_DAT3,
+        TEGRA_PINGROUP_SDMMC3_DAT4,
+        TEGRA_PINGROUP_SDMMC3_DAT5,
+        TEGRA_PINGROUP_SDMMC3_DAT6,
+        TEGRA_PINGROUP_SDMMC3_DAT7,
+        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L0_RST_N,
+        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_WAKE_N,
+        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L1_RST_N,
+        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
+        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
+        TEGRA_PINGROUP_PEX_L2_RST_N,
+        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
+        TEGRA_PINGROUP_HDMI_CEC,
+        TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_drive_pingroup {
+        TEGRA_DRIVE_PINGROUP_AO1 = 0,
+        TEGRA_DRIVE_PINGROUP_AO2,
+        TEGRA_DRIVE_PINGROUP_AT1,
+        TEGRA_DRIVE_PINGROUP_AT2,
+        TEGRA_DRIVE_PINGROUP_AT3,
+        TEGRA_DRIVE_PINGROUP_AT4,
+        TEGRA_DRIVE_PINGROUP_AT5,
+        TEGRA_DRIVE_PINGROUP_CDEV1,
+        TEGRA_DRIVE_PINGROUP_CDEV2,
+        TEGRA_DRIVE_PINGROUP_CSUS,
+        TEGRA_DRIVE_PINGROUP_DAP1,
+        TEGRA_DRIVE_PINGROUP_DAP2,
+        TEGRA_DRIVE_PINGROUP_DAP3,
+        TEGRA_DRIVE_PINGROUP_DAP4,
+        TEGRA_DRIVE_PINGROUP_DBG,
+        TEGRA_DRIVE_PINGROUP_LCD1,
+        TEGRA_DRIVE_PINGROUP_LCD2,
+        TEGRA_DRIVE_PINGROUP_SDIO2,
+        TEGRA_DRIVE_PINGROUP_SDIO3,
+        TEGRA_DRIVE_PINGROUP_SPI,
+        TEGRA_DRIVE_PINGROUP_UAA,
+        TEGRA_DRIVE_PINGROUP_UAB,
+        TEGRA_DRIVE_PINGROUP_UART2,
+        TEGRA_DRIVE_PINGROUP_UART3,
+        TEGRA_DRIVE_PINGROUP_VI1,
+        TEGRA_DRIVE_PINGROUP_SDIO1,
+        TEGRA_DRIVE_PINGROUP_CRT,
+        TEGRA_DRIVE_PINGROUP_DDC,
+        TEGRA_DRIVE_PINGROUP_GMA,
+        TEGRA_DRIVE_PINGROUP_GMB,
+        TEGRA_DRIVE_PINGROUP_GMC,
+        TEGRA_DRIVE_PINGROUP_GMD,
+        TEGRA_DRIVE_PINGROUP_GME,
+        TEGRA_DRIVE_PINGROUP_GMF,
+        TEGRA_DRIVE_PINGROUP_GMG,
+        TEGRA_DRIVE_PINGROUP_GMH,
+        TEGRA_DRIVE_PINGROUP_OWR,
+        TEGRA_DRIVE_PINGROUP_UAD,
+        TEGRA_DRIVE_PINGROUP_GPV,
+        TEGRA_DRIVE_PINGROUP_DEV3,
+        TEGRA_DRIVE_PINGROUP_CEC,
+        TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index bb7dfdb61205..055f1792c8ff 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -2,6 +2,7 @@
  * linux/arch/arm/mach-tegra/include/mach/pinmux.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2010,2011 Nvidia, Inc.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,18 +18,13 @@
 #ifndef __MACH_TEGRA_PINMUX_H
 #define __MACH_TEGRA_PINMUX_H
 
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
-#include "pinmux-t2.h"
-#else
-#error "Undefined Tegra architecture"
-#endif
-
 enum tegra_mux_func {
         TEGRA_MUX_RSVD = 0x8000,
         TEGRA_MUX_RSVD1 = 0x8000,
         TEGRA_MUX_RSVD2 = 0x8001,
         TEGRA_MUX_RSVD3 = 0x8002,
         TEGRA_MUX_RSVD4 = 0x8003,
+        TEGRA_MUX_INVALID = 0x4000,
         TEGRA_MUX_NONE = -1,
         TEGRA_MUX_AHB_CLK,
         TEGRA_MUX_APB_CLK,
@@ -90,6 +86,49 @@ enum tegra_mux_func {
         TEGRA_MUX_VI,
         TEGRA_MUX_VI_SENSOR_CLK,
         TEGRA_MUX_XIO,
+        TEGRA_MUX_BLINK,
+        TEGRA_MUX_CEC,
+        TEGRA_MUX_CLK12,
+        TEGRA_MUX_DAP,
+        TEGRA_MUX_DAPSDMMC2,
+        TEGRA_MUX_DDR,
+        TEGRA_MUX_DEV3,
+        TEGRA_MUX_DTV,
+        TEGRA_MUX_VI_ALT1,
+        TEGRA_MUX_VI_ALT2,
+        TEGRA_MUX_VI_ALT3,
+        TEGRA_MUX_EMC_DLL,
+        TEGRA_MUX_EXTPERIPH1,
+        TEGRA_MUX_EXTPERIPH2,
+        TEGRA_MUX_EXTPERIPH3,
+        TEGRA_MUX_GMI_ALT,
+        TEGRA_MUX_HDA,
+        TEGRA_MUX_HSI,
+        TEGRA_MUX_I2C4,
+        TEGRA_MUX_I2C5,
+        TEGRA_MUX_I2CPWR,
+        TEGRA_MUX_I2S0,
+        TEGRA_MUX_I2S1,
+        TEGRA_MUX_I2S2,
+        TEGRA_MUX_I2S3,
+        TEGRA_MUX_I2S4,
+        TEGRA_MUX_NAND_ALT,
+        TEGRA_MUX_POPSDIO4,
+        TEGRA_MUX_POPSDMMC4,
+        TEGRA_MUX_PWM0,
+        TEGRA_MUX_PWM1,
+        TEGRA_MUX_PWM2,
+        TEGRA_MUX_PWM3,
+        TEGRA_MUX_SATA,
+        TEGRA_MUX_SPI5,
+        TEGRA_MUX_SPI6,
+        TEGRA_MUX_SYSCLK,
+        TEGRA_MUX_VGP1,
+        TEGRA_MUX_VGP2,
+        TEGRA_MUX_VGP3,
+        TEGRA_MUX_VGP4,
+        TEGRA_MUX_VGP5,
+        TEGRA_MUX_VGP6,
         TEGRA_MUX_SAFE,
         TEGRA_MAX_MUX,
 };
@@ -105,6 +144,11 @@ enum tegra_tristate {
         TEGRA_TRI_TRISTATE = 1,
 };
 
+enum tegra_pin_io {
+        TEGRA_PIN_OUTPUT = 0,
+        TEGRA_PIN_INPUT = 1,
+};
+
 enum tegra_vddio {
         TEGRA_VDDIO_BB = 0,
         TEGRA_VDDIO_LCD,
@@ -115,10 +159,16 @@ enum tegra_vddio {
         TEGRA_VDDIO_SYS,
         TEGRA_VDDIO_AUDIO,
         TEGRA_VDDIO_SD,
+        TEGRA_VDDIO_CAM,
+        TEGRA_VDDIO_GMI,
+        TEGRA_VDDIO_PEXCTL,
+        TEGRA_VDDIO_SDMMC1,
+        TEGRA_VDDIO_SDMMC3,
+        TEGRA_VDDIO_SDMMC4,
 };
 
 struct tegra_pingroup_config {
-        enum tegra_pingroup     pingroup;
+        int pingroup;
         enum tegra_mux_func     func;
         enum tegra_pullupdown   pupd;
         enum tegra_tristate     tristate;
@@ -187,7 +237,7 @@ enum tegra_schmitt {
 };
 
 struct tegra_drive_pingroup_config {
-        enum tegra_drive_pingroup pingroup;
+        int pingroup;
         enum tegra_hsm hsm;
         enum tegra_schmitt schmitt;
         enum tegra_drive drive;
@@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
         int funcs[4];
         int func_safe;
         int vddio;
+        enum tegra_pin_io io_default;
         s16 tri_bank;   /* Register bank the tri_reg exists within */
         s16 mux_bank;   /* Register bank the mux_reg exists within */
         s16 pupd_bank;  /* Register bank the pupd_reg exists within */
@@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
         s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
         s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
         s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
+        s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
+        s8 od_bit;      /* offset of the OD bit into mux register bit */
+        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
 };
 
-extern const struct tegra_pingroup_desc tegra_soc_pingroups[];
-extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[];
+typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
+        int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+        int *pgdrive_max);
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd);
+void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
+        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
+
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
 
 void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
         int len);
@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
         int len, enum tegra_pullupdown pupd);
 #endif
-
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
index 027c4215d313..a312988bf6f8 100644
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -21,10 +21,6 @@
 #ifndef __MACH_TEGRA_SYSTEM_H
 #define __MACH_TEGRA_SYSTEM_H
 
-#include <mach/iomap.h>
-
-extern void (*arch_reset)(char mode, const char *cmd);
-
 static inline void arch_idle(void)
 {
 }
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
deleted file mode 100644
index fd6aa65b2dc6..000000000000
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/vmalloc.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- *      Colin Cross <ccross@google.com>
- *      Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_VMALLOC_H
-#define __MACH_TEGRA_VMALLOC_H
-
-#include <asm/sizes.h>
-
-#define VMALLOC_END        0xFE000000UL
-
-#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 5489f8b5d6ad..d23ee2db2827 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -60,24 +60,3 @@ void __init tegra_map_common_io(void)
 {
         iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
 }
-
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        void __iomem *v = IO_ADDRESS(p);
-        if (v == NULL)
-                v = __arm_ioremap(p, size, type);
-        return v;
-}
-EXPORT_SYMBOL(tegra_ioremap);
-
-void tegra_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4956c3cea731..4e1afcd54fae 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -21,6 +21,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 
 #include <asm/hardware/gic.h>
 
@@ -28,10 +29,6 @@
 
 #include "board.h"
 
-#define INT_SYS_NR      (INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ      (INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR          ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
 #define ICTLR_CPU_IEP_VFIQ      0x08
 #define ICTLR_CPU_IEP_FIR       0x14
 #define ICTLR_CPU_IEP_FIR_SET   0x18
@@ -129,6 +126,11 @@ void __init tegra_init_irq(void)
         gic_arch_extn.irq_unmask = tegra_unmask;
         gic_arch_extn.irq_retrigger = tegra_retrigger;
 
-        gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
-                 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+        /*
+         * Check if there is a devicetree present, since the GIC will be
+         * initialized elsewhere under DT.
+         */
+        if (!of_have_populated_dt())
+                gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                        IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 }
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 92947d86fc87..af8b63435727 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -37,7 +37,6 @@
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/pinmux.h>
 #include <mach/iomap.h>
 #include <mach/clk.h>
 #include <mach/powergate.h>
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
index a0dc2bc28ed3..734add1280b7 100644
--- a/arch/arm/mach-tegra/pinmux-t2-tables.c
+++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
@@ -1,7 +1,7 @@
 /*
- * linux/arch/arm/mach-tegra/pinmux-t2-tables.c
+ * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
  *
- * Common pinmux configurations for Tegra 2 SoCs
+ * Common pinmux configurations for Tegra20 SoCs
  *
  * Copyright (C) 2010 NVIDIA Corporation
  *
@@ -29,6 +29,7 @@
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
+#include <mach/pinmux-tegra20.h>
 #include <mach/suspend.h>
 
 #define TRISTATE_REG_A          0x14
@@ -43,7 +44,7 @@
                 .reg = ((r) - PINGROUP_REG_A)                   \
         }
 
-const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
         DRIVE_PINGROUP(AO1,             0x868),
         DRIVE_PINGROUP(AO2,             0x86c),
         DRIVE_PINGROUP(AT1,             0x870),
@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
                 .pupd_bank = 2,                         \
                 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
                 .pupd_bit = pupd_b,                             \
+                .lock_bit = -1,                                 \
+                .od_bit = -1,                                   \
+                .ioreset_bit = -1,                              \
+                .io_default = -1,                               \
         }
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
         PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
         PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
         PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
         PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
 };
+
+void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
new file mode 100644
index 000000000000..14fc0e4c1c44
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
@@ -0,0 +1,376 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+ *
+ * Common pinmux configurations for Tegra30 SoCs
+ *
+ * Copyright (C) 2010,2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-tegra30.h>
+#include <mach/suspend.h>
+
+#define PINGROUP_REG_A  0x868
+#define MUXCTL_REG_A    0x3000
+
+#define DRIVE_PINGROUP(pg_name, r)              \
+        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
+                .name = #pg_name,               \
+                .reg_bank = 0,                  \
+                .reg = ((r) - PINGROUP_REG_A)   \
+        }
+
+static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
+        DRIVE_PINGROUP(AO1,             0x868),
+        DRIVE_PINGROUP(AO2,             0x86c),
+        DRIVE_PINGROUP(AT1,             0x870),
+        DRIVE_PINGROUP(AT2,             0x874),
+        DRIVE_PINGROUP(AT3,             0x878),
+        DRIVE_PINGROUP(AT4,             0x87c),
+        DRIVE_PINGROUP(AT5,             0x880),
+        DRIVE_PINGROUP(CDEV1,           0x884),
+        DRIVE_PINGROUP(CDEV2,           0x888),
+        DRIVE_PINGROUP(CSUS,            0x88c),
+        DRIVE_PINGROUP(DAP1,            0x890),
+        DRIVE_PINGROUP(DAP2,            0x894),
+        DRIVE_PINGROUP(DAP3,            0x898),
+        DRIVE_PINGROUP(DAP4,            0x89c),
+        DRIVE_PINGROUP(DBG,             0x8a0),
+        DRIVE_PINGROUP(LCD1,            0x8a4),
+        DRIVE_PINGROUP(LCD2,            0x8a8),
+        DRIVE_PINGROUP(SDIO2,           0x8ac),
+        DRIVE_PINGROUP(SDIO3,           0x8b0),
+        DRIVE_PINGROUP(SPI,             0x8b4),
+        DRIVE_PINGROUP(UAA,             0x8b8),
+        DRIVE_PINGROUP(UAB,             0x8bc),
+        DRIVE_PINGROUP(UART2,           0x8c0),
+        DRIVE_PINGROUP(UART3,           0x8c4),
+        DRIVE_PINGROUP(VI1,             0x8c8),
+        DRIVE_PINGROUP(SDIO1,           0x8ec),
+        DRIVE_PINGROUP(CRT,             0x8f8),
+        DRIVE_PINGROUP(DDC,             0x8fc),
+        DRIVE_PINGROUP(GMA,             0x900),
+        DRIVE_PINGROUP(GMB,             0x904),
+        DRIVE_PINGROUP(GMC,             0x908),
+        DRIVE_PINGROUP(GMD,             0x90c),
+        DRIVE_PINGROUP(GME,             0x910),
+        DRIVE_PINGROUP(GMF,             0x914),
+        DRIVE_PINGROUP(GMG,             0x918),
+        DRIVE_PINGROUP(GMH,             0x91c),
+        DRIVE_PINGROUP(OWR,             0x920),
+        DRIVE_PINGROUP(UAD,             0x924),
+        DRIVE_PINGROUP(GPV,             0x928),
+        DRIVE_PINGROUP(DEV3,            0x92c),
+        DRIVE_PINGROUP(CEC,             0x938),
+};
+
+#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)    \
+        [TEGRA_PINGROUP_ ## pg_name] = {                        \
+                .name = #pg_name,                               \
+                .vddio = TEGRA_VDDIO_ ## vdd,                   \
+                .funcs = {                                      \
+                        TEGRA_MUX_ ## f0,                       \
+                        TEGRA_MUX_ ## f1,                       \
+                        TEGRA_MUX_ ## f2,                       \
+                        TEGRA_MUX_ ## f3,                       \
+                },                                              \
+                .func_safe = TEGRA_MUX_ ## fs,                  \
+                .tri_bank = 1,                                  \
+                .tri_reg = ((reg) - MUXCTL_REG_A),              \
+                .tri_bit = 4,                                   \
+                .mux_bank = 1,                                  \
+                .mux_reg = ((reg) - MUXCTL_REG_A),              \
+                .mux_bit = 0,                                   \
+                .pupd_bank = 1,                                 \
+                .pupd_reg = ((reg) - MUXCTL_REG_A),             \
+                .pupd_bit = 2,                                  \
+                .io_default = TEGRA_PIN_ ## iod,                \
+                .od_bit = 6,                                    \
+                .lock_bit = 7,                                  \
+                .ioreset_bit = 8,                               \
+        }
+
+static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
+        /*       NAME             VDD       f0          f1          f2          f3          fSafe       io      reg */
+        PINGROUP(ULPI_DATA0,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),
+        PINGROUP(ULPI_DATA1,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),
+        PINGROUP(ULPI_DATA2,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),
+        PINGROUP(ULPI_DATA3,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),
+        PINGROUP(ULPI_DATA4,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),
+        PINGROUP(ULPI_DATA5,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),
+        PINGROUP(ULPI_DATA6,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),
+        PINGROUP(ULPI_DATA7,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),
+        PINGROUP(ULPI_CLK,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),
+        PINGROUP(ULPI_DIR,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),
+        PINGROUP(ULPI_NXT,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),
+        PINGROUP(ULPI_STP,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),
+        PINGROUP(DAP3_FS,         BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),
+        PINGROUP(DAP3_DIN,        BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),
+        PINGROUP(DAP3_DOUT,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),
+        PINGROUP(DAP3_SCLK,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),
+        PINGROUP(GPIO_PV0,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),
+        PINGROUP(GPIO_PV1,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),
+        PINGROUP(SDMMC1_CLK,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x3048),
+        PINGROUP(SDMMC1_CMD,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x304c),
+        PINGROUP(SDMMC1_DAT3,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3050),
+        PINGROUP(SDMMC1_DAT2,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3054),
+        PINGROUP(SDMMC1_DAT1,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3058),
+        PINGROUP(SDMMC1_DAT0,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x305c),
+        PINGROUP(GPIO_PV2,        SDMMC1,   OWR,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3060),
+        PINGROUP(GPIO_PV3,        SDMMC1,   INVALID,    RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3064),
+        PINGROUP(CLK2_OUT,        SDMMC1,   EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),
+        PINGROUP(CLK2_REQ,        SDMMC1,   DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),
+        PINGROUP(LCD_PWR1,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3070),
+        PINGROUP(LCD_PWR2,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3074),
+        PINGROUP(LCD_SDIN,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3078),
+        PINGROUP(LCD_SDOUT,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x307c),
+        PINGROUP(LCD_WR_N,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3080),
+        PINGROUP(LCD_CS0_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3084),
+        PINGROUP(LCD_DC0,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3088),
+        PINGROUP(LCD_SCK,         LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x308c),
+        PINGROUP(LCD_PWR0,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3090),
+        PINGROUP(LCD_PCLK,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3094),
+        PINGROUP(LCD_DE,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3098),
+        PINGROUP(LCD_HSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x309c),
+        PINGROUP(LCD_VSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a0),
+        PINGROUP(LCD_D0,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a4),
+        PINGROUP(LCD_D1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a8),
+        PINGROUP(LCD_D2,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ac),
+        PINGROUP(LCD_D3,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b0),
+        PINGROUP(LCD_D4,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b4),
+        PINGROUP(LCD_D5,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b8),
+        PINGROUP(LCD_D6,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30bc),
+        PINGROUP(LCD_D7,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c0),
+        PINGROUP(LCD_D8,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c4),
+        PINGROUP(LCD_D9,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c8),
+        PINGROUP(LCD_D10,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30cc),
+        PINGROUP(LCD_D11,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d0),
+        PINGROUP(LCD_D12,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d4),
+        PINGROUP(LCD_D13,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d8),
+        PINGROUP(LCD_D14,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30dc),
+        PINGROUP(LCD_D15,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e0),
+        PINGROUP(LCD_D16,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e4),
+        PINGROUP(LCD_D17,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e8),
+        PINGROUP(LCD_D18,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ec),
+        PINGROUP(LCD_D19,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f0),
+        PINGROUP(LCD_D20,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f4),
+        PINGROUP(LCD_D21,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f8),
+        PINGROUP(LCD_D22,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30fc),
+        PINGROUP(LCD_D23,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3100),
+        PINGROUP(LCD_CS1_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD2,      RSVD,       OUTPUT, 0x3104),
+        PINGROUP(LCD_M1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3108),
+        PINGROUP(LCD_DC1,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x310c),
+        PINGROUP(HDMI_INT,        LCD,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),
+        PINGROUP(DDC_SCL,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),
+        PINGROUP(DDC_SDA,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),
+        PINGROUP(CRT_HSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x311c),
+        PINGROUP(CRT_VSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3120),
+        PINGROUP(VI_D0,           VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3124),
+        PINGROUP(VI_D1,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3128),
+        PINGROUP(VI_D2,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x312c),
+        PINGROUP(VI_D3,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3130),
+        PINGROUP(VI_D4,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3134),
+        PINGROUP(VI_D5,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3138),
+        PINGROUP(VI_D6,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x313c),
+        PINGROUP(VI_D7,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3140),
+        PINGROUP(VI_D8,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3144),
+        PINGROUP(VI_D9,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3148),
+        PINGROUP(VI_D10,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x314c),
+        PINGROUP(VI_D11,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3150),
+        PINGROUP(VI_PCLK,         VI,       RSVD1,      SDIO2,      VI,         RSVD2,      RSVD,       INPUT,  0x3154),
+        PINGROUP(VI_MCLK,         VI,       VI,         INVALID,    INVALID,    INVALID,    RSVD,       INPUT,  0x3158),
+        PINGROUP(VI_VSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x315c),
+        PINGROUP(VI_HSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3160),
+        PINGROUP(UART2_RXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),
+        PINGROUP(UART2_TXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),
+        PINGROUP(UART2_RTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x316c),
+        PINGROUP(UART2_CTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x3170),
+        PINGROUP(UART3_TXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3174),
+        PINGROUP(UART3_RXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3178),
+        PINGROUP(UART3_CTS_N,     UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x317c),
+        PINGROUP(UART3_RTS_N,     UART,     UARTC,      PWM0,       GMI,        RSVD2,      RSVD,       INPUT,  0x3180),
+        PINGROUP(GPIO_PU0,        UART,     OWR,        UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3184),
+        PINGROUP(GPIO_PU1,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x3188),
+        PINGROUP(GPIO_PU2,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x318c),
+        PINGROUP(GPIO_PU3,        UART,     PWM0,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3190),
+        PINGROUP(GPIO_PU4,        UART,     PWM1,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3194),
+        PINGROUP(GPIO_PU5,        UART,     PWM2,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3198),
+        PINGROUP(GPIO_PU6,        UART,     PWM3,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x319c),
+        PINGROUP(GEN1_I2C_SDA,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),
+        PINGROUP(GEN1_I2C_SCL,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),
+        PINGROUP(DAP4_FS,         UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31a8),
+        PINGROUP(DAP4_DIN,        UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31ac),
+        PINGROUP(DAP4_DOUT,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b0),
+        PINGROUP(DAP4_SCLK,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b4),
+        PINGROUP(CLK3_OUT,        UART,     EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),
+        PINGROUP(CLK3_REQ,        UART,     DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),
+        PINGROUP(GMI_WP_N,        GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),
+        PINGROUP(GMI_IORDY,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c4),
+        PINGROUP(GMI_WAIT,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c8),
+        PINGROUP(GMI_ADV_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31cc),
+        PINGROUP(GMI_CLK,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d0),
+        PINGROUP(GMI_CS0_N,       GMI,      RSVD1,      NAND,       GMI,        INVALID,    RSVD,       INPUT,  0x31d4),
+        PINGROUP(GMI_CS1_N,       GMI,      RSVD1,      NAND,       GMI,        DTV,        RSVD,       INPUT,  0x31d8),
+        PINGROUP(GMI_CS2_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),
+        PINGROUP(GMI_CS3_N,       GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),
+        PINGROUP(GMI_CS4_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31e4),
+        PINGROUP(GMI_CS6_N,       GMI,      NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),
+        PINGROUP(GMI_CS7_N,       GMI,      NAND,       NAND_ALT,   GMI,        GMI_ALT,    RSVD,       INPUT,  0x31ec),
+        PINGROUP(GMI_AD0,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),
+        PINGROUP(GMI_AD1,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),
+        PINGROUP(GMI_AD2,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),
+        PINGROUP(GMI_AD3,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),
+        PINGROUP(GMI_AD4,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),
+        PINGROUP(GMI_AD5,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),
+        PINGROUP(GMI_AD6,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),
+        PINGROUP(GMI_AD7,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),
+        PINGROUP(GMI_AD8,         GMI,      PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),
+        PINGROUP(GMI_AD9,         GMI,      PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),
+        PINGROUP(GMI_AD10,        GMI,      PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),
+        PINGROUP(GMI_AD11,        GMI,      PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),
+        PINGROUP(GMI_AD12,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),
+        PINGROUP(GMI_AD13,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),
+        PINGROUP(GMI_AD14,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),
+        PINGROUP(GMI_AD15,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),
+        PINGROUP(GMI_A16,         GMI,      UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),
+        PINGROUP(GMI_A17,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3234),
+        PINGROUP(GMI_A18,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3238),
+        PINGROUP(GMI_A19,         GMI,      UARTD,      SPI4,       GMI,        RSVD3,      RSVD,       INPUT,  0x323c),
+        PINGROUP(GMI_WR_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),
+        PINGROUP(GMI_OE_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),
+        PINGROUP(GMI_DQS,         GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3248),
+        PINGROUP(GMI_RST_N,       GMI,      NAND,       NAND_ALT,   GMI,        RSVD3,      RSVD,       INPUT,  0x324c),
+        PINGROUP(GEN2_I2C_SCL,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3250),
+        PINGROUP(GEN2_I2C_SDA,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3254),
+        PINGROUP(SDMMC4_CLK,      SDMMC4,   INVALID,    NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x3258),
+        PINGROUP(SDMMC4_CMD,      SDMMC4,   I2C3,       NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x325c),
+        PINGROUP(SDMMC4_DAT0,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3260),
+        PINGROUP(SDMMC4_DAT1,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3264),
+        PINGROUP(SDMMC4_DAT2,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3268),
+        PINGROUP(SDMMC4_DAT3,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x326c),
+        PINGROUP(SDMMC4_DAT4,     SDMMC4,   I2C3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3270),
+        PINGROUP(SDMMC4_DAT5,     SDMMC4,   VGP3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3274),
+        PINGROUP(SDMMC4_DAT6,     SDMMC4,   VGP4,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3278),
+        PINGROUP(SDMMC4_DAT7,     SDMMC4,   VGP5,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x327c),
+        PINGROUP(SDMMC4_RST_N,    SDMMC4,   VGP6,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3280),
+        PINGROUP(CAM_MCLK,        CAM,      VI,         INVALID,    VI_ALT2,    POPSDMMC4,  RSVD,       INPUT,  0x3284),
+        PINGROUP(GPIO_PCC1,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3288),
+        PINGROUP(GPIO_PBB0,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x328c),
+        PINGROUP(CAM_I2C_SCL,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3290),
+        PINGROUP(CAM_I2C_SDA,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3294),
+        PINGROUP(GPIO_PBB3,       CAM,      VGP3,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x3298),
+        PINGROUP(GPIO_PBB4,       CAM,      VGP4,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x329c),
+        PINGROUP(GPIO_PBB5,       CAM,      VGP5,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a0),
+        PINGROUP(GPIO_PBB6,       CAM,      VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),
+        PINGROUP(GPIO_PBB7,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x32a8),
+        PINGROUP(GPIO_PCC2,       CAM,      I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),
+        PINGROUP(JTAG_RTCK,       SYS,      RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),
+        PINGROUP(PWR_I2C_SCL,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),
+        PINGROUP(PWR_I2C_SDA,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),
+        PINGROUP(KB_ROW0,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32bc),
+        PINGROUP(KB_ROW1,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c0),
+        PINGROUP(KB_ROW2,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c4),
+        PINGROUP(KB_ROW3,         SYS,      KBC,        INVALID,    RSVD2,      INVALID,    RSVD,       INPUT,  0x32c8),
+        PINGROUP(KB_ROW4,         SYS,      KBC,        INVALID,    TRACE,      RSVD3,      RSVD,       INPUT,  0x32cc),
+        PINGROUP(KB_ROW5,         SYS,      KBC,        INVALID,    TRACE,      OWR,        RSVD,       INPUT,  0x32d0),
+        PINGROUP(KB_ROW6,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d4),
+        PINGROUP(KB_ROW7,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d8),
+        PINGROUP(KB_ROW8,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32dc),
+        PINGROUP(KB_ROW9,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e0),
+        PINGROUP(KB_ROW10,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e4),
+        PINGROUP(KB_ROW11,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e8),
+        PINGROUP(KB_ROW12,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32ec),
+        PINGROUP(KB_ROW13,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f0),
+        PINGROUP(KB_ROW14,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f4),
+        PINGROUP(KB_ROW15,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f8),
+        PINGROUP(KB_COL0,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x32fc),
+        PINGROUP(KB_COL1,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3300),
+        PINGROUP(KB_COL2,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3304),
+        PINGROUP(KB_COL3,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3308),
+        PINGROUP(KB_COL4,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x330c),
+        PINGROUP(KB_COL5,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3310),
+        PINGROUP(KB_COL6,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3314),
+        PINGROUP(KB_COL7,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3318),
+        PINGROUP(CLK_32K_OUT,     SYS,      BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),
+        PINGROUP(SYS_CLK_REQ,     SYS,      SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),
+        PINGROUP(CORE_PWR_REQ,    SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),
+        PINGROUP(CPU_PWR_REQ,     SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),
+        PINGROUP(PWR_INT_N,       SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),
+        PINGROUP(CLK_32K_IN,      SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),
+        PINGROUP(OWR,             SYS,      OWR,        RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),
+        PINGROUP(DAP1_FS,         AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3338),
+        PINGROUP(DAP1_DIN,        AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x333c),
+        PINGROUP(DAP1_DOUT,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3340),
+        PINGROUP(DAP1_SCLK,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3344),
+        PINGROUP(CLK1_REQ,        AUDIO,    DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),
+        PINGROUP(CLK1_OUT,        AUDIO,    EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),
+        PINGROUP(SPDIF_IN,        AUDIO,    SPDIF,      HDA,        INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3350),
+        PINGROUP(SPDIF_OUT,       AUDIO,    SPDIF,      RSVD1,      INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3354),
+        PINGROUP(DAP2_FS,         AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3358),
+        PINGROUP(DAP2_DIN,        AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x335c),
+        PINGROUP(DAP2_DOUT,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3360),
+        PINGROUP(DAP2_SCLK,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3364),
+        PINGROUP(SPI2_MOSI,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3368),
+        PINGROUP(SPI2_MISO,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x336c),
+        PINGROUP(SPI2_CS0_N,      AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3370),
+        PINGROUP(SPI2_SCK,        AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3374),
+        PINGROUP(SPI1_MOSI,       AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3378),
+        PINGROUP(SPI1_SCK,        AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),
+        PINGROUP(SPI1_CS0_N,      AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),
+        PINGROUP(SPI1_MISO,       AUDIO,    INVALID,    SPI1,       INVALID,    RSVD3,      RSVD,       INPUT,  0x3384),
+        PINGROUP(SPI2_CS1_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x3388),
+        PINGROUP(SPI2_CS2_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x338c),
+        PINGROUP(SDMMC3_CLK,      SDMMC3,   UARTA,      PWM2,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3390),
+        PINGROUP(SDMMC3_CMD,      SDMMC3,   UARTA,      PWM3,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3394),
+        PINGROUP(SDMMC3_DAT0,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x3398),
+        PINGROUP(SDMMC3_DAT1,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x339c),
+        PINGROUP(SDMMC3_DAT2,     SDMMC3,   RSVD,       PWM1,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a0),
+        PINGROUP(SDMMC3_DAT3,     SDMMC3,   RSVD,       PWM0,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a4),
+        PINGROUP(SDMMC3_DAT4,     SDMMC3,   PWM1,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33a8),
+        PINGROUP(SDMMC3_DAT5,     SDMMC3,   PWM0,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33ac),
+        PINGROUP(SDMMC3_DAT6,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b0),
+        PINGROUP(SDMMC3_DAT7,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b4),
+        PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33b8),
+        PINGROUP(PEX_L0_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33bc),
+        PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c0),
+        PINGROUP(PEX_WAKE_N,      PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c4),
+        PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c8),
+        PINGROUP(PEX_L1_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33cc),
+        PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d0),
+        PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d4),
+        PINGROUP(PEX_L2_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d8),
+        PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33dc),
+        PINGROUP(HDMI_CEC,        SYS,      CEC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),
+};
+
+void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
+                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
+                int *pgdrive_max)
+{
+        *pg = tegra_soc_pingroups;
+        *pg_max = TEGRA_MAX_PINGROUP;
+        *pgdrive = tegra_soc_drive_pingroups;
+        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
+}
+
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 1d201650d7a4..ac35d2b76850 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -21,6 +21,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_device.h>
 
 #include <mach/iomap.h>
 #include <mach/pinmux.h>
@@ -33,8 +34,10 @@
 #define SLWR(reg)       (((reg) >> 28) & 0x3)
 #define SLWF(reg)       (((reg) >> 30) & 0x3)
 
-static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
-static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
+static const struct tegra_pingroup_desc *pingroups;
+static const struct tegra_drive_pingroup_desc *drive_pingroups;
+static int pingroup_max;
+static int drive_max;
 
 static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
         [TEGRA_MUX_VI] = "VI",
         [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
         [TEGRA_MUX_XIO] = "XIO",
+        [TEGRA_MUX_BLINK] = "BLINK",
+        [TEGRA_MUX_CEC] = "CEC",
+        [TEGRA_MUX_CLK12] = "CLK12",
+        [TEGRA_MUX_DAP] = "DAP",
+        [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
+        [TEGRA_MUX_DDR] = "DDR",
+        [TEGRA_MUX_DEV3] = "DEV3",
+        [TEGRA_MUX_DTV] = "DTV",
+        [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
+        [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
+        [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
+        [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
+        [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
+        [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
+        [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
+        [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
+        [TEGRA_MUX_HDA] = "HDA",
+        [TEGRA_MUX_HSI] = "HSI",
+        [TEGRA_MUX_I2C4] = "I2C4",
+        [TEGRA_MUX_I2C5] = "I2C5",
+        [TEGRA_MUX_I2CPWR] = "I2CPWR",
+        [TEGRA_MUX_I2S0] = "I2S0",
+        [TEGRA_MUX_I2S1] = "I2S1",
+        [TEGRA_MUX_I2S2] = "I2S2",
+        [TEGRA_MUX_I2S3] = "I2S3",
+        [TEGRA_MUX_I2S4] = "I2S4",
+        [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
+        [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
+        [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
+        [TEGRA_MUX_PWM0] = "PWM0",
+        [TEGRA_MUX_PWM1] = "PWM2",
+        [TEGRA_MUX_PWM2] = "PWM2",
+        [TEGRA_MUX_PWM3] = "PWM3",
+        [TEGRA_MUX_SATA] = "SATA",
+        [TEGRA_MUX_SPI5] = "SPI5",
+        [TEGRA_MUX_SPI6] = "SPI6",
+        [TEGRA_MUX_SYSCLK] = "SYSCLK",
+        [TEGRA_MUX_VGP1] = "VGP1",
+        [TEGRA_MUX_VGP2] = "VGP2",
+        [TEGRA_MUX_VGP3] = "VGP3",
+        [TEGRA_MUX_VGP4] = "VGP4",
+        [TEGRA_MUX_VGP5] = "VGP5",
+        [TEGRA_MUX_VGP6] = "VGP6",
         [TEGRA_MUX_SAFE] = "<safe>",
 };
 
@@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
 
 static DEFINE_SPINLOCK(mux_lock);
 
-static const char *pingroup_name(enum tegra_pingroup pg)
+static const char *pingroup_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return "<UNKNOWN>";
 
         return pingroups[pg].name;
@@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         int i;
         unsigned long reg;
         unsigned long flags;
-        enum tegra_pingroup pg = config->pingroup;
+        int pg = config->pingroup;
         enum tegra_mux_func func = config->func;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].mux_reg < 0)
@@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
         return 0;
 }
 
-int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
-        enum tegra_tristate tristate)
+int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].tri_reg < 0)
@@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
         return 0;
 }
 
-int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
-        enum tegra_pullupdown pupd)
+int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
 {
         unsigned long reg;
         unsigned long flags;
 
-        if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+        if (pg < 0 || pg >=  pingroup_max)
                 return -ERANGE;
 
         if (pingroups[pg].pupd_reg < 0)
@@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
 
 static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
 {
-        enum tegra_pingroup pingroup = config->pingroup;
+        int pingroup = config->pingroup;
         enum tegra_mux_func func     = config->func;
         enum tegra_pullupdown pupd   = config->pupd;
         enum tegra_tristate tristate = config->tristate;
@@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l
                 tegra_pinmux_config_pingroup(&config[i]);
 }
 
-static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
+static const char *drive_pinmux_name(int pg)
 {
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return "<UNKNOWN>";
 
         return drive_pingroups[pg].name;
@@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val)
         return tegra_slew_names[val];
 }
 
-static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
-        enum tegra_hsm hsm)
+static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
@@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
-        enum tegra_schmitt schmitt)
+static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
@@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
-        enum tegra_drive drive)
+static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
@@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_down(int pg,
         enum tegra_pull_strength pull_down)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
@@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_pull_up(int pg,
         enum tegra_pull_strength pull_up)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
@@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_rising(int pg,
         enum tegra_slew slew_rising)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
@@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
+static int tegra_drive_pinmux_set_slew_falling(int pg,
         enum tegra_slew slew_falling)
 {
         unsigned long flags;
         u32 reg;
-        if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+        if (pg < 0 || pg >=  drive_max)
                 return -ERANGE;
 
         if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
@@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
         return 0;
 }
 
-static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
+static void tegra_drive_pinmux_config_pingroup(int pingroup,
                                           enum tegra_hsm hsm,
                                           enum tegra_schmitt schmitt,
                                           enum tegra_drive drive,
@@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf
         for (i = 0; i < len; i++) {
                 int err;
                 c = config[i];
-                if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
+                if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config
         for (i = 0; i < len; i++) {
                 int err;
                 if (config[i].pingroup < 0 ||
-                    config[i].pingroup >= TEGRA_MAX_PINGROUP) {
+                    config[i].pingroup >= pingroup_max) {
                         WARN_ON(1);
                         continue;
                 }
@@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
 {
         int i;
         int err;
-        enum tegra_pingroup pingroup;
+        int pingroup;
 
         for (i = 0; i < len; i++) {
                 pingroup = config[i].pingroup;
@@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
         }
 }
 
+static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
+#endif
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+        { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
+#endif
+        { },
+};
+
 static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
 {
         struct resource *res;
         int i;
         int config_bad = 0;
+        const struct of_device_id *match;
+
+        match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
+
+        if (match)
+                ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
+                        &drive_pingroups, &drive_max);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        else
+                /* no device tree available, so we must be on tegra20 */
+                tegra20_pinmux_init(&pingroups, &pingroup_max,
+                                        &drive_pingroups, &drive_max);
+#else
+        pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
+#endif
 
         for (i = 0; ; i++) {
                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         }
         nbanks = i;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 if (pingroups[i].tri_bank >= nbanks) {
                         dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
                         config_bad = 1;
@@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
                 }
         }
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 if (drive_pingroups[i].reg_bank >= nbanks) {
                         dev_err(&pdev->dev,
                                 "drive pingroup %d: bad reg_bank\n", i);
@@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
         return 0;
 }
 
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-        { .compatible = "nvidia,tegra20-pinmux", },
-        { },
-};
-
 static struct platform_driver tegra_pinmux_driver = {
         .driver         = {
                 .name   = "tegra-pinmux",
@@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+        for (i = 0; i < pingroup_max; i++) {
                 unsigned long reg;
                 unsigned long tri;
                 unsigned long mux;
@@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
         int i;
         int len;
 
-        for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+        for (i = 0; i < drive_max; i++) {
                 u32 reg;
 
                 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 371869d8ea01..ff9e6b6c0460 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
 #define pmc_readl(reg) \
         __raw_readl(reg_pmc_base + (reg))
 
-unsigned long clk_measure_input_freq(void)
+static unsigned long clk_measure_input_freq(void)
 {
         u32 clock_autodetect;
         clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
         .disable        = tegra2_clk_m_disable,
 };
 
-void tegra2_periph_reset_assert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, true);
-}
-
-void tegra2_periph_reset_deassert(struct clk *c)
-{
-        BUG_ON(!c->ops->reset);
-        c->ops->reset(c, false);
-}
-
 /* super clock functions */
 /* "super clocks" on tegra have two-stage muxes and a clock skipping
  * super divider.  We will ignore the clock skipping divider, since we
@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
 {
         u32 reg;
+        unsigned long flags;
+
+        spin_lock_irqsave(&c->spinlock, flags);
 
         delay = clamp(delay, 0, 15);
         reg = clk_readl(c->reg);
@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
         reg |= SDMMC_CLK_INT_FB_SEL;
         reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
         clk_writel(reg, c->reg);
+
+        spin_unlock_irqrestore(&c->spinlock, flags);
 }
 
 /* External memory controller clock ops */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index e2272d263a83..1d1acda4f3e0 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -19,7 +19,6 @@
 
 #include <linux/init.h>
 #include <linux/err.h>
-#include <linux/sched.h>
 #include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -106,25 +105,9 @@ static struct clock_event_device tegra_clockevent = {
         .set_mode       = tegra_timer_set_mode,
 };
 
-static DEFINE_CLOCK_DATA(cd);
-
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
- * This gives a resolution of about 1us and a wrap period of about 1h11min.
- */
-#define SC_MULT         4194304000u
-#define SC_SHIFT        22
-
-unsigned long long notrace sched_clock(void)
+static u32 notrace tegra_read_sched_clock(void)
 {
-        u32 cyc = timer_readl(TIMERUS_CNTR_1US);
-        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
-
-static void notrace tegra_update_sched_clock(void)
-{
-        u32 cyc = timer_readl(TIMERUS_CNTR_1US);
-        update_sched_clock(&cd, cyc, (u32)~0);
+        return timer_readl(TIMERUS_CNTR_1US);
 }
 
 /*
@@ -182,20 +165,28 @@ static struct irqaction tegra_timer_irq = {
 static void __init tegra_init_timer(void)
 {
         struct clk *clk;
-        unsigned long rate = clk_measure_input_freq();
+        unsigned long rate;
         int ret;
 
         clk = clk_get_sys("timer", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk)) {
+                pr_warn("Unable to get timer clock."
+                        " Assuming 12Mhz input clock.\n");
+                rate = 12000000;
+        } else {
+                clk_enable(clk);
+                rate = clk_get_rate(clk);
+        }
 
         /*
          * rtc registers are used by read_persistent_clock, keep the rtc clock
          * enabled
          */
         clk = clk_get_sys("rtc-tegra", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        if (IS_ERR(clk))
+                pr_warn("Unable to get rtc-tegra clock\n");
+        else
+                clk_enable(clk);
 
 #ifdef CONFIG_HAVE_ARM_TWD
         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
@@ -218,8 +209,7 @@ static void __init tegra_init_timer(void)
                 WARN(1, "Unknown clock rate");
         }
 
-        init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
-                               1000000, SC_MULT, SC_SHIFT);
+        setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
 
         if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
                 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {