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-rw-r--r--arch/arm/mach-tegra/board-dt.c2
-rw-r--r--arch/arm/mach-tegra/board-harmony.c2
-rw-r--r--arch/arm/mach-tegra/board-paz00.c2
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c4
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c2
-rw-r--r--arch/arm/mach-tegra/include/mach/entry-macro.S22
-rw-r--r--arch/arm/mach-tegra/include/mach/io.h6
-rw-r--r--arch/arm/mach-tegra/include/mach/vmalloc.h28
-rw-r--r--arch/arm/mach-tegra/io.c21
-rw-r--r--arch/arm/mach-tegra/timer.c24
10 files changed, 17 insertions, 96 deletions
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 74743ad3d2d3..f6f03ce340fc 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -32,6 +32,7 @@
32#include <linux/i2c.h> 32#include <linux/i2c.h>
33#include <linux/i2c-tegra.h> 33#include <linux/i2c-tegra.h>
34 34
35#include <asm/hardware/gic.h>
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
37#include <asm/mach/time.h> 38#include <asm/mach/time.h>
@@ -130,6 +131,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
130 .map_io = tegra_map_common_io, 131 .map_io = tegra_map_common_io,
131 .init_early = tegra_init_early, 132 .init_early = tegra_init_early,
132 .init_irq = tegra_init_irq, 133 .init_irq = tegra_init_irq,
134 .handle_irq = gic_handle_irq,
133 .timer = &tegra_timer, 135 .timer = &tegra_timer,
134 .init_machine = tegra_dt_init, 136 .init_machine = tegra_dt_init,
135 .dt_compat = tegra_dt_board_compat, 137 .dt_compat = tegra_dt_board_compat,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index f0bdc5e3fe52..fd190a8dc665 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -31,6 +31,7 @@
31#include <asm/mach-types.h> 31#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
33#include <asm/mach/time.h> 33#include <asm/mach/time.h>
34#include <asm/hardware/gic.h>
34#include <asm/setup.h> 35#include <asm/setup.h>
35 36
36#include <mach/tegra_wm8903_pdata.h> 37#include <mach/tegra_wm8903_pdata.h>
@@ -187,6 +188,7 @@ MACHINE_START(HARMONY, "harmony")
187 .map_io = tegra_map_common_io, 188 .map_io = tegra_map_common_io,
188 .init_early = tegra_init_early, 189 .init_early = tegra_init_early,
189 .init_irq = tegra_init_irq, 190 .init_irq = tegra_init_irq,
191 .handle_irq = gic_handle_irq,
190 .timer = &tegra_timer, 192 .timer = &tegra_timer,
191 .init_machine = tegra_harmony_init, 193 .init_machine = tegra_harmony_init,
192MACHINE_END 194MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 55c55ba89f1e..0b7e1cfee70d 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -29,6 +29,7 @@
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/rfkill-gpio.h> 30#include <linux/rfkill-gpio.h>
31 31
32#include <asm/hardware/gic.h>
32#include <asm/mach-types.h> 33#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
34#include <asm/mach/time.h> 35#include <asm/mach/time.h>
@@ -190,6 +191,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
190 .map_io = tegra_map_common_io, 191 .map_io = tegra_map_common_io,
191 .init_early = tegra_init_early, 192 .init_early = tegra_init_early,
192 .init_irq = tegra_init_irq, 193 .init_irq = tegra_init_irq,
194 .handle_irq = gic_handle_irq,
193 .timer = &tegra_timer, 195 .timer = &tegra_timer,
194 .init_machine = tegra_paz00_init, 196 .init_machine = tegra_paz00_init,
195MACHINE_END 197MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index bf13ea355efc..7328379b1356 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -34,6 +34,7 @@
34 34
35#include <asm/mach-types.h> 35#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
37#include <asm/hardware/gic.h>
37 38
38#include "board.h" 39#include "board.h"
39#include "board-seaboard.h" 40#include "board-seaboard.h"
@@ -284,6 +285,7 @@ MACHINE_START(SEABOARD, "seaboard")
284 .map_io = tegra_map_common_io, 285 .map_io = tegra_map_common_io,
285 .init_early = tegra_init_early, 286 .init_early = tegra_init_early,
286 .init_irq = tegra_init_irq, 287 .init_irq = tegra_init_irq,
288 .handle_irq = gic_handle_irq,
287 .timer = &tegra_timer, 289 .timer = &tegra_timer,
288 .init_machine = tegra_seaboard_init, 290 .init_machine = tegra_seaboard_init,
289MACHINE_END 291MACHINE_END
@@ -293,6 +295,7 @@ MACHINE_START(KAEN, "kaen")
293 .map_io = tegra_map_common_io, 295 .map_io = tegra_map_common_io,
294 .init_early = tegra_init_early, 296 .init_early = tegra_init_early,
295 .init_irq = tegra_init_irq, 297 .init_irq = tegra_init_irq,
298 .handle_irq = gic_handle_irq,
296 .timer = &tegra_timer, 299 .timer = &tegra_timer,
297 .init_machine = tegra_kaen_init, 300 .init_machine = tegra_kaen_init,
298MACHINE_END 301MACHINE_END
@@ -302,6 +305,7 @@ MACHINE_START(WARIO, "wario")
302 .map_io = tegra_map_common_io, 305 .map_io = tegra_map_common_io,
303 .init_early = tegra_init_early, 306 .init_early = tegra_init_early,
304 .init_irq = tegra_init_irq, 307 .init_irq = tegra_init_irq,
308 .handle_irq = gic_handle_irq,
305 .timer = &tegra_timer, 309 .timer = &tegra_timer,
306 .init_machine = tegra_wario_init, 310 .init_machine = tegra_wario_init,
307MACHINE_END 311MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 1a6617b7806f..60a36a2e0be1 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -26,6 +26,7 @@
26#include <linux/i2c.h> 26#include <linux/i2c.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28 28
29#include <asm/hardware/gic.h>
29#include <asm/mach-types.h> 30#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
31#include <asm/setup.h> 32#include <asm/setup.h>
@@ -176,6 +177,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
176 .map_io = tegra_map_common_io, 177 .map_io = tegra_map_common_io,
177 .init_early = tegra_init_early, 178 .init_early = tegra_init_early,
178 .init_irq = tegra_init_irq, 179 .init_irq = tegra_init_irq,
180 .handle_irq = gic_handle_irq,
179 .timer = &tegra_timer, 181 .timer = &tegra_timer,
180 .init_machine = tegra_trimslice_init, 182 .init_machine = tegra_trimslice_init,
181MACHINE_END 183MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c53889d..ac11262149c7 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -12,30 +12,15 @@
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 */ 14 */
15#include <mach/iomap.h>
16#include <mach/io.h>
17
18#if defined(CONFIG_ARM_GIC)
19#define HAVE_GET_IRQNR_PREAMBLE
20#include <asm/hardware/entry-macro-gic.S>
21
22 /* Uses the GIC interrupt controller built into the cpu */
23#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
24 15
25 .macro disable_fiq 16 .macro disable_fiq
26 .endm 17 .endm
27 18
28 .macro get_irqnr_preamble, base, tmp 19 .macro arch_ret_to_user, tmp1, tmp2
29 movw \base, #(ICTRL_BASE & 0x0000ffff)
30 movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
31 .endm 20 .endm
32 21
33 .macro arch_ret_to_user, tmp1, tmp2 22#if !defined(CONFIG_ARM_GIC)
34 .endm
35#else
36 /* legacy interrupt controller for AP16 */ 23 /* legacy interrupt controller for AP16 */
37 .macro disable_fiq
38 .endm
39 24
40 .macro get_irqnr_preamble, base, tmp 25 .macro get_irqnr_preamble, base, tmp
41 @ enable imprecise aborts 26 @ enable imprecise aborts
@@ -46,9 +31,6 @@
46 orr \base, #0x0000f000 31 orr \base, #0x0000f000
47 .endm 32 .endm
48 33
49 .macro arch_ret_to_user, tmp1, tmp2
50 .endm
51
52 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 34 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
53 ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS 35 ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS
54 cmp \irqnr, #0x80 36 cmp \irqnr, #0x80
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index 35a011fbc42d..f15defffb5d2 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -71,12 +71,6 @@
71 71
72#ifndef __ASSEMBLER__ 72#ifndef __ASSEMBLER__
73 73
74#define __arch_ioremap tegra_ioremap
75#define __arch_iounmap tegra_iounmap
76
77void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
78void tegra_iounmap(volatile void __iomem *addr);
79
80#define IO_ADDRESS(n) (IO_TO_VIRT(n)) 74#define IO_ADDRESS(n) (IO_TO_VIRT(n))
81 75
82#ifdef CONFIG_TEGRA_PCI 76#ifdef CONFIG_TEGRA_PCI
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
deleted file mode 100644
index fd6aa65b2dc6..000000000000
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_VMALLOC_H
22#define __MACH_TEGRA_VMALLOC_H
23
24#include <asm/sizes.h>
25
26#define VMALLOC_END 0xFE000000UL
27
28#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 5489f8b5d6ad..d23ee2db2827 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -60,24 +60,3 @@ void __init tegra_map_common_io(void)
60{ 60{
61 iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); 61 iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
62} 62}
63
64/*
65 * Intercept ioremap() requests for addresses in our fixed mapping regions.
66 */
67void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
68{
69 void __iomem *v = IO_ADDRESS(p);
70 if (v == NULL)
71 v = __arm_ioremap(p, size, type);
72 return v;
73}
74EXPORT_SYMBOL(tegra_ioremap);
75
76void tegra_iounmap(volatile void __iomem *addr)
77{
78 unsigned long virt = (unsigned long)addr;
79
80 if (virt >= VMALLOC_START && virt < VMALLOC_END)
81 __iounmap(addr);
82}
83EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index e2272d263a83..732c724008b1 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -19,7 +19,6 @@
19 19
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/err.h> 21#include <linux/err.h>
22#include <linux/sched.h>
23#include <linux/time.h> 22#include <linux/time.h>
24#include <linux/interrupt.h> 23#include <linux/interrupt.h>
25#include <linux/irq.h> 24#include <linux/irq.h>
@@ -106,25 +105,9 @@ static struct clock_event_device tegra_clockevent = {
106 .set_mode = tegra_timer_set_mode, 105 .set_mode = tegra_timer_set_mode,
107}; 106};
108 107
109static DEFINE_CLOCK_DATA(cd); 108static u32 notrace tegra_read_sched_clock(void)
110
111/*
112 * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
113 * This gives a resolution of about 1us and a wrap period of about 1h11min.
114 */
115#define SC_MULT 4194304000u
116#define SC_SHIFT 22
117
118unsigned long long notrace sched_clock(void)
119{
120 u32 cyc = timer_readl(TIMERUS_CNTR_1US);
121 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
122}
123
124static void notrace tegra_update_sched_clock(void)
125{ 109{
126 u32 cyc = timer_readl(TIMERUS_CNTR_1US); 110 return timer_readl(TIMERUS_CNTR_1US);
127 update_sched_clock(&cd, cyc, (u32)~0);
128} 111}
129 112
130/* 113/*
@@ -218,8 +201,7 @@ static void __init tegra_init_timer(void)
218 WARN(1, "Unknown clock rate"); 201 WARN(1, "Unknown clock rate");
219 } 202 }
220 203
221 init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, 204 setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
222 1000000, SC_MULT, SC_SHIFT);
223 205
224 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, 206 if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
225 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { 207 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {