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-rw-r--r--arch/arm/mach-tegra/Kconfig31
-rw-r--r--arch/arm/mach-tegra/Makefile35
-rw-r--r--arch/arm/mach-tegra/Makefile.boot3
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c (renamed from arch/arm/mach-tegra/board-dt.c)44
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c63
-rw-r--r--arch/arm/mach-tegra/board-harmony-pinmux.c1
-rw-r--r--arch/arm/mach-tegra/board-harmony.c2
-rw-r--r--arch/arm/mach-tegra/board-paz00-pinmux.c1
-rw-r--r--arch/arm/mach-tegra/board-paz00.c2
-rw-r--r--arch/arm/mach-tegra/board-seaboard-pinmux.c2
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c6
-rw-r--r--arch/arm/mach-tegra/board-trimslice-pinmux.c1
-rw-r--r--arch/arm/mach-tegra/board-trimslice.c2
-rw-r--r--arch/arm/mach-tegra/board.h5
-rw-r--r--arch/arm/mach-tegra/clock.c25
-rw-r--r--arch/arm/mach-tegra/clock.h4
-rw-r--r--arch/arm/mach-tegra/common.c55
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra20.h (renamed from arch/arm/mach-tegra/include/mach/pinmux-t2.h)6
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux-tegra30.h320
-rw-r--r--arch/arm/mach-tegra/include/mach/pinmux.h88
-rw-r--r--arch/arm/mach-tegra/irq.c10
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra20-tables.c (renamed from arch/arm/mach-tegra/pinmux-t2-tables.c)24
-rw-r--r--arch/arm/mach-tegra/pinmux-tegra30-tables.c376
-rw-r--r--arch/arm/mach-tegra/pinmux.c153
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c19
-rw-r--r--arch/arm/mach-tegra/timer.c18
28 files changed, 1122 insertions, 178 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 91aff7cb8284..373652d76b90 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,11 +2,8 @@ if ARCH_TEGRA
2 2
3comment "NVIDIA Tegra options" 3comment "NVIDIA Tegra options"
4 4
5choice
6 prompt "Select Tegra processor family for target system"
7
8config ARCH_TEGRA_2x_SOC 5config ARCH_TEGRA_2x_SOC
9 bool "Tegra 2 family" 6 bool "Enable support for Tegra20 family"
10 select CPU_V7 7 select CPU_V7
11 select ARM_GIC 8 select ARM_GIC
12 select ARCH_REQUIRE_GPIOLIB 9 select ARCH_REQUIRE_GPIOLIB
@@ -17,22 +14,36 @@ config ARCH_TEGRA_2x_SOC
17 Support for NVIDIA Tegra AP20 and T20 processors, based on the 14 Support for NVIDIA Tegra AP20 and T20 processors, based on the
18 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 15 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
19 16
20endchoice 17config ARCH_TEGRA_3x_SOC
18 bool "Enable support for Tegra30 family"
19 select CPU_V7
20 select ARM_GIC
21 select ARCH_REQUIRE_GPIOLIB
22 select USB_ARCH_HAS_EHCI if USB_SUPPORT
23 select USB_ULPI if USB_SUPPORT
24 select USB_ULPI_VIEWPORT if USB_SUPPORT
25 select USE_OF
26 help
27 Support for NVIDIA Tegra T30 processor family, based on the
28 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
21 29
22config TEGRA_PCI 30config TEGRA_PCI
23 bool "PCI Express support" 31 bool "PCI Express support"
32 depends on ARCH_TEGRA_2x_SOC
24 select PCI 33 select PCI
25 34
26comment "Tegra board type" 35comment "Tegra board type"
27 36
28config MACH_HARMONY 37config MACH_HARMONY
29 bool "Harmony board" 38 bool "Harmony board"
39 depends on ARCH_TEGRA_2x_SOC
30 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 40 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
31 help 41 help
32 Support for nVidia Harmony development platform 42 Support for nVidia Harmony development platform
33 43
34config MACH_KAEN 44config MACH_KAEN
35 bool "Kaen board" 45 bool "Kaen board"
46 depends on ARCH_TEGRA_2x_SOC
36 select MACH_SEABOARD 47 select MACH_SEABOARD
37 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 48 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
38 help 49 help
@@ -40,11 +51,13 @@ config MACH_KAEN
40 51
41config MACH_PAZ00 52config MACH_PAZ00
42 bool "Paz00 board" 53 bool "Paz00 board"
54 depends on ARCH_TEGRA_2x_SOC
43 help 55 help
44 Support for the Toshiba AC100/Dynabook AZ netbook 56 Support for the Toshiba AC100/Dynabook AZ netbook
45 57
46config MACH_SEABOARD 58config MACH_SEABOARD
47 bool "Seaboard board" 59 bool "Seaboard board"
60 depends on ARCH_TEGRA_2x_SOC
48 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC 61 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
49 help 62 help
50 Support for nVidia Seaboard development platform. It will 63 Support for nVidia Seaboard development platform. It will
@@ -52,25 +65,29 @@ config MACH_SEABOARD
52 have large similarities with the seaboard design. 65 have large similarities with the seaboard design.
53 66
54config MACH_TEGRA_DT 67config MACH_TEGRA_DT
55 bool "Generic Tegra board (FDT support)" 68 bool "Generic Tegra20 board (FDT support)"
69 depends on ARCH_TEGRA_2x_SOC
56 select USE_OF 70 select USE_OF
57 help 71 help
58 Support for generic nVidia Tegra boards using Flattened Device Tree 72 Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
59 73
60config MACH_TRIMSLICE 74config MACH_TRIMSLICE
61 bool "TrimSlice board" 75 bool "TrimSlice board"
76 depends on ARCH_TEGRA_2x_SOC
62 select TEGRA_PCI 77 select TEGRA_PCI
63 help 78 help
64 Support for CompuLab TrimSlice platform 79 Support for CompuLab TrimSlice platform
65 80
66config MACH_WARIO 81config MACH_WARIO
67 bool "Wario board" 82 bool "Wario board"
83 depends on ARCH_TEGRA_2x_SOC
68 select MACH_SEABOARD 84 select MACH_SEABOARD
69 help 85 help
70 Support for the Wario version of Seaboard 86 Support for the Wario version of Seaboard
71 87
72config MACH_VENTANA 88config MACH_VENTANA
73 bool "Ventana board" 89 bool "Ventana board"
90 depends on ARCH_TEGRA_2x_SOC
74 select MACH_TEGRA_DT 91 select MACH_TEGRA_DT
75 help 92 help
76 Support for the nVidia Ventana development platform 93 Support for the nVidia Ventana development platform
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e98c49aabd10..e120ff54f663 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -6,12 +6,13 @@ obj-y += irq.o
6obj-y += clock.o 6obj-y += clock.o
7obj-y += timer.o 7obj-y += timer.o
8obj-y += pinmux.o 8obj-y += pinmux.o
9obj-y += powergate.o
10obj-y += fuse.o 9obj-y += fuse.o
11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clock.o 10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
12obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o 11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 12obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-t2-tables.o 13obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
14obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
15obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
15obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o 16obj-$(CONFIG_SMP) += platsmp.o localtimer.o headsmp.o
16obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
17obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o 18obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o
@@ -19,20 +20,22 @@ obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
19obj-$(CONFIG_TEGRA_PCI) += pcie.o 20obj-$(CONFIG_TEGRA_PCI) += pcie.o
20obj-$(CONFIG_USB_SUPPORT) += usb_phy.o 21obj-$(CONFIG_USB_SUPPORT) += usb_phy.o
21 22
22obj-${CONFIG_MACH_HARMONY} += board-harmony.o 23obj-$(CONFIG_MACH_HARMONY) += board-harmony.o
23obj-${CONFIG_MACH_HARMONY} += board-harmony-pinmux.o 24obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o
24obj-${CONFIG_MACH_HARMONY} += board-harmony-pcie.o 25obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o
25obj-${CONFIG_MACH_HARMONY} += board-harmony-power.o 26obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o
26 27
27obj-${CONFIG_MACH_PAZ00} += board-paz00.o 28obj-$(CONFIG_MACH_PAZ00) += board-paz00.o
28obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o 29obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
29 30
30obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o 31obj-$(CONFIG_MACH_SEABOARD) += board-seaboard.o
31obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o 32obj-$(CONFIG_MACH_SEABOARD) += board-seaboard-pinmux.o
32 33
33obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o 34obj-$(CONFIG_MACH_TEGRA_DT) += board-dt-tegra20.o
34obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o 35obj-$(CONFIG_MACH_TEGRA_DT) += board-harmony-pinmux.o
35obj-${CONFIG_MACH_TEGRA_DT} += board-seaboard-pinmux.o 36obj-$(CONFIG_MACH_TEGRA_DT) += board-seaboard-pinmux.o
37obj-$(CONFIG_MACH_TEGRA_DT) += board-paz00-pinmux.o
38obj-$(CONFIG_MACH_TEGRA_DT) += board-trimslice-pinmux.o
36 39
37obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o 40obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
38obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o 41obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index bd12c9fb81e8..9a82094092d7 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,5 +3,8 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 3initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
4 4
5dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb 5dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
6dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
6dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb 7dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
8dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
7dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb 9dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
10dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 86237b641060..70f060251f00 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -37,6 +37,7 @@
37#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
38#include <asm/mach/time.h> 38#include <asm/mach/time.h>
39#include <asm/setup.h> 39#include <asm/setup.h>
40#include <asm/hardware/gic.h>
40 41
41#include <mach/iomap.h> 42#include <mach/iomap.h>
42#include <mach/irqs.h> 43#include <mach/irqs.h>
@@ -47,7 +48,9 @@
47#include "devices.h" 48#include "devices.h"
48 49
49void harmony_pinmux_init(void); 50void harmony_pinmux_init(void);
51void paz00_pinmux_init(void);
50void seaboard_pinmux_init(void); 52void seaboard_pinmux_init(void);
53void trimslice_pinmux_init(void);
51void ventana_pinmux_init(void); 54void ventana_pinmux_init(void);
52 55
53struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 56struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
@@ -62,14 +65,28 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
62 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), 65 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
63 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), 66 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
64 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), 67 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
65 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), 68 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
66 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), 69 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
70 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
71 &tegra_ehci1_device.dev.platform_data),
72 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
73 &tegra_ehci2_device.dev.platform_data),
74 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
75 &tegra_ehci3_device.dev.platform_data),
67 {} 76 {}
68}; 77};
69 78
70static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 79static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
71 /* name parent rate enabled */ 80 /* name parent rate enabled */
72 { "uartd", "pll_p", 216000000, true }, 81 { "uartd", "pll_p", 216000000, true },
82 { "usbd", "clk_m", 12000000, false },
83 { "usb2", "clk_m", 12000000, false },
84 { "usb3", "clk_m", 12000000, false },
85 { "pll_a", "pll_p_out1", 56448000, true },
86 { "pll_a_out0", "pll_a", 11289600, true },
87 { "cdev1", NULL, 0, true },
88 { "i2s1", "pll_a_out0", 11289600, false},
89 { "i2s2", "pll_a_out0", 11289600, false},
73 { NULL, NULL, 0, 0}, 90 { NULL, NULL, 0, 0},
74}; 91};
75 92
@@ -78,30 +95,21 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
78 {} 95 {}
79}; 96};
80 97
81static struct of_device_id tegra_dt_gic_match[] __initdata = {
82 { .compatible = "nvidia,tegra20-gic", },
83 {}
84};
85
86static struct { 98static struct {
87 char *machine; 99 char *machine;
88 void (*init)(void); 100 void (*init)(void);
89} pinmux_configs[] = { 101} pinmux_configs[] = {
102 { "compulab,trimslice", trimslice_pinmux_init },
90 { "nvidia,harmony", harmony_pinmux_init }, 103 { "nvidia,harmony", harmony_pinmux_init },
104 { "compal,paz00", paz00_pinmux_init },
91 { "nvidia,seaboard", seaboard_pinmux_init }, 105 { "nvidia,seaboard", seaboard_pinmux_init },
92 { "nvidia,ventana", ventana_pinmux_init }, 106 { "nvidia,ventana", ventana_pinmux_init },
93}; 107};
94 108
95static void __init tegra_dt_init(void) 109static void __init tegra_dt_init(void)
96{ 110{
97 struct device_node *node;
98 int i; 111 int i;
99 112
100 node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
101 TEGRA_ARM_INT_DIST_BASE);
102 if (node)
103 irq_domain_add_simple(node, INT_GIC_BASE);
104
105 tegra_clk_init_from_table(tegra_dt_clk_init_table); 113 tegra_clk_init_from_table(tegra_dt_clk_init_table);
106 114
107 for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) { 115 for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
@@ -122,19 +130,21 @@ static void __init tegra_dt_init(void)
122 tegra20_auxdata_lookup, NULL); 130 tegra20_auxdata_lookup, NULL);
123} 131}
124 132
125static const char * tegra_dt_board_compat[] = { 133static const char *tegra20_dt_board_compat[] = {
134 "compulab,trimslice",
126 "nvidia,harmony", 135 "nvidia,harmony",
136 "compal,paz00",
127 "nvidia,seaboard", 137 "nvidia,seaboard",
128 "nvidia,ventana", 138 "nvidia,ventana",
129 NULL 139 NULL
130}; 140};
131 141
132DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") 142DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
133 .map_io = tegra_map_common_io, 143 .map_io = tegra_map_common_io,
134 .init_early = tegra_init_early, 144 .init_early = tegra20_init_early,
135 .init_irq = tegra_init_irq, 145 .init_irq = tegra_dt_init_irq,
136 .handle_irq = gic_handle_irq, 146 .handle_irq = gic_handle_irq,
137 .timer = &tegra_timer, 147 .timer = &tegra_timer,
138 .init_machine = tegra_dt_init, 148 .init_machine = tegra_dt_init,
139 .dt_compat = tegra_dt_board_compat, 149 .dt_compat = tegra20_dt_board_compat,
140MACHINE_END 150MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
new file mode 100644
index 000000000000..3c197e2440b7
--- /dev/null
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -0,0 +1,63 @@
1/*
2 * arch/arm/mach-tegra/board-dt-tegra30.c
3 *
4 * NVIDIA Tegra30 device tree board support
5 *
6 * Copyright (C) 2011 NVIDIA Corporation
7 *
8 * Derived from:
9 *
10 * arch/arm/mach-tegra/board-dt-tegra20.c
11 *
12 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
13 * Copyright (C) 2010 Google, Inc.
14 *
15 * This software is licensed under the terms of the GNU General Public
16 * License version 2, as published by the Free Software Foundation, and
17 * may be copied, distributed, and modified under those terms.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_fdt.h>
30#include <linux/of_irq.h>
31#include <linux/of_platform.h>
32
33#include <asm/mach/arch.h>
34#include <asm/hardware/gic.h>
35
36#include "board.h"
37
38static struct of_device_id tegra_dt_match_table[] __initdata = {
39 { .compatible = "simple-bus", },
40 {}
41};
42
43static void __init tegra30_dt_init(void)
44{
45 of_platform_populate(NULL, tegra_dt_match_table,
46 NULL, NULL);
47}
48
49static const char *tegra30_dt_board_compat[] = {
50 "nvidia,cardhu",
51 NULL
52};
53
54DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
55 .map_io = tegra_map_common_io,
56 .init_early = tegra30_init_early,
57 .init_irq = tegra_dt_init_irq,
58 .handle_irq = gic_handle_irq,
59 .timer = &tegra_timer,
60 .init_machine = tegra30_dt_init,
61 .restart = tegra_assert_system_reset,
62 .dt_compat = tegra30_dt_board_compat,
63MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 5038f5b130e6..465808c8ac0b 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20 20
21#include <mach/pinmux.h> 21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
22 23
23#include "gpio-names.h" 24#include "gpio-names.h"
24#include "board-harmony.h" 25#include "board-harmony.h"
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index fd190a8dc665..d60a0d45f2f7 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -186,7 +186,7 @@ MACHINE_START(HARMONY, "harmony")
186 .atag_offset = 0x100, 186 .atag_offset = 0x100,
187 .fixup = tegra_harmony_fixup, 187 .fixup = tegra_harmony_fixup,
188 .map_io = tegra_map_common_io, 188 .map_io = tegra_map_common_io,
189 .init_early = tegra_init_early, 189 .init_early = tegra20_init_early,
190 .init_irq = tegra_init_irq, 190 .init_irq = tegra_init_irq,
191 .handle_irq = gic_handle_irq, 191 .handle_irq = gic_handle_irq,
192 .timer = &tegra_timer, 192 .timer = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index d6b37daf3252..c775572dcea4 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20 20
21#include <mach/pinmux.h> 21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
22 23
23#include "gpio-names.h" 24#include "gpio-names.h"
24#include "board-paz00.h" 25#include "board-paz00.h"
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index e5480b47c8e7..8a5245919456 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -216,7 +216,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
216 .atag_offset = 0x100, 216 .atag_offset = 0x100,
217 .fixup = tegra_paz00_fixup, 217 .fixup = tegra_paz00_fixup,
218 .map_io = tegra_map_common_io, 218 .map_io = tegra_map_common_io,
219 .init_early = tegra_init_early, 219 .init_early = tegra20_init_early,
220 .init_irq = tegra_init_irq, 220 .init_irq = tegra_init_irq,
221 .handle_irq = gic_handle_irq, 221 .handle_irq = gic_handle_irq,
222 .timer = &tegra_timer, 222 .timer = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index a448f29fbbb2..55e7e43a14ad 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -19,7 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20 20
21#include <mach/pinmux.h> 21#include <mach/pinmux.h>
22#include <mach/pinmux-t2.h> 22#include <mach/pinmux-tegra20.h>
23 23
24#include "gpio-names.h" 24#include "gpio-names.h"
25#include "board-pinmux.h" 25#include "board-pinmux.h"
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 7328379b1356..b79f9ce9941c 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -283,7 +283,7 @@ static void __init tegra_wario_init(void)
283MACHINE_START(SEABOARD, "seaboard") 283MACHINE_START(SEABOARD, "seaboard")
284 .atag_offset = 0x100, 284 .atag_offset = 0x100,
285 .map_io = tegra_map_common_io, 285 .map_io = tegra_map_common_io,
286 .init_early = tegra_init_early, 286 .init_early = tegra20_init_early,
287 .init_irq = tegra_init_irq, 287 .init_irq = tegra_init_irq,
288 .handle_irq = gic_handle_irq, 288 .handle_irq = gic_handle_irq,
289 .timer = &tegra_timer, 289 .timer = &tegra_timer,
@@ -293,7 +293,7 @@ MACHINE_END
293MACHINE_START(KAEN, "kaen") 293MACHINE_START(KAEN, "kaen")
294 .atag_offset = 0x100, 294 .atag_offset = 0x100,
295 .map_io = tegra_map_common_io, 295 .map_io = tegra_map_common_io,
296 .init_early = tegra_init_early, 296 .init_early = tegra20_init_early,
297 .init_irq = tegra_init_irq, 297 .init_irq = tegra_init_irq,
298 .handle_irq = gic_handle_irq, 298 .handle_irq = gic_handle_irq,
299 .timer = &tegra_timer, 299 .timer = &tegra_timer,
@@ -303,7 +303,7 @@ MACHINE_END
303MACHINE_START(WARIO, "wario") 303MACHINE_START(WARIO, "wario")
304 .atag_offset = 0x100, 304 .atag_offset = 0x100,
305 .map_io = tegra_map_common_io, 305 .map_io = tegra_map_common_io,
306 .init_early = tegra_init_early, 306 .init_early = tegra20_init_early,
307 .init_irq = tegra_init_irq, 307 .init_irq = tegra_init_irq,
308 .handle_irq = gic_handle_irq, 308 .handle_irq = gic_handle_irq,
309 .timer = &tegra_timer, 309 .timer = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index 1b3ccec45ea5..a21a2be57cb6 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -19,6 +19,7 @@
19#include <linux/of.h> 19#include <linux/of.h>
20 20
21#include <mach/pinmux.h> 21#include <mach/pinmux.h>
22#include <mach/pinmux-tegra20.h>
22 23
23#include "gpio-names.h" 24#include "gpio-names.h"
24#include "board-pinmux.h" 25#include "board-pinmux.h"
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 60a36a2e0be1..4a197a20be93 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -175,7 +175,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
175 .atag_offset = 0x100, 175 .atag_offset = 0x100,
176 .fixup = tegra_trimslice_fixup, 176 .fixup = tegra_trimslice_fixup,
177 .map_io = tegra_map_common_io, 177 .map_io = tegra_map_common_io,
178 .init_early = tegra_init_early, 178 .init_early = tegra20_init_early,
179 .init_irq = tegra_init_irq, 179 .init_irq = tegra_init_irq,
180 .handle_irq = gic_handle_irq, 180 .handle_irq = gic_handle_irq,
181 .timer = &tegra_timer, 181 .timer = &tegra_timer,
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1d14df7eb7de..75d1543d77c0 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -25,10 +25,11 @@
25 25
26void tegra_assert_system_reset(char mode, const char *cmd); 26void tegra_assert_system_reset(char mode, const char *cmd);
27 27
28void __init tegra_init_early(void); 28void __init tegra20_init_early(void);
29void __init tegra30_init_early(void);
29void __init tegra_map_common_io(void); 30void __init tegra_map_common_io(void);
30void __init tegra_init_irq(void); 31void __init tegra_init_irq(void);
31void __init tegra_init_clock(void); 32void __init tegra_dt_init_irq(void);
32int __init tegra_pcie_init(bool init_port0, bool init_port1); 33int __init tegra_pcie_init(bool init_port0, bool init_port1);
33 34
34extern struct sys_timer tegra_timer; 35extern struct sys_timer tegra_timer;
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca9..8337068a4abe 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
387 387
388void tegra_periph_reset_deassert(struct clk *c) 388void tegra_periph_reset_deassert(struct clk *c)
389{ 389{
390 tegra2_periph_reset_deassert(c); 390 BUG_ON(!c->ops->reset);
391 c->ops->reset(c, false);
391} 392}
392EXPORT_SYMBOL(tegra_periph_reset_deassert); 393EXPORT_SYMBOL(tegra_periph_reset_deassert);
393 394
394void tegra_periph_reset_assert(struct clk *c) 395void tegra_periph_reset_assert(struct clk *c)
395{ 396{
396 tegra2_periph_reset_assert(c); 397 BUG_ON(!c->ops->reset);
398 c->ops->reset(c, true);
397} 399}
398EXPORT_SYMBOL(tegra_periph_reset_assert); 400EXPORT_SYMBOL(tegra_periph_reset_assert);
399 401
400void __init tegra_init_clock(void)
401{
402 tegra2_init_clocks();
403}
404
405/*
406 * The SDMMC controllers have extra bits in the clock source register that
407 * adjust the delay between the clock and data to compenstate for delays
408 * on the PCB.
409 */
410void tegra_sdmmc_tap_delay(struct clk *c, int delay)
411{
412 unsigned long flags;
413
414 spin_lock_irqsave(&c->spinlock, flags);
415 tegra2_sdmmc_tap_delay(c, delay);
416 spin_unlock_irqrestore(&c->spinlock, flags);
417}
418
419#ifdef CONFIG_DEBUG_FS 402#ifdef CONFIG_DEBUG_FS
420 403
421static int __clk_lock_all_spinlocks(void) 404static int __clk_lock_all_spinlocks(void)
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 688316abc64e..5c44106616c5 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -146,15 +146,11 @@ struct tegra_clk_init_table {
146}; 146};
147 147
148void tegra2_init_clocks(void); 148void tegra2_init_clocks(void);
149void tegra2_periph_reset_deassert(struct clk *c);
150void tegra2_periph_reset_assert(struct clk *c);
151void clk_init(struct clk *clk); 149void clk_init(struct clk *clk);
152struct clk *tegra_get_clock_by_name(const char *name); 150struct clk *tegra_get_clock_by_name(const char *name);
153unsigned long clk_measure_input_freq(void);
154int clk_reparent(struct clk *c, struct clk *parent); 151int clk_reparent(struct clk *c, struct clk *parent);
155void tegra_clk_init_from_table(struct tegra_clk_init_table *table); 152void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
156unsigned long clk_get_rate_locked(struct clk *c); 153unsigned long clk_get_rate_locked(struct clk *c);
157int clk_set_rate_locked(struct clk *c, unsigned long rate); 154int clk_set_rate_locked(struct clk *c, unsigned long rate);
158void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
159 155
160#endif 156#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 690b888be506..72b666bd3043 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-tegra/board-harmony.c 2 * arch/arm/mach-tegra/common.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * 5 *
@@ -21,8 +21,10 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of_irq.h>
24 25
25#include <asm/hardware/cache-l2x0.h> 26#include <asm/hardware/cache-l2x0.h>
27#include <asm/hardware/gic.h>
26 28
27#include <mach/iomap.h> 29#include <mach/iomap.h>
28#include <mach/system.h> 30#include <mach/system.h>
@@ -33,18 +35,31 @@
33 35
34void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; 36void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
35 37
38#ifdef CONFIG_OF
39static const struct of_device_id tegra_dt_irq_match[] __initconst = {
40 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
41 { }
42};
43
44void __init tegra_dt_init_irq(void)
45{
46 tegra_init_irq();
47 of_irq_init(tegra_dt_irq_match);
48}
49#endif
50
36void tegra_assert_system_reset(char mode, const char *cmd) 51void tegra_assert_system_reset(char mode, const char *cmd)
37{ 52{
38 void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); 53 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
39 u32 reg; 54 u32 reg;
40 55
41 /* use *_related to avoid spinlock since caches are off */
42 reg = readl_relaxed(reset); 56 reg = readl_relaxed(reset);
43 reg |= 0x04; 57 reg |= 0x10;
44 writel_relaxed(reg, reset); 58 writel_relaxed(reg, reset);
45} 59}
46 60
47static __initdata struct tegra_clk_init_table common_clk_init_table[] = { 61#ifdef CONFIG_ARCH_TEGRA_2x_SOC
62static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
48 /* name parent rate enabled */ 63 /* name parent rate enabled */
49 { "clk_m", NULL, 0, true }, 64 { "clk_m", NULL, 0, true },
50 { "pll_p", "clk_m", 216000000, true }, 65 { "pll_p", "clk_m", 216000000, true },
@@ -60,24 +75,38 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
60 { "cpu", NULL, 0, true }, 75 { "cpu", NULL, 0, true },
61 { NULL, NULL, 0, 0}, 76 { NULL, NULL, 0, 0},
62}; 77};
78#endif
63 79
64static void __init tegra_init_cache(void) 80static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
65{ 81{
66#ifdef CONFIG_CACHE_L2X0 82#ifdef CONFIG_CACHE_L2X0
67 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 83 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
84 u32 aux_ctrl, cache_type;
85
86 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
87 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
68 88
69 writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); 89 cache_type = readl(p + L2X0_CACHE_TYPE);
70 writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); 90 aux_ctrl = (cache_type & 0x700) << (17-8);
91 aux_ctrl |= 0x6C000001;
71 92
72 l2x0_init(p, 0x6C080001, 0x8200c3fe); 93 l2x0_init(p, aux_ctrl, 0x8200c3fe);
73#endif 94#endif
74 95
75} 96}
76 97
77void __init tegra_init_early(void) 98#ifdef CONFIG_ARCH_TEGRA_2x_SOC
99void __init tegra20_init_early(void)
78{ 100{
79 tegra_init_fuse(); 101 tegra_init_fuse();
80 tegra_init_clock(); 102 tegra2_init_clocks();
81 tegra_clk_init_from_table(common_clk_init_table); 103 tegra_clk_init_from_table(tegra20_clk_init_table);
82 tegra_init_cache(); 104 tegra_init_cache(0x331, 0x441);
105}
106#endif
107#ifdef CONFIG_ARCH_TEGRA_3x_SOC
108void __init tegra30_init_early(void)
109{
110 tegra_init_cache(0x441, 0x551);
83} 111}
112#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index c8baf8f80d23..fc3ecb66de08 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -26,6 +26,6 @@ void tegra_periph_reset_deassert(struct clk *c);
26void tegra_periph_reset_assert(struct clk *c); 26void tegra_periph_reset_assert(struct clk *c);
27 27
28unsigned long clk_get_rate_all_locked(struct clk *c); 28unsigned long clk_get_rate_all_locked(struct clk *c);
29void tegra_sdmmc_tap_delay(struct clk *c, int delay); 29void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
30 30
31#endif 31#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index 73265af4dda3..a2146cd6867d 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -25,7 +25,6 @@
25 25
26#define IRQ_LOCALTIMER 29 26#define IRQ_LOCALTIMER 29
27 27
28#ifdef CONFIG_ARCH_TEGRA_2x_SOC
29/* Primary Interrupt Controller */ 28/* Primary Interrupt Controller */
30#define INT_PRI_BASE (INT_GIC_BASE + 32) 29#define INT_PRI_BASE (INT_GIC_BASE + 32)
31#define INT_TMR1 (INT_PRI_BASE + 0) 30#define INT_TMR1 (INT_PRI_BASE + 0)
@@ -178,6 +177,5 @@
178#define NR_BOARD_IRQS 32 177#define NR_BOARD_IRQS 32
179 178
180#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS) 179#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
181#endif
182 180
183#endif 181#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-t2.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
index 4c2626347263..6a40c1dbab17 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux-t2.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-t2.h 2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * 5 *
@@ -14,8 +14,8 @@
14 * 14 *
15 */ 15 */
16 16
17#ifndef __MACH_TEGRA_PINMUX_T2_H 17#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
18#define __MACH_TEGRA_PINMUX_T2_H 18#define __MACH_TEGRA_PINMUX_TEGRA20_H
19 19
20enum tegra_pingroup { 20enum tegra_pingroup {
21 TEGRA_PINGROUP_ATA = 0, 21 TEGRA_PINGROUP_ATA = 0,
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
new file mode 100644
index 000000000000..c1aee3eb2df1
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
@@ -0,0 +1,320 @@
1/*
2 * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
19#define __MACH_TEGRA_PINMUX_TEGRA30_H
20
21enum tegra_pingroup {
22 TEGRA_PINGROUP_ULPI_DATA0 = 0,
23 TEGRA_PINGROUP_ULPI_DATA1,
24 TEGRA_PINGROUP_ULPI_DATA2,
25 TEGRA_PINGROUP_ULPI_DATA3,
26 TEGRA_PINGROUP_ULPI_DATA4,
27 TEGRA_PINGROUP_ULPI_DATA5,
28 TEGRA_PINGROUP_ULPI_DATA6,
29 TEGRA_PINGROUP_ULPI_DATA7,
30 TEGRA_PINGROUP_ULPI_CLK,
31 TEGRA_PINGROUP_ULPI_DIR,
32 TEGRA_PINGROUP_ULPI_NXT,
33 TEGRA_PINGROUP_ULPI_STP,
34 TEGRA_PINGROUP_DAP3_FS,
35 TEGRA_PINGROUP_DAP3_DIN,
36 TEGRA_PINGROUP_DAP3_DOUT,
37 TEGRA_PINGROUP_DAP3_SCLK,
38 TEGRA_PINGROUP_GPIO_PV0,
39 TEGRA_PINGROUP_GPIO_PV1,
40 TEGRA_PINGROUP_SDMMC1_CLK,
41 TEGRA_PINGROUP_SDMMC1_CMD,
42 TEGRA_PINGROUP_SDMMC1_DAT3,
43 TEGRA_PINGROUP_SDMMC1_DAT2,
44 TEGRA_PINGROUP_SDMMC1_DAT1,
45 TEGRA_PINGROUP_SDMMC1_DAT0,
46 TEGRA_PINGROUP_GPIO_PV2,
47 TEGRA_PINGROUP_GPIO_PV3,
48 TEGRA_PINGROUP_CLK2_OUT,
49 TEGRA_PINGROUP_CLK2_REQ,
50 TEGRA_PINGROUP_LCD_PWR1,
51 TEGRA_PINGROUP_LCD_PWR2,
52 TEGRA_PINGROUP_LCD_SDIN,
53 TEGRA_PINGROUP_LCD_SDOUT,
54 TEGRA_PINGROUP_LCD_WR_N,
55 TEGRA_PINGROUP_LCD_CS0_N,
56 TEGRA_PINGROUP_LCD_DC0,
57 TEGRA_PINGROUP_LCD_SCK,
58 TEGRA_PINGROUP_LCD_PWR0,
59 TEGRA_PINGROUP_LCD_PCLK,
60 TEGRA_PINGROUP_LCD_DE,
61 TEGRA_PINGROUP_LCD_HSYNC,
62 TEGRA_PINGROUP_LCD_VSYNC,
63 TEGRA_PINGROUP_LCD_D0,
64 TEGRA_PINGROUP_LCD_D1,
65 TEGRA_PINGROUP_LCD_D2,
66 TEGRA_PINGROUP_LCD_D3,
67 TEGRA_PINGROUP_LCD_D4,
68 TEGRA_PINGROUP_LCD_D5,
69 TEGRA_PINGROUP_LCD_D6,
70 TEGRA_PINGROUP_LCD_D7,
71 TEGRA_PINGROUP_LCD_D8,
72 TEGRA_PINGROUP_LCD_D9,
73 TEGRA_PINGROUP_LCD_D10,
74 TEGRA_PINGROUP_LCD_D11,
75 TEGRA_PINGROUP_LCD_D12,
76 TEGRA_PINGROUP_LCD_D13,
77 TEGRA_PINGROUP_LCD_D14,
78 TEGRA_PINGROUP_LCD_D15,
79 TEGRA_PINGROUP_LCD_D16,
80 TEGRA_PINGROUP_LCD_D17,
81 TEGRA_PINGROUP_LCD_D18,
82 TEGRA_PINGROUP_LCD_D19,
83 TEGRA_PINGROUP_LCD_D20,
84 TEGRA_PINGROUP_LCD_D21,
85 TEGRA_PINGROUP_LCD_D22,
86 TEGRA_PINGROUP_LCD_D23,
87 TEGRA_PINGROUP_LCD_CS1_N,
88 TEGRA_PINGROUP_LCD_M1,
89 TEGRA_PINGROUP_LCD_DC1,
90 TEGRA_PINGROUP_HDMI_INT,
91 TEGRA_PINGROUP_DDC_SCL,
92 TEGRA_PINGROUP_DDC_SDA,
93 TEGRA_PINGROUP_CRT_HSYNC,
94 TEGRA_PINGROUP_CRT_VSYNC,
95 TEGRA_PINGROUP_VI_D0,
96 TEGRA_PINGROUP_VI_D1,
97 TEGRA_PINGROUP_VI_D2,
98 TEGRA_PINGROUP_VI_D3,
99 TEGRA_PINGROUP_VI_D4,
100 TEGRA_PINGROUP_VI_D5,
101 TEGRA_PINGROUP_VI_D6,
102 TEGRA_PINGROUP_VI_D7,
103 TEGRA_PINGROUP_VI_D8,
104 TEGRA_PINGROUP_VI_D9,
105 TEGRA_PINGROUP_VI_D10,
106 TEGRA_PINGROUP_VI_D11,
107 TEGRA_PINGROUP_VI_PCLK,
108 TEGRA_PINGROUP_VI_MCLK,
109 TEGRA_PINGROUP_VI_VSYNC,
110 TEGRA_PINGROUP_VI_HSYNC,
111 TEGRA_PINGROUP_UART2_RXD,
112 TEGRA_PINGROUP_UART2_TXD,
113 TEGRA_PINGROUP_UART2_RTS_N,
114 TEGRA_PINGROUP_UART2_CTS_N,
115 TEGRA_PINGROUP_UART3_TXD,
116 TEGRA_PINGROUP_UART3_RXD,
117 TEGRA_PINGROUP_UART3_CTS_N,
118 TEGRA_PINGROUP_UART3_RTS_N,
119 TEGRA_PINGROUP_GPIO_PU0,
120 TEGRA_PINGROUP_GPIO_PU1,
121 TEGRA_PINGROUP_GPIO_PU2,
122 TEGRA_PINGROUP_GPIO_PU3,
123 TEGRA_PINGROUP_GPIO_PU4,
124 TEGRA_PINGROUP_GPIO_PU5,
125 TEGRA_PINGROUP_GPIO_PU6,
126 TEGRA_PINGROUP_GEN1_I2C_SDA,
127 TEGRA_PINGROUP_GEN1_I2C_SCL,
128 TEGRA_PINGROUP_DAP4_FS,
129 TEGRA_PINGROUP_DAP4_DIN,
130 TEGRA_PINGROUP_DAP4_DOUT,
131 TEGRA_PINGROUP_DAP4_SCLK,
132 TEGRA_PINGROUP_CLK3_OUT,
133 TEGRA_PINGROUP_CLK3_REQ,
134 TEGRA_PINGROUP_GMI_WP_N,
135 TEGRA_PINGROUP_GMI_IORDY,
136 TEGRA_PINGROUP_GMI_WAIT,
137 TEGRA_PINGROUP_GMI_ADV_N,
138 TEGRA_PINGROUP_GMI_CLK,
139 TEGRA_PINGROUP_GMI_CS0_N,
140 TEGRA_PINGROUP_GMI_CS1_N,
141 TEGRA_PINGROUP_GMI_CS2_N,
142 TEGRA_PINGROUP_GMI_CS3_N,
143 TEGRA_PINGROUP_GMI_CS4_N,
144 TEGRA_PINGROUP_GMI_CS6_N,
145 TEGRA_PINGROUP_GMI_CS7_N,
146 TEGRA_PINGROUP_GMI_AD0,
147 TEGRA_PINGROUP_GMI_AD1,
148 TEGRA_PINGROUP_GMI_AD2,
149 TEGRA_PINGROUP_GMI_AD3,
150 TEGRA_PINGROUP_GMI_AD4,
151 TEGRA_PINGROUP_GMI_AD5,
152 TEGRA_PINGROUP_GMI_AD6,
153 TEGRA_PINGROUP_GMI_AD7,
154 TEGRA_PINGROUP_GMI_AD8,
155 TEGRA_PINGROUP_GMI_AD9,
156 TEGRA_PINGROUP_GMI_AD10,
157 TEGRA_PINGROUP_GMI_AD11,
158 TEGRA_PINGROUP_GMI_AD12,
159 TEGRA_PINGROUP_GMI_AD13,
160 TEGRA_PINGROUP_GMI_AD14,
161 TEGRA_PINGROUP_GMI_AD15,
162 TEGRA_PINGROUP_GMI_A16,
163 TEGRA_PINGROUP_GMI_A17,
164 TEGRA_PINGROUP_GMI_A18,
165 TEGRA_PINGROUP_GMI_A19,
166 TEGRA_PINGROUP_GMI_WR_N,
167 TEGRA_PINGROUP_GMI_OE_N,
168 TEGRA_PINGROUP_GMI_DQS,
169 TEGRA_PINGROUP_GMI_RST_N,
170 TEGRA_PINGROUP_GEN2_I2C_SCL,
171 TEGRA_PINGROUP_GEN2_I2C_SDA,
172 TEGRA_PINGROUP_SDMMC4_CLK,
173 TEGRA_PINGROUP_SDMMC4_CMD,
174 TEGRA_PINGROUP_SDMMC4_DAT0,
175 TEGRA_PINGROUP_SDMMC4_DAT1,
176 TEGRA_PINGROUP_SDMMC4_DAT2,
177 TEGRA_PINGROUP_SDMMC4_DAT3,
178 TEGRA_PINGROUP_SDMMC4_DAT4,
179 TEGRA_PINGROUP_SDMMC4_DAT5,
180 TEGRA_PINGROUP_SDMMC4_DAT6,
181 TEGRA_PINGROUP_SDMMC4_DAT7,
182 TEGRA_PINGROUP_SDMMC4_RST_N,
183 TEGRA_PINGROUP_CAM_MCLK,
184 TEGRA_PINGROUP_GPIO_PCC1,
185 TEGRA_PINGROUP_GPIO_PBB0,
186 TEGRA_PINGROUP_CAM_I2C_SCL,
187 TEGRA_PINGROUP_CAM_I2C_SDA,
188 TEGRA_PINGROUP_GPIO_PBB3,
189 TEGRA_PINGROUP_GPIO_PBB4,
190 TEGRA_PINGROUP_GPIO_PBB5,
191 TEGRA_PINGROUP_GPIO_PBB6,
192 TEGRA_PINGROUP_GPIO_PBB7,
193 TEGRA_PINGROUP_GPIO_PCC2,
194 TEGRA_PINGROUP_JTAG_RTCK,
195 TEGRA_PINGROUP_PWR_I2C_SCL,
196 TEGRA_PINGROUP_PWR_I2C_SDA,
197 TEGRA_PINGROUP_KB_ROW0,
198 TEGRA_PINGROUP_KB_ROW1,
199 TEGRA_PINGROUP_KB_ROW2,
200 TEGRA_PINGROUP_KB_ROW3,
201 TEGRA_PINGROUP_KB_ROW4,
202 TEGRA_PINGROUP_KB_ROW5,
203 TEGRA_PINGROUP_KB_ROW6,
204 TEGRA_PINGROUP_KB_ROW7,
205 TEGRA_PINGROUP_KB_ROW8,
206 TEGRA_PINGROUP_KB_ROW9,
207 TEGRA_PINGROUP_KB_ROW10,
208 TEGRA_PINGROUP_KB_ROW11,
209 TEGRA_PINGROUP_KB_ROW12,
210 TEGRA_PINGROUP_KB_ROW13,
211 TEGRA_PINGROUP_KB_ROW14,
212 TEGRA_PINGROUP_KB_ROW15,
213 TEGRA_PINGROUP_KB_COL0,
214 TEGRA_PINGROUP_KB_COL1,
215 TEGRA_PINGROUP_KB_COL2,
216 TEGRA_PINGROUP_KB_COL3,
217 TEGRA_PINGROUP_KB_COL4,
218 TEGRA_PINGROUP_KB_COL5,
219 TEGRA_PINGROUP_KB_COL6,
220 TEGRA_PINGROUP_KB_COL7,
221 TEGRA_PINGROUP_CLK_32K_OUT,
222 TEGRA_PINGROUP_SYS_CLK_REQ,
223 TEGRA_PINGROUP_CORE_PWR_REQ,
224 TEGRA_PINGROUP_CPU_PWR_REQ,
225 TEGRA_PINGROUP_PWR_INT_N,
226 TEGRA_PINGROUP_CLK_32K_IN,
227 TEGRA_PINGROUP_OWR,
228 TEGRA_PINGROUP_DAP1_FS,
229 TEGRA_PINGROUP_DAP1_DIN,
230 TEGRA_PINGROUP_DAP1_DOUT,
231 TEGRA_PINGROUP_DAP1_SCLK,
232 TEGRA_PINGROUP_CLK1_REQ,
233 TEGRA_PINGROUP_CLK1_OUT,
234 TEGRA_PINGROUP_SPDIF_IN,
235 TEGRA_PINGROUP_SPDIF_OUT,
236 TEGRA_PINGROUP_DAP2_FS,
237 TEGRA_PINGROUP_DAP2_DIN,
238 TEGRA_PINGROUP_DAP2_DOUT,
239 TEGRA_PINGROUP_DAP2_SCLK,
240 TEGRA_PINGROUP_SPI2_MOSI,
241 TEGRA_PINGROUP_SPI2_MISO,
242 TEGRA_PINGROUP_SPI2_CS0_N,
243 TEGRA_PINGROUP_SPI2_SCK,
244 TEGRA_PINGROUP_SPI1_MOSI,
245 TEGRA_PINGROUP_SPI1_SCK,
246 TEGRA_PINGROUP_SPI1_CS0_N,
247 TEGRA_PINGROUP_SPI1_MISO,
248 TEGRA_PINGROUP_SPI2_CS1_N,
249 TEGRA_PINGROUP_SPI2_CS2_N,
250 TEGRA_PINGROUP_SDMMC3_CLK,
251 TEGRA_PINGROUP_SDMMC3_CMD,
252 TEGRA_PINGROUP_SDMMC3_DAT0,
253 TEGRA_PINGROUP_SDMMC3_DAT1,
254 TEGRA_PINGROUP_SDMMC3_DAT2,
255 TEGRA_PINGROUP_SDMMC3_DAT3,
256 TEGRA_PINGROUP_SDMMC3_DAT4,
257 TEGRA_PINGROUP_SDMMC3_DAT5,
258 TEGRA_PINGROUP_SDMMC3_DAT6,
259 TEGRA_PINGROUP_SDMMC3_DAT7,
260 TEGRA_PINGROUP_PEX_L0_PRSNT_N,
261 TEGRA_PINGROUP_PEX_L0_RST_N,
262 TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
263 TEGRA_PINGROUP_PEX_WAKE_N,
264 TEGRA_PINGROUP_PEX_L1_PRSNT_N,
265 TEGRA_PINGROUP_PEX_L1_RST_N,
266 TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
267 TEGRA_PINGROUP_PEX_L2_PRSNT_N,
268 TEGRA_PINGROUP_PEX_L2_RST_N,
269 TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
270 TEGRA_PINGROUP_HDMI_CEC,
271 TEGRA_MAX_PINGROUP,
272};
273
274enum tegra_drive_pingroup {
275 TEGRA_DRIVE_PINGROUP_AO1 = 0,
276 TEGRA_DRIVE_PINGROUP_AO2,
277 TEGRA_DRIVE_PINGROUP_AT1,
278 TEGRA_DRIVE_PINGROUP_AT2,
279 TEGRA_DRIVE_PINGROUP_AT3,
280 TEGRA_DRIVE_PINGROUP_AT4,
281 TEGRA_DRIVE_PINGROUP_AT5,
282 TEGRA_DRIVE_PINGROUP_CDEV1,
283 TEGRA_DRIVE_PINGROUP_CDEV2,
284 TEGRA_DRIVE_PINGROUP_CSUS,
285 TEGRA_DRIVE_PINGROUP_DAP1,
286 TEGRA_DRIVE_PINGROUP_DAP2,
287 TEGRA_DRIVE_PINGROUP_DAP3,
288 TEGRA_DRIVE_PINGROUP_DAP4,
289 TEGRA_DRIVE_PINGROUP_DBG,
290 TEGRA_DRIVE_PINGROUP_LCD1,
291 TEGRA_DRIVE_PINGROUP_LCD2,
292 TEGRA_DRIVE_PINGROUP_SDIO2,
293 TEGRA_DRIVE_PINGROUP_SDIO3,
294 TEGRA_DRIVE_PINGROUP_SPI,
295 TEGRA_DRIVE_PINGROUP_UAA,
296 TEGRA_DRIVE_PINGROUP_UAB,
297 TEGRA_DRIVE_PINGROUP_UART2,
298 TEGRA_DRIVE_PINGROUP_UART3,
299 TEGRA_DRIVE_PINGROUP_VI1,
300 TEGRA_DRIVE_PINGROUP_SDIO1,
301 TEGRA_DRIVE_PINGROUP_CRT,
302 TEGRA_DRIVE_PINGROUP_DDC,
303 TEGRA_DRIVE_PINGROUP_GMA,
304 TEGRA_DRIVE_PINGROUP_GMB,
305 TEGRA_DRIVE_PINGROUP_GMC,
306 TEGRA_DRIVE_PINGROUP_GMD,
307 TEGRA_DRIVE_PINGROUP_GME,
308 TEGRA_DRIVE_PINGROUP_GMF,
309 TEGRA_DRIVE_PINGROUP_GMG,
310 TEGRA_DRIVE_PINGROUP_GMH,
311 TEGRA_DRIVE_PINGROUP_OWR,
312 TEGRA_DRIVE_PINGROUP_UAD,
313 TEGRA_DRIVE_PINGROUP_GPV,
314 TEGRA_DRIVE_PINGROUP_DEV3,
315 TEGRA_DRIVE_PINGROUP_CEC,
316 TEGRA_MAX_DRIVE_PINGROUP,
317};
318
319#endif
320
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
index bb7dfdb61205..055f1792c8ff 100644
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -2,6 +2,7 @@
2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h 2 * linux/arch/arm/mach-tegra/include/mach/pinmux.h
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2010,2011 Nvidia, Inc.
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 8 * License version 2, as published by the Free Software Foundation, and
@@ -17,18 +18,13 @@
17#ifndef __MACH_TEGRA_PINMUX_H 18#ifndef __MACH_TEGRA_PINMUX_H
18#define __MACH_TEGRA_PINMUX_H 19#define __MACH_TEGRA_PINMUX_H
19 20
20#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
21#include "pinmux-t2.h"
22#else
23#error "Undefined Tegra architecture"
24#endif
25
26enum tegra_mux_func { 21enum tegra_mux_func {
27 TEGRA_MUX_RSVD = 0x8000, 22 TEGRA_MUX_RSVD = 0x8000,
28 TEGRA_MUX_RSVD1 = 0x8000, 23 TEGRA_MUX_RSVD1 = 0x8000,
29 TEGRA_MUX_RSVD2 = 0x8001, 24 TEGRA_MUX_RSVD2 = 0x8001,
30 TEGRA_MUX_RSVD3 = 0x8002, 25 TEGRA_MUX_RSVD3 = 0x8002,
31 TEGRA_MUX_RSVD4 = 0x8003, 26 TEGRA_MUX_RSVD4 = 0x8003,
27 TEGRA_MUX_INVALID = 0x4000,
32 TEGRA_MUX_NONE = -1, 28 TEGRA_MUX_NONE = -1,
33 TEGRA_MUX_AHB_CLK, 29 TEGRA_MUX_AHB_CLK,
34 TEGRA_MUX_APB_CLK, 30 TEGRA_MUX_APB_CLK,
@@ -90,6 +86,49 @@ enum tegra_mux_func {
90 TEGRA_MUX_VI, 86 TEGRA_MUX_VI,
91 TEGRA_MUX_VI_SENSOR_CLK, 87 TEGRA_MUX_VI_SENSOR_CLK,
92 TEGRA_MUX_XIO, 88 TEGRA_MUX_XIO,
89 TEGRA_MUX_BLINK,
90 TEGRA_MUX_CEC,
91 TEGRA_MUX_CLK12,
92 TEGRA_MUX_DAP,
93 TEGRA_MUX_DAPSDMMC2,
94 TEGRA_MUX_DDR,
95 TEGRA_MUX_DEV3,
96 TEGRA_MUX_DTV,
97 TEGRA_MUX_VI_ALT1,
98 TEGRA_MUX_VI_ALT2,
99 TEGRA_MUX_VI_ALT3,
100 TEGRA_MUX_EMC_DLL,
101 TEGRA_MUX_EXTPERIPH1,
102 TEGRA_MUX_EXTPERIPH2,
103 TEGRA_MUX_EXTPERIPH3,
104 TEGRA_MUX_GMI_ALT,
105 TEGRA_MUX_HDA,
106 TEGRA_MUX_HSI,
107 TEGRA_MUX_I2C4,
108 TEGRA_MUX_I2C5,
109 TEGRA_MUX_I2CPWR,
110 TEGRA_MUX_I2S0,
111 TEGRA_MUX_I2S1,
112 TEGRA_MUX_I2S2,
113 TEGRA_MUX_I2S3,
114 TEGRA_MUX_I2S4,
115 TEGRA_MUX_NAND_ALT,
116 TEGRA_MUX_POPSDIO4,
117 TEGRA_MUX_POPSDMMC4,
118 TEGRA_MUX_PWM0,
119 TEGRA_MUX_PWM1,
120 TEGRA_MUX_PWM2,
121 TEGRA_MUX_PWM3,
122 TEGRA_MUX_SATA,
123 TEGRA_MUX_SPI5,
124 TEGRA_MUX_SPI6,
125 TEGRA_MUX_SYSCLK,
126 TEGRA_MUX_VGP1,
127 TEGRA_MUX_VGP2,
128 TEGRA_MUX_VGP3,
129 TEGRA_MUX_VGP4,
130 TEGRA_MUX_VGP5,
131 TEGRA_MUX_VGP6,
93 TEGRA_MUX_SAFE, 132 TEGRA_MUX_SAFE,
94 TEGRA_MAX_MUX, 133 TEGRA_MAX_MUX,
95}; 134};
@@ -105,6 +144,11 @@ enum tegra_tristate {
105 TEGRA_TRI_TRISTATE = 1, 144 TEGRA_TRI_TRISTATE = 1,
106}; 145};
107 146
147enum tegra_pin_io {
148 TEGRA_PIN_OUTPUT = 0,
149 TEGRA_PIN_INPUT = 1,
150};
151
108enum tegra_vddio { 152enum tegra_vddio {
109 TEGRA_VDDIO_BB = 0, 153 TEGRA_VDDIO_BB = 0,
110 TEGRA_VDDIO_LCD, 154 TEGRA_VDDIO_LCD,
@@ -115,10 +159,16 @@ enum tegra_vddio {
115 TEGRA_VDDIO_SYS, 159 TEGRA_VDDIO_SYS,
116 TEGRA_VDDIO_AUDIO, 160 TEGRA_VDDIO_AUDIO,
117 TEGRA_VDDIO_SD, 161 TEGRA_VDDIO_SD,
162 TEGRA_VDDIO_CAM,
163 TEGRA_VDDIO_GMI,
164 TEGRA_VDDIO_PEXCTL,
165 TEGRA_VDDIO_SDMMC1,
166 TEGRA_VDDIO_SDMMC3,
167 TEGRA_VDDIO_SDMMC4,
118}; 168};
119 169
120struct tegra_pingroup_config { 170struct tegra_pingroup_config {
121 enum tegra_pingroup pingroup; 171 int pingroup;
122 enum tegra_mux_func func; 172 enum tegra_mux_func func;
123 enum tegra_pullupdown pupd; 173 enum tegra_pullupdown pupd;
124 enum tegra_tristate tristate; 174 enum tegra_tristate tristate;
@@ -187,7 +237,7 @@ enum tegra_schmitt {
187}; 237};
188 238
189struct tegra_drive_pingroup_config { 239struct tegra_drive_pingroup_config {
190 enum tegra_drive_pingroup pingroup; 240 int pingroup;
191 enum tegra_hsm hsm; 241 enum tegra_hsm hsm;
192 enum tegra_schmitt schmitt; 242 enum tegra_schmitt schmitt;
193 enum tegra_drive drive; 243 enum tegra_drive drive;
@@ -208,6 +258,7 @@ struct tegra_pingroup_desc {
208 int funcs[4]; 258 int funcs[4];
209 int func_safe; 259 int func_safe;
210 int vddio; 260 int vddio;
261 enum tegra_pin_io io_default;
211 s16 tri_bank; /* Register bank the tri_reg exists within */ 262 s16 tri_bank; /* Register bank the tri_reg exists within */
212 s16 mux_bank; /* Register bank the mux_reg exists within */ 263 s16 mux_bank; /* Register bank the mux_reg exists within */
213 s16 pupd_bank; /* Register bank the pupd_reg exists within */ 264 s16 pupd_bank; /* Register bank the pupd_reg exists within */
@@ -217,15 +268,23 @@ struct tegra_pingroup_desc {
217 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */ 268 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
218 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */ 269 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
219 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */ 270 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
271 s8 lock_bit; /* offset of the LOCK bit into mux register bit */
272 s8 od_bit; /* offset of the OD bit into mux register bit */
273 s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
220}; 274};
221 275
222extern const struct tegra_pingroup_desc tegra_soc_pingroups[]; 276typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
223extern const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[]; 277 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
278 int *pgdrive_max);
224 279
225int tegra_pinmux_set_tristate(enum tegra_pingroup pg, 280void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
226 enum tegra_tristate tristate); 281 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
227int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, 282
228 enum tegra_pullupdown pupd); 283void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
284 const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
285
286int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
287int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
229 288
230void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, 289void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
231 int len); 290 int len);
@@ -241,4 +300,3 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
241void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config, 300void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
242 int len, enum tegra_pullupdown pupd); 301 int len, enum tegra_pullupdown pupd);
243#endif 302#endif
244
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4956c3cea731..004b0fdf0d76 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -21,6 +21,7 @@
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/of.h>
24 25
25#include <asm/hardware/gic.h> 26#include <asm/hardware/gic.h>
26 27
@@ -129,6 +130,11 @@ void __init tegra_init_irq(void)
129 gic_arch_extn.irq_unmask = tegra_unmask; 130 gic_arch_extn.irq_unmask = tegra_unmask;
130 gic_arch_extn.irq_retrigger = tegra_retrigger; 131 gic_arch_extn.irq_retrigger = tegra_retrigger;
131 132
132 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 133 /*
133 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 134 * Check if there is a devicetree present, since the GIC will be
135 * initialized elsewhere under DT.
136 */
137 if (!of_have_populated_dt())
138 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
139 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
134} 140}
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
index a0dc2bc28ed3..734add1280b7 100644
--- a/arch/arm/mach-tegra/pinmux-t2-tables.c
+++ b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-tegra/pinmux-t2-tables.c 2 * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
3 * 3 *
4 * Common pinmux configurations for Tegra 2 SoCs 4 * Common pinmux configurations for Tegra20 SoCs
5 * 5 *
6 * Copyright (C) 2010 NVIDIA Corporation 6 * Copyright (C) 2010 NVIDIA Corporation
7 * 7 *
@@ -29,6 +29,7 @@
29 29
30#include <mach/iomap.h> 30#include <mach/iomap.h>
31#include <mach/pinmux.h> 31#include <mach/pinmux.h>
32#include <mach/pinmux-tegra20.h>
32#include <mach/suspend.h> 33#include <mach/suspend.h>
33 34
34#define TRISTATE_REG_A 0x14 35#define TRISTATE_REG_A 0x14
@@ -43,7 +44,7 @@
43 .reg = ((r) - PINGROUP_REG_A) \ 44 .reg = ((r) - PINGROUP_REG_A) \
44 } 45 }
45 46
46const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { 47static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
47 DRIVE_PINGROUP(AO1, 0x868), 48 DRIVE_PINGROUP(AO1, 0x868),
48 DRIVE_PINGROUP(AO2, 0x86c), 49 DRIVE_PINGROUP(AO2, 0x86c),
49 DRIVE_PINGROUP(AT1, 0x870), 50 DRIVE_PINGROUP(AT1, 0x870),
@@ -105,9 +106,13 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
105 .pupd_bank = 2, \ 106 .pupd_bank = 2, \
106 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ 107 .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \
107 .pupd_bit = pupd_b, \ 108 .pupd_bit = pupd_b, \
109 .lock_bit = -1, \
110 .od_bit = -1, \
111 .ioreset_bit = -1, \
112 .io_default = -1, \
108 } 113 }
109 114
110const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { 115static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
111 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0), 116 PINGROUP(ATA, NAND, IDE, NAND, GMI, RSVD, IDE, 0x14, 0, 0x80, 24, 0xA0, 0),
112 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2), 117 PINGROUP(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 1, 0x80, 16, 0xA0, 2),
113 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4), 118 PINGROUP(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE, 0x14, 2, 0x80, 22, 0xA0, 4),
@@ -226,3 +231,14 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
226 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), 231 PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30),
227 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), 232 PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28),
228}; 233};
234
235void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
236 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
237 int *pgdrive_max)
238{
239 *pg = tegra_soc_pingroups;
240 *pg_max = TEGRA_MAX_PINGROUP;
241 *pgdrive = tegra_soc_drive_pingroups;
242 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
243}
244
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
new file mode 100644
index 000000000000..14fc0e4c1c44
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
@@ -0,0 +1,376 @@
1/*
2 * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
3 *
4 * Common pinmux configurations for Tegra30 SoCs
5 *
6 * Copyright (C) 2010,2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/errno.h>
24#include <linux/spinlock.h>
25#include <linux/io.h>
26#include <linux/init.h>
27#include <linux/string.h>
28
29#include <mach/iomap.h>
30#include <mach/pinmux.h>
31#include <mach/pinmux-tegra30.h>
32#include <mach/suspend.h>
33
34#define PINGROUP_REG_A 0x868
35#define MUXCTL_REG_A 0x3000
36
37#define DRIVE_PINGROUP(pg_name, r) \
38 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
39 .name = #pg_name, \
40 .reg_bank = 0, \
41 .reg = ((r) - PINGROUP_REG_A) \
42 }
43
44static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
45 DRIVE_PINGROUP(AO1, 0x868),
46 DRIVE_PINGROUP(AO2, 0x86c),
47 DRIVE_PINGROUP(AT1, 0x870),
48 DRIVE_PINGROUP(AT2, 0x874),
49 DRIVE_PINGROUP(AT3, 0x878),
50 DRIVE_PINGROUP(AT4, 0x87c),
51 DRIVE_PINGROUP(AT5, 0x880),
52 DRIVE_PINGROUP(CDEV1, 0x884),
53 DRIVE_PINGROUP(CDEV2, 0x888),
54 DRIVE_PINGROUP(CSUS, 0x88c),
55 DRIVE_PINGROUP(DAP1, 0x890),
56 DRIVE_PINGROUP(DAP2, 0x894),
57 DRIVE_PINGROUP(DAP3, 0x898),
58 DRIVE_PINGROUP(DAP4, 0x89c),
59 DRIVE_PINGROUP(DBG, 0x8a0),
60 DRIVE_PINGROUP(LCD1, 0x8a4),
61 DRIVE_PINGROUP(LCD2, 0x8a8),
62 DRIVE_PINGROUP(SDIO2, 0x8ac),
63 DRIVE_PINGROUP(SDIO3, 0x8b0),
64 DRIVE_PINGROUP(SPI, 0x8b4),
65 DRIVE_PINGROUP(UAA, 0x8b8),
66 DRIVE_PINGROUP(UAB, 0x8bc),
67 DRIVE_PINGROUP(UART2, 0x8c0),
68 DRIVE_PINGROUP(UART3, 0x8c4),
69 DRIVE_PINGROUP(VI1, 0x8c8),
70 DRIVE_PINGROUP(SDIO1, 0x8ec),
71 DRIVE_PINGROUP(CRT, 0x8f8),
72 DRIVE_PINGROUP(DDC, 0x8fc),
73 DRIVE_PINGROUP(GMA, 0x900),
74 DRIVE_PINGROUP(GMB, 0x904),
75 DRIVE_PINGROUP(GMC, 0x908),
76 DRIVE_PINGROUP(GMD, 0x90c),
77 DRIVE_PINGROUP(GME, 0x910),
78 DRIVE_PINGROUP(GMF, 0x914),
79 DRIVE_PINGROUP(GMG, 0x918),
80 DRIVE_PINGROUP(GMH, 0x91c),
81 DRIVE_PINGROUP(OWR, 0x920),
82 DRIVE_PINGROUP(UAD, 0x924),
83 DRIVE_PINGROUP(GPV, 0x928),
84 DRIVE_PINGROUP(DEV3, 0x92c),
85 DRIVE_PINGROUP(CEC, 0x938),
86};
87
88#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg) \
89 [TEGRA_PINGROUP_ ## pg_name] = { \
90 .name = #pg_name, \
91 .vddio = TEGRA_VDDIO_ ## vdd, \
92 .funcs = { \
93 TEGRA_MUX_ ## f0, \
94 TEGRA_MUX_ ## f1, \
95 TEGRA_MUX_ ## f2, \
96 TEGRA_MUX_ ## f3, \
97 }, \
98 .func_safe = TEGRA_MUX_ ## fs, \
99 .tri_bank = 1, \
100 .tri_reg = ((reg) - MUXCTL_REG_A), \
101 .tri_bit = 4, \
102 .mux_bank = 1, \
103 .mux_reg = ((reg) - MUXCTL_REG_A), \
104 .mux_bit = 0, \
105 .pupd_bank = 1, \
106 .pupd_reg = ((reg) - MUXCTL_REG_A), \
107 .pupd_bit = 2, \
108 .io_default = TEGRA_PIN_ ## iod, \
109 .od_bit = 6, \
110 .lock_bit = 7, \
111 .ioreset_bit = 8, \
112 }
113
114static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
115 /* NAME VDD f0 f1 f2 f3 fSafe io reg */
116 PINGROUP(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3000),
117 PINGROUP(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3004),
118 PINGROUP(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x3008),
119 PINGROUP(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI, RSVD, INPUT, 0x300c),
120 PINGROUP(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3010),
121 PINGROUP(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3014),
122 PINGROUP(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x3018),
123 PINGROUP(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI, RSVD, INPUT, 0x301c),
124 PINGROUP(ULPI_CLK, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3020),
125 PINGROUP(ULPI_DIR, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3024),
126 PINGROUP(ULPI_NXT, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x3028),
127 PINGROUP(ULPI_STP, BB, SPI1, RSVD, UARTD, ULPI, RSVD, INPUT, 0x302c),
128 PINGROUP(DAP3_FS, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3030),
129 PINGROUP(DAP3_DIN, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3034),
130 PINGROUP(DAP3_DOUT, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x3038),
131 PINGROUP(DAP3_SCLK, BB, I2S2, RSVD1, DISPLAYA, DISPLAYB, RSVD, INPUT, 0x303c),
132 PINGROUP(GPIO_PV0, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3040),
133 PINGROUP(GPIO_PV1, BB, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3044),
134 PINGROUP(SDMMC1_CLK, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x3048),
135 PINGROUP(SDMMC1_CMD, SDMMC1, SDIO1, RSVD1, RSVD2, INVALID, RSVD, INPUT, 0x304c),
136 PINGROUP(SDMMC1_DAT3, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3050),
137 PINGROUP(SDMMC1_DAT2, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3054),
138 PINGROUP(SDMMC1_DAT1, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x3058),
139 PINGROUP(SDMMC1_DAT0, SDMMC1, SDIO1, RSVD1, UARTE, INVALID, RSVD, INPUT, 0x305c),
140 PINGROUP(GPIO_PV2, SDMMC1, OWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3060),
141 PINGROUP(GPIO_PV3, SDMMC1, INVALID, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3064),
142 PINGROUP(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3068),
143 PINGROUP(CLK2_REQ, SDMMC1, DAP, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x306c),
144 PINGROUP(LCD_PWR1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3070),
145 PINGROUP(LCD_PWR2, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3074),
146 PINGROUP(LCD_SDIN, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3078),
147 PINGROUP(LCD_SDOUT, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x307c),
148 PINGROUP(LCD_WR_N, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3080),
149 PINGROUP(LCD_CS0_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD, RSVD, OUTPUT, 0x3084),
150 PINGROUP(LCD_DC0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3088),
151 PINGROUP(LCD_SCK, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x308c),
152 PINGROUP(LCD_PWR0, LCD, DISPLAYA, DISPLAYB, SPI5, INVALID, RSVD, OUTPUT, 0x3090),
153 PINGROUP(LCD_PCLK, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3094),
154 PINGROUP(LCD_DE, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3098),
155 PINGROUP(LCD_HSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x309c),
156 PINGROUP(LCD_VSYNC, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a0),
157 PINGROUP(LCD_D0, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a4),
158 PINGROUP(LCD_D1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30a8),
159 PINGROUP(LCD_D2, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ac),
160 PINGROUP(LCD_D3, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b0),
161 PINGROUP(LCD_D4, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b4),
162 PINGROUP(LCD_D5, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30b8),
163 PINGROUP(LCD_D6, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30bc),
164 PINGROUP(LCD_D7, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c0),
165 PINGROUP(LCD_D8, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c4),
166 PINGROUP(LCD_D9, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30c8),
167 PINGROUP(LCD_D10, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30cc),
168 PINGROUP(LCD_D11, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d0),
169 PINGROUP(LCD_D12, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d4),
170 PINGROUP(LCD_D13, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30d8),
171 PINGROUP(LCD_D14, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30dc),
172 PINGROUP(LCD_D15, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e0),
173 PINGROUP(LCD_D16, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e4),
174 PINGROUP(LCD_D17, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30e8),
175 PINGROUP(LCD_D18, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30ec),
176 PINGROUP(LCD_D19, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f0),
177 PINGROUP(LCD_D20, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f4),
178 PINGROUP(LCD_D21, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30f8),
179 PINGROUP(LCD_D22, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x30fc),
180 PINGROUP(LCD_D23, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3100),
181 PINGROUP(LCD_CS1_N, LCD, DISPLAYA, DISPLAYB, SPI5, RSVD2, RSVD, OUTPUT, 0x3104),
182 PINGROUP(LCD_M1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x3108),
183 PINGROUP(LCD_DC1, LCD, DISPLAYA, DISPLAYB, RSVD1, RSVD2, RSVD, OUTPUT, 0x310c),
184 PINGROUP(HDMI_INT, LCD, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3110),
185 PINGROUP(DDC_SCL, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3114),
186 PINGROUP(DDC_SDA, LCD, I2C4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3118),
187 PINGROUP(CRT_HSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x311c),
188 PINGROUP(CRT_VSYNC, LCD, CRT, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3120),
189 PINGROUP(VI_D0, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3124),
190 PINGROUP(VI_D1, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3128),
191 PINGROUP(VI_D2, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x312c),
192 PINGROUP(VI_D3, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3130),
193 PINGROUP(VI_D4, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3134),
194 PINGROUP(VI_D5, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3138),
195 PINGROUP(VI_D6, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x313c),
196 PINGROUP(VI_D7, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3140),
197 PINGROUP(VI_D8, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3144),
198 PINGROUP(VI_D9, VI, INVALID, SDIO2, VI, RSVD1, RSVD, INPUT, 0x3148),
199 PINGROUP(VI_D10, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x314c),
200 PINGROUP(VI_D11, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3150),
201 PINGROUP(VI_PCLK, VI, RSVD1, SDIO2, VI, RSVD2, RSVD, INPUT, 0x3154),
202 PINGROUP(VI_MCLK, VI, VI, INVALID, INVALID, INVALID, RSVD, INPUT, 0x3158),
203 PINGROUP(VI_VSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x315c),
204 PINGROUP(VI_HSYNC, VI, INVALID, RSVD1, VI, RSVD2, RSVD, INPUT, 0x3160),
205 PINGROUP(UART2_RXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3164),
206 PINGROUP(UART2_TXD, UART, IRDA, SPDIF, UARTA, SPI4, RSVD, INPUT, 0x3168),
207 PINGROUP(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x316c),
208 PINGROUP(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4, RSVD, INPUT, 0x3170),
209 PINGROUP(UART3_TXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3174),
210 PINGROUP(UART3_RXD, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x3178),
211 PINGROUP(UART3_CTS_N, UART, UARTC, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x317c),
212 PINGROUP(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD2, RSVD, INPUT, 0x3180),
213 PINGROUP(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3184),
214 PINGROUP(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x3188),
215 PINGROUP(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD2, RSVD, INPUT, 0x318c),
216 PINGROUP(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3190),
217 PINGROUP(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3194),
218 PINGROUP(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD1, RSVD, INPUT, 0x3198),
219 PINGROUP(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD1, RSVD, INPUT, 0x319c),
220 PINGROUP(GEN1_I2C_SDA, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a0),
221 PINGROUP(GEN1_I2C_SCL, UART, I2C, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31a4),
222 PINGROUP(DAP4_FS, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31a8),
223 PINGROUP(DAP4_DIN, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31ac),
224 PINGROUP(DAP4_DOUT, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b0),
225 PINGROUP(DAP4_SCLK, UART, I2S3, RSVD1, GMI, RSVD2, RSVD, INPUT, 0x31b4),
226 PINGROUP(CLK3_OUT, UART, EXTPERIPH3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31b8),
227 PINGROUP(CLK3_REQ, UART, DEV3, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x31bc),
228 PINGROUP(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31c0),
229 PINGROUP(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c4),
230 PINGROUP(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),
231 PINGROUP(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),
232 PINGROUP(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),
233 PINGROUP(GMI_CS0_N, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),
234 PINGROUP(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),
235 PINGROUP(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),
236 PINGROUP(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),
237 PINGROUP(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31e4),
238 PINGROUP(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA, RSVD, INPUT, 0x31e8),
239 PINGROUP(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT, RSVD, INPUT, 0x31ec),
240 PINGROUP(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f0),
241 PINGROUP(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f4),
242 PINGROUP(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31f8),
243 PINGROUP(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31fc),
244 PINGROUP(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3200),
245 PINGROUP(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3204),
246 PINGROUP(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3208),
247 PINGROUP(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x320c),
248 PINGROUP(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD2, RSVD, INPUT, 0x3210),
249 PINGROUP(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3214),
250 PINGROUP(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD2, RSVD, INPUT, 0x3218),
251 PINGROUP(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD2, RSVD, INPUT, 0x321c),
252 PINGROUP(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3220),
253 PINGROUP(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3224),
254 PINGROUP(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),
255 PINGROUP(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),
256 PINGROUP(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),
257 PINGROUP(GMI_A17, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),
258 PINGROUP(GMI_A18, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),
259 PINGROUP(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),
260 PINGROUP(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),
261 PINGROUP(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),
262 PINGROUP(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3248),
263 PINGROUP(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD3, RSVD, INPUT, 0x324c),
264 PINGROUP(GEN2_I2C_SCL, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3250),
265 PINGROUP(GEN2_I2C_SDA, GMI, I2C2, INVALID, GMI, RSVD3, RSVD, INPUT, 0x3254),
266 PINGROUP(SDMMC4_CLK, SDMMC4, INVALID, NAND, GMI, SDIO4, RSVD, INPUT, 0x3258),
267 PINGROUP(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDIO4, RSVD, INPUT, 0x325c),
268 PINGROUP(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3260),
269 PINGROUP(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3264),
270 PINGROUP(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x3268),
271 PINGROUP(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDIO4, RSVD, INPUT, 0x326c),
272 PINGROUP(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3270),
273 PINGROUP(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3274),
274 PINGROUP(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDIO4, RSVD, INPUT, 0x3278),
275 PINGROUP(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDIO4, RSVD, INPUT, 0x327c),
276 PINGROUP(SDMMC4_RST_N, SDMMC4, VGP6, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3280),
277 PINGROUP(CAM_MCLK, CAM, VI, INVALID, VI_ALT2, POPSDMMC4, RSVD, INPUT, 0x3284),
278 PINGROUP(GPIO_PCC1, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3288),
279 PINGROUP(GPIO_PBB0, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x328c),
280 PINGROUP(CAM_I2C_SCL, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3290),
281 PINGROUP(CAM_I2C_SDA, CAM, INVALID, I2C3, RSVD2, POPSDMMC4, RSVD, INPUT, 0x3294),
282 PINGROUP(GPIO_PBB3, CAM, VGP3, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x3298),
283 PINGROUP(GPIO_PBB4, CAM, VGP4, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x329c),
284 PINGROUP(GPIO_PBB5, CAM, VGP5, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a0),
285 PINGROUP(GPIO_PBB6, CAM, VGP6, DISPLAYA, DISPLAYB, POPSDMMC4, RSVD, INPUT, 0x32a4),
286 PINGROUP(GPIO_PBB7, CAM, I2S4, RSVD1, RSVD2, POPSDMMC4, RSVD, INPUT, 0x32a8),
287 PINGROUP(GPIO_PCC2, CAM, I2S4, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32ac),
288 PINGROUP(JTAG_RTCK, SYS, RTCK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b0),
289 PINGROUP(PWR_I2C_SCL, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b4),
290 PINGROUP(PWR_I2C_SDA, SYS, I2CPWR, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x32b8),
291 PINGROUP(KB_ROW0, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32bc),
292 PINGROUP(KB_ROW1, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c0),
293 PINGROUP(KB_ROW2, SYS, KBC, INVALID, RSVD2, RSVD3, RSVD, INPUT, 0x32c4),
294 PINGROUP(KB_ROW3, SYS, KBC, INVALID, RSVD2, INVALID, RSVD, INPUT, 0x32c8),
295 PINGROUP(KB_ROW4, SYS, KBC, INVALID, TRACE, RSVD3, RSVD, INPUT, 0x32cc),
296 PINGROUP(KB_ROW5, SYS, KBC, INVALID, TRACE, OWR, RSVD, INPUT, 0x32d0),
297 PINGROUP(KB_ROW6, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d4),
298 PINGROUP(KB_ROW7, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32d8),
299 PINGROUP(KB_ROW8, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32dc),
300 PINGROUP(KB_ROW9, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e0),
301 PINGROUP(KB_ROW10, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e4),
302 PINGROUP(KB_ROW11, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32e8),
303 PINGROUP(KB_ROW12, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32ec),
304 PINGROUP(KB_ROW13, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f0),
305 PINGROUP(KB_ROW14, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f4),
306 PINGROUP(KB_ROW15, SYS, KBC, INVALID, SDIO2, INVALID, RSVD, INPUT, 0x32f8),
307 PINGROUP(KB_COL0, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x32fc),
308 PINGROUP(KB_COL1, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3300),
309 PINGROUP(KB_COL2, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3304),
310 PINGROUP(KB_COL3, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3308),
311 PINGROUP(KB_COL4, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x330c),
312 PINGROUP(KB_COL5, SYS, KBC, INVALID, TRACE, RSVD, RSVD, INPUT, 0x3310),
313 PINGROUP(KB_COL6, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3314),
314 PINGROUP(KB_COL7, SYS, KBC, INVALID, TRACE, INVALID, RSVD, INPUT, 0x3318),
315 PINGROUP(CLK_32K_OUT, SYS, BLINK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x331c),
316 PINGROUP(SYS_CLK_REQ, SYS, SYSCLK, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x3320),
317 PINGROUP(CORE_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3324),
318 PINGROUP(CPU_PWR_REQ, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3328),
319 PINGROUP(PWR_INT_N, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x332c),
320 PINGROUP(CLK_32K_IN, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3330),
321 PINGROUP(OWR, SYS, OWR, RSVD, RSVD, RSVD, RSVD, INPUT, 0x3334),
322 PINGROUP(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3338),
323 PINGROUP(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x333c),
324 PINGROUP(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3340),
325 PINGROUP(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDIO2, RSVD, INPUT, 0x3344),
326 PINGROUP(CLK1_REQ, AUDIO, DAP, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x3348),
327 PINGROUP(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x334c),
328 PINGROUP(SPDIF_IN, AUDIO, SPDIF, HDA, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3350),
329 PINGROUP(SPDIF_OUT, AUDIO, SPDIF, RSVD1, INVALID, DAPSDMMC2, RSVD, INPUT, 0x3354),
330 PINGROUP(DAP2_FS, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3358),
331 PINGROUP(DAP2_DIN, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x335c),
332 PINGROUP(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3360),
333 PINGROUP(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD2, GMI, RSVD, INPUT, 0x3364),
334 PINGROUP(SPI2_MOSI, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3368),
335 PINGROUP(SPI2_MISO, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x336c),
336 PINGROUP(SPI2_CS0_N, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3370),
337 PINGROUP(SPI2_SCK, AUDIO, SPI6, SPI2, INVALID, GMI, RSVD, INPUT, 0x3374),
338 PINGROUP(SPI1_MOSI, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3378),
339 PINGROUP(SPI1_SCK, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x337c),
340 PINGROUP(SPI1_CS0_N, AUDIO, SPI2, SPI1, INVALID, GMI, RSVD, INPUT, 0x3380),
341 PINGROUP(SPI1_MISO, AUDIO, INVALID, SPI1, INVALID, RSVD3, RSVD, INPUT, 0x3384),
342 PINGROUP(SPI2_CS1_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x3388),
343 PINGROUP(SPI2_CS2_N, AUDIO, INVALID, SPI2, INVALID, INVALID, RSVD, INPUT, 0x338c),
344 PINGROUP(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDIO3, INVALID, RSVD, INPUT, 0x3390),
345 PINGROUP(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDIO3, INVALID, RSVD, INPUT, 0x3394),
346 PINGROUP(SDMMC3_DAT0, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x3398),
347 PINGROUP(SDMMC3_DAT1, SDMMC3, RSVD, RSVD1, SDIO3, INVALID, RSVD, INPUT, 0x339c),
348 PINGROUP(SDMMC3_DAT2, SDMMC3, RSVD, PWM1, SDIO3, INVALID, RSVD, INPUT, 0x33a0),
349 PINGROUP(SDMMC3_DAT3, SDMMC3, RSVD, PWM0, SDIO3, INVALID, RSVD, INPUT, 0x33a4),
350 PINGROUP(SDMMC3_DAT4, SDMMC3, PWM1, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33a8),
351 PINGROUP(SDMMC3_DAT5, SDMMC3, PWM0, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33ac),
352 PINGROUP(SDMMC3_DAT6, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b0),
353 PINGROUP(SDMMC3_DAT7, SDMMC3, SPDIF, INVALID, SDIO3, INVALID, RSVD, INPUT, 0x33b4),
354 PINGROUP(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33b8),
355 PINGROUP(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33bc),
356 PINGROUP(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c0),
357 PINGROUP(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c4),
358 PINGROUP(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33c8),
359 PINGROUP(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33cc),
360 PINGROUP(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d0),
361 PINGROUP(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d4),
362 PINGROUP(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33d8),
363 PINGROUP(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD2, RSVD3, RSVD, INPUT, 0x33dc),
364 PINGROUP(HDMI_CEC, SYS, CEC, RSVD1, RSVD2, RSVD3, RSVD, INPUT, 0x33e0),
365};
366
367void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
368 int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
369 int *pgdrive_max)
370{
371 *pg = tegra_soc_pingroups;
372 *pg_max = TEGRA_MAX_PINGROUP;
373 *pgdrive = tegra_soc_drive_pingroups;
374 *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
375}
376
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 1d201650d7a4..ac35d2b76850 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -21,6 +21,7 @@
21#include <linux/spinlock.h> 21#include <linux/spinlock.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/of_device.h>
24 25
25#include <mach/iomap.h> 26#include <mach/iomap.h>
26#include <mach/pinmux.h> 27#include <mach/pinmux.h>
@@ -33,8 +34,10 @@
33#define SLWR(reg) (((reg) >> 28) & 0x3) 34#define SLWR(reg) (((reg) >> 28) & 0x3)
34#define SLWF(reg) (((reg) >> 30) & 0x3) 35#define SLWF(reg) (((reg) >> 30) & 0x3)
35 36
36static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups; 37static const struct tegra_pingroup_desc *pingroups;
37static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups; 38static const struct tegra_drive_pingroup_desc *drive_pingroups;
39static int pingroup_max;
40static int drive_max;
38 41
39static char *tegra_mux_names[TEGRA_MAX_MUX] = { 42static char *tegra_mux_names[TEGRA_MAX_MUX] = {
40 [TEGRA_MUX_AHB_CLK] = "AHB_CLK", 43 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -97,6 +100,49 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
97 [TEGRA_MUX_VI] = "VI", 100 [TEGRA_MUX_VI] = "VI",
98 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", 101 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
99 [TEGRA_MUX_XIO] = "XIO", 102 [TEGRA_MUX_XIO] = "XIO",
103 [TEGRA_MUX_BLINK] = "BLINK",
104 [TEGRA_MUX_CEC] = "CEC",
105 [TEGRA_MUX_CLK12] = "CLK12",
106 [TEGRA_MUX_DAP] = "DAP",
107 [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
108 [TEGRA_MUX_DDR] = "DDR",
109 [TEGRA_MUX_DEV3] = "DEV3",
110 [TEGRA_MUX_DTV] = "DTV",
111 [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
112 [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
113 [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
114 [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
115 [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
116 [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
117 [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
118 [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
119 [TEGRA_MUX_HDA] = "HDA",
120 [TEGRA_MUX_HSI] = "HSI",
121 [TEGRA_MUX_I2C4] = "I2C4",
122 [TEGRA_MUX_I2C5] = "I2C5",
123 [TEGRA_MUX_I2CPWR] = "I2CPWR",
124 [TEGRA_MUX_I2S0] = "I2S0",
125 [TEGRA_MUX_I2S1] = "I2S1",
126 [TEGRA_MUX_I2S2] = "I2S2",
127 [TEGRA_MUX_I2S3] = "I2S3",
128 [TEGRA_MUX_I2S4] = "I2S4",
129 [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
130 [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
131 [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
132 [TEGRA_MUX_PWM0] = "PWM0",
133 [TEGRA_MUX_PWM1] = "PWM2",
134 [TEGRA_MUX_PWM2] = "PWM2",
135 [TEGRA_MUX_PWM3] = "PWM3",
136 [TEGRA_MUX_SATA] = "SATA",
137 [TEGRA_MUX_SPI5] = "SPI5",
138 [TEGRA_MUX_SPI6] = "SPI6",
139 [TEGRA_MUX_SYSCLK] = "SYSCLK",
140 [TEGRA_MUX_VGP1] = "VGP1",
141 [TEGRA_MUX_VGP2] = "VGP2",
142 [TEGRA_MUX_VGP3] = "VGP3",
143 [TEGRA_MUX_VGP4] = "VGP4",
144 [TEGRA_MUX_VGP5] = "VGP5",
145 [TEGRA_MUX_VGP6] = "VGP6",
100 [TEGRA_MUX_SAFE] = "<safe>", 146 [TEGRA_MUX_SAFE] = "<safe>",
101}; 147};
102 148
@@ -116,9 +162,9 @@ static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
116 162
117static DEFINE_SPINLOCK(mux_lock); 163static DEFINE_SPINLOCK(mux_lock);
118 164
119static const char *pingroup_name(enum tegra_pingroup pg) 165static const char *pingroup_name(int pg)
120{ 166{
121 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 167 if (pg < 0 || pg >= pingroup_max)
122 return "<UNKNOWN>"; 168 return "<UNKNOWN>";
123 169
124 return pingroups[pg].name; 170 return pingroups[pg].name;
@@ -189,10 +235,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
189 int i; 235 int i;
190 unsigned long reg; 236 unsigned long reg;
191 unsigned long flags; 237 unsigned long flags;
192 enum tegra_pingroup pg = config->pingroup; 238 int pg = config->pingroup;
193 enum tegra_mux_func func = config->func; 239 enum tegra_mux_func func = config->func;
194 240
195 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 241 if (pg < 0 || pg >= pingroup_max)
196 return -ERANGE; 242 return -ERANGE;
197 243
198 if (pingroups[pg].mux_reg < 0) 244 if (pingroups[pg].mux_reg < 0)
@@ -230,13 +276,12 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
230 return 0; 276 return 0;
231} 277}
232 278
233int tegra_pinmux_set_tristate(enum tegra_pingroup pg, 279int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
234 enum tegra_tristate tristate)
235{ 280{
236 unsigned long reg; 281 unsigned long reg;
237 unsigned long flags; 282 unsigned long flags;
238 283
239 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 284 if (pg < 0 || pg >= pingroup_max)
240 return -ERANGE; 285 return -ERANGE;
241 286
242 if (pingroups[pg].tri_reg < 0) 287 if (pingroups[pg].tri_reg < 0)
@@ -255,13 +300,12 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
255 return 0; 300 return 0;
256} 301}
257 302
258int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, 303int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
259 enum tegra_pullupdown pupd)
260{ 304{
261 unsigned long reg; 305 unsigned long reg;
262 unsigned long flags; 306 unsigned long flags;
263 307
264 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 308 if (pg < 0 || pg >= pingroup_max)
265 return -ERANGE; 309 return -ERANGE;
266 310
267 if (pingroups[pg].pupd_reg < 0) 311 if (pingroups[pg].pupd_reg < 0)
@@ -287,7 +331,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
287 331
288static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config) 332static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
289{ 333{
290 enum tegra_pingroup pingroup = config->pingroup; 334 int pingroup = config->pingroup;
291 enum tegra_mux_func func = config->func; 335 enum tegra_mux_func func = config->func;
292 enum tegra_pullupdown pupd = config->pupd; 336 enum tegra_pullupdown pupd = config->pupd;
293 enum tegra_tristate tristate = config->tristate; 337 enum tegra_tristate tristate = config->tristate;
@@ -323,9 +367,9 @@ void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int l
323 tegra_pinmux_config_pingroup(&config[i]); 367 tegra_pinmux_config_pingroup(&config[i]);
324} 368}
325 369
326static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) 370static const char *drive_pinmux_name(int pg)
327{ 371{
328 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 372 if (pg < 0 || pg >= drive_max)
329 return "<UNKNOWN>"; 373 return "<UNKNOWN>";
330 374
331 return drive_pingroups[pg].name; 375 return drive_pingroups[pg].name;
@@ -352,12 +396,11 @@ static const char *slew_name(unsigned long val)
352 return tegra_slew_names[val]; 396 return tegra_slew_names[val];
353} 397}
354 398
355static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, 399static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
356 enum tegra_hsm hsm)
357{ 400{
358 unsigned long flags; 401 unsigned long flags;
359 u32 reg; 402 u32 reg;
360 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 403 if (pg < 0 || pg >= drive_max)
361 return -ERANGE; 404 return -ERANGE;
362 405
363 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE) 406 if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
@@ -377,12 +420,11 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
377 return 0; 420 return 0;
378} 421}
379 422
380static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, 423static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
381 enum tegra_schmitt schmitt)
382{ 424{
383 unsigned long flags; 425 unsigned long flags;
384 u32 reg; 426 u32 reg;
385 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 427 if (pg < 0 || pg >= drive_max)
386 return -ERANGE; 428 return -ERANGE;
387 429
388 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE) 430 if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
@@ -402,12 +444,11 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
402 return 0; 444 return 0;
403} 445}
404 446
405static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, 447static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
406 enum tegra_drive drive)
407{ 448{
408 unsigned long flags; 449 unsigned long flags;
409 u32 reg; 450 u32 reg;
410 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 451 if (pg < 0 || pg >= drive_max)
411 return -ERANGE; 452 return -ERANGE;
412 453
413 if (drive < 0 || drive >= TEGRA_MAX_DRIVE) 454 if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
@@ -425,12 +466,12 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
425 return 0; 466 return 0;
426} 467}
427 468
428static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, 469static int tegra_drive_pinmux_set_pull_down(int pg,
429 enum tegra_pull_strength pull_down) 470 enum tegra_pull_strength pull_down)
430{ 471{
431 unsigned long flags; 472 unsigned long flags;
432 u32 reg; 473 u32 reg;
433 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 474 if (pg < 0 || pg >= drive_max)
434 return -ERANGE; 475 return -ERANGE;
435 476
436 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL) 477 if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
@@ -448,12 +489,12 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
448 return 0; 489 return 0;
449} 490}
450 491
451static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, 492static int tegra_drive_pinmux_set_pull_up(int pg,
452 enum tegra_pull_strength pull_up) 493 enum tegra_pull_strength pull_up)
453{ 494{
454 unsigned long flags; 495 unsigned long flags;
455 u32 reg; 496 u32 reg;
456 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 497 if (pg < 0 || pg >= drive_max)
457 return -ERANGE; 498 return -ERANGE;
458 499
459 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL) 500 if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
@@ -471,12 +512,12 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
471 return 0; 512 return 0;
472} 513}
473 514
474static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, 515static int tegra_drive_pinmux_set_slew_rising(int pg,
475 enum tegra_slew slew_rising) 516 enum tegra_slew slew_rising)
476{ 517{
477 unsigned long flags; 518 unsigned long flags;
478 u32 reg; 519 u32 reg;
479 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 520 if (pg < 0 || pg >= drive_max)
480 return -ERANGE; 521 return -ERANGE;
481 522
482 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW) 523 if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
@@ -494,12 +535,12 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
494 return 0; 535 return 0;
495} 536}
496 537
497static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, 538static int tegra_drive_pinmux_set_slew_falling(int pg,
498 enum tegra_slew slew_falling) 539 enum tegra_slew slew_falling)
499{ 540{
500 unsigned long flags; 541 unsigned long flags;
501 u32 reg; 542 u32 reg;
502 if (pg < 0 || pg >= TEGRA_MAX_DRIVE_PINGROUP) 543 if (pg < 0 || pg >= drive_max)
503 return -ERANGE; 544 return -ERANGE;
504 545
505 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW) 546 if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
@@ -517,7 +558,7 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
517 return 0; 558 return 0;
518} 559}
519 560
520static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup, 561static void tegra_drive_pinmux_config_pingroup(int pingroup,
521 enum tegra_hsm hsm, 562 enum tegra_hsm hsm,
522 enum tegra_schmitt schmitt, 563 enum tegra_schmitt schmitt,
523 enum tegra_drive drive, 564 enum tegra_drive drive,
@@ -596,7 +637,7 @@ void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *conf
596 for (i = 0; i < len; i++) { 637 for (i = 0; i < len; i++) {
597 int err; 638 int err;
598 c = config[i]; 639 c = config[i];
599 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) { 640 if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
600 WARN_ON(1); 641 WARN_ON(1);
601 continue; 642 continue;
602 } 643 }
@@ -617,7 +658,7 @@ void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config
617 for (i = 0; i < len; i++) { 658 for (i = 0; i < len; i++) {
618 int err; 659 int err;
619 if (config[i].pingroup < 0 || 660 if (config[i].pingroup < 0 ||
620 config[i].pingroup >= TEGRA_MAX_PINGROUP) { 661 config[i].pingroup >= pingroup_max) {
621 WARN_ON(1); 662 WARN_ON(1);
622 continue; 663 continue;
623 } 664 }
@@ -635,7 +676,7 @@ void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *conf
635{ 676{
636 int i; 677 int i;
637 int err; 678 int err;
638 enum tegra_pingroup pingroup; 679 int pingroup;
639 680
640 for (i = 0; i < len; i++) { 681 for (i = 0; i < len; i++) {
641 pingroup = config[i].pingroup; 682 pingroup = config[i].pingroup;
@@ -654,7 +695,7 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
654{ 695{
655 int i; 696 int i;
656 int err; 697 int err;
657 enum tegra_pingroup pingroup; 698 int pingroup;
658 699
659 for (i = 0; i < len; i++) { 700 for (i = 0; i < len; i++) {
660 pingroup = config[i].pingroup; 701 pingroup = config[i].pingroup;
@@ -668,11 +709,36 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co
668 } 709 }
669} 710}
670 711
712static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
713#ifdef CONFIG_ARCH_TEGRA_2x_SOC
714 { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
715#endif
716#ifdef CONFIG_ARCH_TEGRA_3x_SOC
717 { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
718#endif
719 { },
720};
721
671static int __devinit tegra_pinmux_probe(struct platform_device *pdev) 722static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
672{ 723{
673 struct resource *res; 724 struct resource *res;
674 int i; 725 int i;
675 int config_bad = 0; 726 int config_bad = 0;
727 const struct of_device_id *match;
728
729 match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
730
731 if (match)
732 ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
733 &drive_pingroups, &drive_max);
734#ifdef CONFIG_ARCH_TEGRA_2x_SOC
735 else
736 /* no device tree available, so we must be on tegra20 */
737 tegra20_pinmux_init(&pingroups, &pingroup_max,
738 &drive_pingroups, &drive_max);
739#else
740 pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
741#endif
676 742
677 for (i = 0; ; i++) { 743 for (i = 0; ; i++) {
678 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 744 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -681,7 +747,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
681 } 747 }
682 nbanks = i; 748 nbanks = i;
683 749
684 for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { 750 for (i = 0; i < pingroup_max; i++) {
685 if (pingroups[i].tri_bank >= nbanks) { 751 if (pingroups[i].tri_bank >= nbanks) {
686 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); 752 dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
687 config_bad = 1; 753 config_bad = 1;
@@ -698,7 +764,7 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
698 } 764 }
699 } 765 }
700 766
701 for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { 767 for (i = 0; i < drive_max; i++) {
702 if (drive_pingroups[i].reg_bank >= nbanks) { 768 if (drive_pingroups[i].reg_bank >= nbanks) {
703 dev_err(&pdev->dev, 769 dev_err(&pdev->dev,
704 "drive pingroup %d: bad reg_bank\n", i); 770 "drive pingroup %d: bad reg_bank\n", i);
@@ -741,11 +807,6 @@ static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
741 return 0; 807 return 0;
742} 808}
743 809
744static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
745 { .compatible = "nvidia,tegra20-pinmux", },
746 { },
747};
748
749static struct platform_driver tegra_pinmux_driver = { 810static struct platform_driver tegra_pinmux_driver = {
750 .driver = { 811 .driver = {
751 .name = "tegra-pinmux", 812 .name = "tegra-pinmux",
@@ -779,7 +840,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
779 int i; 840 int i;
780 int len; 841 int len;
781 842
782 for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { 843 for (i = 0; i < pingroup_max; i++) {
783 unsigned long reg; 844 unsigned long reg;
784 unsigned long tri; 845 unsigned long tri;
785 unsigned long mux; 846 unsigned long mux;
@@ -850,7 +911,7 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
850 int i; 911 int i;
851 int len; 912 int len;
852 913
853 for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { 914 for (i = 0; i < drive_max; i++) {
854 u32 reg; 915 u32 reg;
855 916
856 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s", 917 seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 371869d8ea01..ff9e6b6c0460 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -174,7 +174,7 @@ static int tegra_periph_clk_enable_refcount[3 * 32];
174#define pmc_readl(reg) \ 174#define pmc_readl(reg) \
175 __raw_readl(reg_pmc_base + (reg)) 175 __raw_readl(reg_pmc_base + (reg))
176 176
177unsigned long clk_measure_input_freq(void) 177static unsigned long clk_measure_input_freq(void)
178{ 178{
179 u32 clock_autodetect; 179 u32 clock_autodetect;
180 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); 180 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
@@ -278,18 +278,6 @@ static struct clk_ops tegra_clk_m_ops = {
278 .disable = tegra2_clk_m_disable, 278 .disable = tegra2_clk_m_disable,
279}; 279};
280 280
281void tegra2_periph_reset_assert(struct clk *c)
282{
283 BUG_ON(!c->ops->reset);
284 c->ops->reset(c, true);
285}
286
287void tegra2_periph_reset_deassert(struct clk *c)
288{
289 BUG_ON(!c->ops->reset);
290 c->ops->reset(c, false);
291}
292
293/* super clock functions */ 281/* super clock functions */
294/* "super clocks" on tegra have two-stage muxes and a clock skipping 282/* "super clocks" on tegra have two-stage muxes and a clock skipping
295 * super divider. We will ignore the clock skipping divider, since we 283 * super divider. We will ignore the clock skipping divider, since we
@@ -1132,6 +1120,9 @@ static struct clk_ops tegra_periph_clk_ops = {
1132void tegra2_sdmmc_tap_delay(struct clk *c, int delay) 1120void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1133{ 1121{
1134 u32 reg; 1122 u32 reg;
1123 unsigned long flags;
1124
1125 spin_lock_irqsave(&c->spinlock, flags);
1135 1126
1136 delay = clamp(delay, 0, 15); 1127 delay = clamp(delay, 0, 15);
1137 reg = clk_readl(c->reg); 1128 reg = clk_readl(c->reg);
@@ -1139,6 +1130,8 @@ void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
1139 reg |= SDMMC_CLK_INT_FB_SEL; 1130 reg |= SDMMC_CLK_INT_FB_SEL;
1140 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; 1131 reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
1141 clk_writel(reg, c->reg); 1132 clk_writel(reg, c->reg);
1133
1134 spin_unlock_irqrestore(&c->spinlock, flags);
1142} 1135}
1143 1136
1144/* External memory controller clock ops */ 1137/* External memory controller clock ops */
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index e2272d263a83..6366654b54c5 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -182,20 +182,28 @@ static struct irqaction tegra_timer_irq = {
182static void __init tegra_init_timer(void) 182static void __init tegra_init_timer(void)
183{ 183{
184 struct clk *clk; 184 struct clk *clk;
185 unsigned long rate = clk_measure_input_freq(); 185 unsigned long rate;
186 int ret; 186 int ret;
187 187
188 clk = clk_get_sys("timer", NULL); 188 clk = clk_get_sys("timer", NULL);
189 BUG_ON(IS_ERR(clk)); 189 if (IS_ERR(clk)) {
190 clk_enable(clk); 190 pr_warn("Unable to get timer clock."
191 " Assuming 12Mhz input clock.\n");
192 rate = 12000000;
193 } else {
194 clk_enable(clk);
195 rate = clk_get_rate(clk);
196 }
191 197
192 /* 198 /*
193 * rtc registers are used by read_persistent_clock, keep the rtc clock 199 * rtc registers are used by read_persistent_clock, keep the rtc clock
194 * enabled 200 * enabled
195 */ 201 */
196 clk = clk_get_sys("rtc-tegra", NULL); 202 clk = clk_get_sys("rtc-tegra", NULL);
197 BUG_ON(IS_ERR(clk)); 203 if (IS_ERR(clk))
198 clk_enable(clk); 204 pr_warn("Unable to get rtc-tegra clock\n");
205 else
206 clk_enable(clk);
199 207
200#ifdef CONFIG_HAVE_ARM_TWD 208#ifdef CONFIG_HAVE_ARM_TWD
201 twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); 209 twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 09:39:49 -0500