2 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index e945ae28ee77..f4ef5eb317bd 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -223,7 +223,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
          *  - Change the source selector to invalid to stop the DMA from
          *    FIFO to memory.
          *  - Read the status register to know the number of pending
-         *    bytes to be transfered.
+         *    bytes to be transferred.
          *  - Finally stop or program the DMA to the next buffer in the
          *    list.
          */
@@ -244,7 +244,7 @@ int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
         if (status & STA_BUSY)
                 req->bytes_transferred -= to_transfer;
 
-        /* In continous transfer mode, DMA only tracks the count of the
+        /* In continuous transfer mode, DMA only tracks the count of the
          * half DMA buffer. So, if the DMA already finished half the DMA
          * then add the half buffer to the completed count.
          *
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 39011bd9a925..d0132e8031a1 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -92,11 +92,11 @@ struct tegra_dma_req {
         /*  This is a called from the DMA ISR context when the DMA is still in
          *  progress and is actively filling same buffer.
          *
-         *  In case of continous mode receive, this threshold is 1/2 the buffer
+         *  In case of continuous mode receive, this threshold is 1/2 the buffer
          *  size. In other cases, this will not even be called as there is no
          *  hardware support for it.
          *
-         * In the case of continous mode receive, if there is next req already
+         * In the case of continuous mode receive, if there is next req already
          * queued, DMA programs the HW to use that req when this req is
          * completed. If there is no "next req" queued, then DMA ISR doesn't do
          * anything before calling this callback.