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-rw-r--r--arch/arm/mach-tegra/usb_phy.c817
1 files changed, 0 insertions, 817 deletions
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
deleted file mode 100644
index 022b33a05c3a..000000000000
--- a/arch/arm/mach-tegra/usb_phy.c
+++ /dev/null
@@ -1,817 +0,0 @@
1/*
2 * arch/arm/mach-tegra/usb_phy.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/resource.h>
22#include <linux/delay.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/export.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/gpio.h>
29#include <linux/of_gpio.h>
30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h>
32#include <asm/mach-types.h>
33#include <mach/gpio-tegra.h>
34#include <mach/usb_phy.h>
35#include <mach/iomap.h>
36
37#define ULPI_VIEWPORT 0x170
38
39#define USB_PORTSC1 0x184
40#define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
41#define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26)
42#define USB_PORTSC1_PHCD (1 << 23)
43#define USB_PORTSC1_WKOC (1 << 22)
44#define USB_PORTSC1_WKDS (1 << 21)
45#define USB_PORTSC1_WKCN (1 << 20)
46#define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16)
47#define USB_PORTSC1_PP (1 << 12)
48#define USB_PORTSC1_SUSP (1 << 7)
49#define USB_PORTSC1_PE (1 << 2)
50#define USB_PORTSC1_CCS (1 << 0)
51
52#define USB_SUSP_CTRL 0x400
53#define USB_WAKE_ON_CNNT_EN_DEV (1 << 3)
54#define USB_WAKE_ON_DISCON_EN_DEV (1 << 4)
55#define USB_SUSP_CLR (1 << 5)
56#define USB_PHY_CLK_VALID (1 << 7)
57#define UTMIP_RESET (1 << 11)
58#define UHSIC_RESET (1 << 11)
59#define UTMIP_PHY_ENABLE (1 << 12)
60#define ULPI_PHY_ENABLE (1 << 13)
61#define USB_SUSP_SET (1 << 14)
62#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
63
64#define USB1_LEGACY_CTRL 0x410
65#define USB1_NO_LEGACY_MODE (1 << 0)
66#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
67#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
68#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
69 (1 << 1)
70#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
71#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
72
73#define ULPI_TIMING_CTRL_0 0x424
74#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
75#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
76
77#define ULPI_TIMING_CTRL_1 0x428
78#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
79#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
80#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
81#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
82#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
83#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
84
85#define UTMIP_PLL_CFG1 0x804
86#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
87#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
88
89#define UTMIP_XCVR_CFG0 0x808
90#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
91#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
92#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
93#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
94#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
95#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
96#define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25)
97
98#define UTMIP_BIAS_CFG0 0x80c
99#define UTMIP_OTGPD (1 << 11)
100#define UTMIP_BIASPD (1 << 10)
101
102#define UTMIP_HSRX_CFG0 0x810
103#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
104#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
105
106#define UTMIP_HSRX_CFG1 0x814
107#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
108
109#define UTMIP_TX_CFG0 0x820
110#define UTMIP_FS_PREABMLE_J (1 << 19)
111#define UTMIP_HS_DISCON_DISABLE (1 << 8)
112
113#define UTMIP_MISC_CFG0 0x824
114#define UTMIP_DPDM_OBSERVE (1 << 26)
115#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
116#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
117#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
118#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
119#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
120#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
121
122#define UTMIP_MISC_CFG1 0x828
123#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
124#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
125
126#define UTMIP_DEBOUNCE_CFG0 0x82c
127#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
128
129#define UTMIP_BAT_CHRG_CFG0 0x830
130#define UTMIP_PD_CHRG (1 << 0)
131
132#define UTMIP_SPARE_CFG0 0x834
133#define FUSE_SETUP_SEL (1 << 3)
134
135#define UTMIP_XCVR_CFG1 0x838
136#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
137#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
138#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
139#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
140
141#define UTMIP_BIAS_CFG1 0x83c
142#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
143
144static DEFINE_SPINLOCK(utmip_pad_lock);
145static int utmip_pad_count;
146
147struct tegra_xtal_freq {
148 int freq;
149 u8 enable_delay;
150 u8 stable_count;
151 u8 active_delay;
152 u8 xtal_freq_count;
153 u16 debounce;
154};
155
156static const struct tegra_xtal_freq tegra_freq_table[] = {
157 {
158 .freq = 12000000,
159 .enable_delay = 0x02,
160 .stable_count = 0x2F,
161 .active_delay = 0x04,
162 .xtal_freq_count = 0x76,
163 .debounce = 0x7530,
164 },
165 {
166 .freq = 13000000,
167 .enable_delay = 0x02,
168 .stable_count = 0x33,
169 .active_delay = 0x05,
170 .xtal_freq_count = 0x7F,
171 .debounce = 0x7EF4,
172 },
173 {
174 .freq = 19200000,
175 .enable_delay = 0x03,
176 .stable_count = 0x4B,
177 .active_delay = 0x06,
178 .xtal_freq_count = 0xBB,
179 .debounce = 0xBB80,
180 },
181 {
182 .freq = 26000000,
183 .enable_delay = 0x04,
184 .stable_count = 0x66,
185 .active_delay = 0x09,
186 .xtal_freq_count = 0xFE,
187 .debounce = 0xFDE8,
188 },
189};
190
191static struct tegra_utmip_config utmip_default[] = {
192 [0] = {
193 .hssync_start_delay = 9,
194 .idle_wait_delay = 17,
195 .elastic_limit = 16,
196 .term_range_adj = 6,
197 .xcvr_setup = 9,
198 .xcvr_lsfslew = 1,
199 .xcvr_lsrslew = 1,
200 },
201 [2] = {
202 .hssync_start_delay = 9,
203 .idle_wait_delay = 17,
204 .elastic_limit = 16,
205 .term_range_adj = 6,
206 .xcvr_setup = 9,
207 .xcvr_lsfslew = 2,
208 .xcvr_lsrslew = 2,
209 },
210};
211
212static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
213{
214 return (phy->instance == 1);
215}
216
217static int utmip_pad_open(struct tegra_usb_phy *phy)
218{
219 phy->pad_clk = clk_get_sys("utmip-pad", NULL);
220 if (IS_ERR(phy->pad_clk)) {
221 pr_err("%s: can't get utmip pad clock\n", __func__);
222 return PTR_ERR(phy->pad_clk);
223 }
224
225 if (phy->instance == 0) {
226 phy->pad_regs = phy->regs;
227 } else {
228 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
229 if (!phy->pad_regs) {
230 pr_err("%s: can't remap usb registers\n", __func__);
231 clk_put(phy->pad_clk);
232 return -ENOMEM;
233 }
234 }
235 return 0;
236}
237
238static void utmip_pad_close(struct tegra_usb_phy *phy)
239{
240 if (phy->instance != 0)
241 iounmap(phy->pad_regs);
242 clk_put(phy->pad_clk);
243}
244
245static void utmip_pad_power_on(struct tegra_usb_phy *phy)
246{
247 unsigned long val, flags;
248 void __iomem *base = phy->pad_regs;
249
250 clk_prepare_enable(phy->pad_clk);
251
252 spin_lock_irqsave(&utmip_pad_lock, flags);
253
254 if (utmip_pad_count++ == 0) {
255 val = readl(base + UTMIP_BIAS_CFG0);
256 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
257 writel(val, base + UTMIP_BIAS_CFG0);
258 }
259
260 spin_unlock_irqrestore(&utmip_pad_lock, flags);
261
262 clk_disable_unprepare(phy->pad_clk);
263}
264
265static int utmip_pad_power_off(struct tegra_usb_phy *phy)
266{
267 unsigned long val, flags;
268 void __iomem *base = phy->pad_regs;
269
270 if (!utmip_pad_count) {
271 pr_err("%s: utmip pad already powered off\n", __func__);
272 return -EINVAL;
273 }
274
275 clk_prepare_enable(phy->pad_clk);
276
277 spin_lock_irqsave(&utmip_pad_lock, flags);
278
279 if (--utmip_pad_count == 0) {
280 val = readl(base + UTMIP_BIAS_CFG0);
281 val |= UTMIP_OTGPD | UTMIP_BIASPD;
282 writel(val, base + UTMIP_BIAS_CFG0);
283 }
284
285 spin_unlock_irqrestore(&utmip_pad_lock, flags);
286
287 clk_disable_unprepare(phy->pad_clk);
288
289 return 0;
290}
291
292static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
293{
294 unsigned long timeout = 2000;
295 do {
296 if ((readl(reg) & mask) == result)
297 return 0;
298 udelay(1);
299 timeout--;
300 } while (timeout);
301 return -1;
302}
303
304static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
305{
306 unsigned long val;
307 void __iomem *base = phy->regs;
308
309 if (phy->instance == 0) {
310 val = readl(base + USB_SUSP_CTRL);
311 val |= USB_SUSP_SET;
312 writel(val, base + USB_SUSP_CTRL);
313
314 udelay(10);
315
316 val = readl(base + USB_SUSP_CTRL);
317 val &= ~USB_SUSP_SET;
318 writel(val, base + USB_SUSP_CTRL);
319 }
320
321 if (phy->instance == 2) {
322 val = readl(base + USB_PORTSC1);
323 val |= USB_PORTSC1_PHCD;
324 writel(val, base + USB_PORTSC1);
325 }
326
327 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
328 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
329}
330
331static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
332{
333 unsigned long val;
334 void __iomem *base = phy->regs;
335
336 if (phy->instance == 0) {
337 val = readl(base + USB_SUSP_CTRL);
338 val |= USB_SUSP_CLR;
339 writel(val, base + USB_SUSP_CTRL);
340
341 udelay(10);
342
343 val = readl(base + USB_SUSP_CTRL);
344 val &= ~USB_SUSP_CLR;
345 writel(val, base + USB_SUSP_CTRL);
346 }
347
348 if (phy->instance == 2) {
349 val = readl(base + USB_PORTSC1);
350 val &= ~USB_PORTSC1_PHCD;
351 writel(val, base + USB_PORTSC1);
352 }
353
354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
355 USB_PHY_CLK_VALID))
356 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
357}
358
359static int utmi_phy_power_on(struct tegra_usb_phy *phy)
360{
361 unsigned long val;
362 void __iomem *base = phy->regs;
363 struct tegra_utmip_config *config = phy->config;
364
365 val = readl(base + USB_SUSP_CTRL);
366 val |= UTMIP_RESET;
367 writel(val, base + USB_SUSP_CTRL);
368
369 if (phy->instance == 0) {
370 val = readl(base + USB1_LEGACY_CTRL);
371 val |= USB1_NO_LEGACY_MODE;
372 writel(val, base + USB1_LEGACY_CTRL);
373 }
374
375 val = readl(base + UTMIP_TX_CFG0);
376 val &= ~UTMIP_FS_PREABMLE_J;
377 writel(val, base + UTMIP_TX_CFG0);
378
379 val = readl(base + UTMIP_HSRX_CFG0);
380 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
381 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
382 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
383 writel(val, base + UTMIP_HSRX_CFG0);
384
385 val = readl(base + UTMIP_HSRX_CFG1);
386 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
387 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
388 writel(val, base + UTMIP_HSRX_CFG1);
389
390 val = readl(base + UTMIP_DEBOUNCE_CFG0);
391 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
392 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
393 writel(val, base + UTMIP_DEBOUNCE_CFG0);
394
395 val = readl(base + UTMIP_MISC_CFG0);
396 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
397 writel(val, base + UTMIP_MISC_CFG0);
398
399 val = readl(base + UTMIP_MISC_CFG1);
400 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
401 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
402 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
403 writel(val, base + UTMIP_MISC_CFG1);
404
405 val = readl(base + UTMIP_PLL_CFG1);
406 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
407 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
408 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
409 writel(val, base + UTMIP_PLL_CFG1);
410
411 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
412 val = readl(base + USB_SUSP_CTRL);
413 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
414 writel(val, base + USB_SUSP_CTRL);
415 }
416
417 utmip_pad_power_on(phy);
418
419 val = readl(base + UTMIP_XCVR_CFG0);
420 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
421 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
422 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
423 UTMIP_XCVR_HSSLEW_MSB(~0));
424 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
425 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
426 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
427 writel(val, base + UTMIP_XCVR_CFG0);
428
429 val = readl(base + UTMIP_XCVR_CFG1);
430 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
431 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
432 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
433 writel(val, base + UTMIP_XCVR_CFG1);
434
435 val = readl(base + UTMIP_BAT_CHRG_CFG0);
436 val &= ~UTMIP_PD_CHRG;
437 writel(val, base + UTMIP_BAT_CHRG_CFG0);
438
439 val = readl(base + UTMIP_BIAS_CFG1);
440 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
441 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
442 writel(val, base + UTMIP_BIAS_CFG1);
443
444 if (phy->instance == 0) {
445 val = readl(base + UTMIP_SPARE_CFG0);
446 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
447 val &= ~FUSE_SETUP_SEL;
448 else
449 val |= FUSE_SETUP_SEL;
450 writel(val, base + UTMIP_SPARE_CFG0);
451 }
452
453 if (phy->instance == 2) {
454 val = readl(base + USB_SUSP_CTRL);
455 val |= UTMIP_PHY_ENABLE;
456 writel(val, base + USB_SUSP_CTRL);
457 }
458
459 val = readl(base + USB_SUSP_CTRL);
460 val &= ~UTMIP_RESET;
461 writel(val, base + USB_SUSP_CTRL);
462
463 if (phy->instance == 0) {
464 val = readl(base + USB1_LEGACY_CTRL);
465 val &= ~USB1_VBUS_SENSE_CTL_MASK;
466 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
467 writel(val, base + USB1_LEGACY_CTRL);
468
469 val = readl(base + USB_SUSP_CTRL);
470 val &= ~USB_SUSP_SET;
471 writel(val, base + USB_SUSP_CTRL);
472 }
473
474 utmi_phy_clk_enable(phy);
475
476 if (phy->instance == 2) {
477 val = readl(base + USB_PORTSC1);
478 val &= ~USB_PORTSC1_PTS(~0);
479 writel(val, base + USB_PORTSC1);
480 }
481
482 return 0;
483}
484
485static void utmi_phy_power_off(struct tegra_usb_phy *phy)
486{
487 unsigned long val;
488 void __iomem *base = phy->regs;
489
490 utmi_phy_clk_disable(phy);
491
492 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
493 val = readl(base + USB_SUSP_CTRL);
494 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
495 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
496 writel(val, base + USB_SUSP_CTRL);
497 }
498
499 val = readl(base + USB_SUSP_CTRL);
500 val |= UTMIP_RESET;
501 writel(val, base + USB_SUSP_CTRL);
502
503 val = readl(base + UTMIP_BAT_CHRG_CFG0);
504 val |= UTMIP_PD_CHRG;
505 writel(val, base + UTMIP_BAT_CHRG_CFG0);
506
507 val = readl(base + UTMIP_XCVR_CFG0);
508 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
509 UTMIP_FORCE_PDZI_POWERDOWN;
510 writel(val, base + UTMIP_XCVR_CFG0);
511
512 val = readl(base + UTMIP_XCVR_CFG1);
513 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
514 UTMIP_FORCE_PDDR_POWERDOWN;
515 writel(val, base + UTMIP_XCVR_CFG1);
516
517 utmip_pad_power_off(phy);
518}
519
520static void utmi_phy_preresume(struct tegra_usb_phy *phy)
521{
522 unsigned long val;
523 void __iomem *base = phy->regs;
524
525 val = readl(base + UTMIP_TX_CFG0);
526 val |= UTMIP_HS_DISCON_DISABLE;
527 writel(val, base + UTMIP_TX_CFG0);
528}
529
530static void utmi_phy_postresume(struct tegra_usb_phy *phy)
531{
532 unsigned long val;
533 void __iomem *base = phy->regs;
534
535 val = readl(base + UTMIP_TX_CFG0);
536 val &= ~UTMIP_HS_DISCON_DISABLE;
537 writel(val, base + UTMIP_TX_CFG0);
538}
539
540static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
541 enum tegra_usb_phy_port_speed port_speed)
542{
543 unsigned long val;
544 void __iomem *base = phy->regs;
545
546 val = readl(base + UTMIP_MISC_CFG0);
547 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
548 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
549 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
550 else
551 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
552 writel(val, base + UTMIP_MISC_CFG0);
553 udelay(1);
554
555 val = readl(base + UTMIP_MISC_CFG0);
556 val |= UTMIP_DPDM_OBSERVE;
557 writel(val, base + UTMIP_MISC_CFG0);
558 udelay(10);
559}
560
561static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
562{
563 unsigned long val;
564 void __iomem *base = phy->regs;
565
566 val = readl(base + UTMIP_MISC_CFG0);
567 val &= ~UTMIP_DPDM_OBSERVE;
568 writel(val, base + UTMIP_MISC_CFG0);
569 udelay(10);
570}
571
572static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
573{
574 int ret;
575 unsigned long val;
576 void __iomem *base = phy->regs;
577 struct tegra_ulpi_config *config = phy->config;
578
579 gpio_direction_output(config->reset_gpio, 0);
580 msleep(5);
581 gpio_direction_output(config->reset_gpio, 1);
582
583 clk_prepare_enable(phy->clk);
584 msleep(1);
585
586 val = readl(base + USB_SUSP_CTRL);
587 val |= UHSIC_RESET;
588 writel(val, base + USB_SUSP_CTRL);
589
590 val = readl(base + ULPI_TIMING_CTRL_0);
591 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
592 writel(val, base + ULPI_TIMING_CTRL_0);
593
594 val = readl(base + USB_SUSP_CTRL);
595 val |= ULPI_PHY_ENABLE;
596 writel(val, base + USB_SUSP_CTRL);
597
598 val = 0;
599 writel(val, base + ULPI_TIMING_CTRL_1);
600
601 val |= ULPI_DATA_TRIMMER_SEL(4);
602 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
603 val |= ULPI_DIR_TRIMMER_SEL(4);
604 writel(val, base + ULPI_TIMING_CTRL_1);
605 udelay(10);
606
607 val |= ULPI_DATA_TRIMMER_LOAD;
608 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
609 val |= ULPI_DIR_TRIMMER_LOAD;
610 writel(val, base + ULPI_TIMING_CTRL_1);
611
612 /* Fix VbusInvalid due to floating VBUS */
613 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
614 if (ret) {
615 pr_err("%s: ulpi write failed\n", __func__);
616 return ret;
617 }
618
619 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
620 if (ret) {
621 pr_err("%s: ulpi write failed\n", __func__);
622 return ret;
623 }
624
625 val = readl(base + USB_PORTSC1);
626 val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
627 writel(val, base + USB_PORTSC1);
628
629 val = readl(base + USB_SUSP_CTRL);
630 val |= USB_SUSP_CLR;
631 writel(val, base + USB_SUSP_CTRL);
632 udelay(100);
633
634 val = readl(base + USB_SUSP_CTRL);
635 val &= ~USB_SUSP_CLR;
636 writel(val, base + USB_SUSP_CTRL);
637
638 return 0;
639}
640
641static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
642{
643 unsigned long val;
644 void __iomem *base = phy->regs;
645 struct tegra_ulpi_config *config = phy->config;
646
647 /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
648 * Controller to immediately bring the ULPI PHY out of low power
649 */
650 val = readl(base + USB_PORTSC1);
651 val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
652 writel(val, base + USB_PORTSC1);
653
654 gpio_direction_output(config->reset_gpio, 0);
655 clk_disable(phy->clk);
656}
657
658struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
659 void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
660{
661 struct tegra_usb_phy *phy;
662 struct tegra_ulpi_config *ulpi_config;
663 unsigned long parent_rate;
664 int i;
665 int err;
666
667 phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
668 if (!phy)
669 return ERR_PTR(-ENOMEM);
670
671 phy->instance = instance;
672 phy->regs = regs;
673 phy->config = config;
674 phy->mode = phy_mode;
675
676 if (!phy->config) {
677 if (phy_is_ulpi(phy)) {
678 pr_err("%s: ulpi phy configuration missing", __func__);
679 err = -EINVAL;
680 goto err0;
681 } else {
682 phy->config = &utmip_default[instance];
683 }
684 }
685
686 phy->pll_u = clk_get_sys(NULL, "pll_u");
687 if (IS_ERR(phy->pll_u)) {
688 pr_err("Can't get pll_u clock\n");
689 err = PTR_ERR(phy->pll_u);
690 goto err0;
691 }
692 clk_prepare_enable(phy->pll_u);
693
694 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
695 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
696 if (tegra_freq_table[i].freq == parent_rate) {
697 phy->freq = &tegra_freq_table[i];
698 break;
699 }
700 }
701 if (!phy->freq) {
702 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
703 err = -EINVAL;
704 goto err1;
705 }
706
707 if (phy_is_ulpi(phy)) {
708 ulpi_config = config;
709 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
710 if (IS_ERR(phy->clk)) {
711 pr_err("%s: can't get ulpi clock\n", __func__);
712 err = -ENXIO;
713 goto err1;
714 }
715 if (!gpio_is_valid(ulpi_config->reset_gpio))
716 ulpi_config->reset_gpio =
717 of_get_named_gpio(dev->of_node,
718 "nvidia,phy-reset-gpio", 0);
719 if (!gpio_is_valid(ulpi_config->reset_gpio)) {
720 pr_err("%s: invalid reset gpio: %d\n", __func__,
721 ulpi_config->reset_gpio);
722 err = -EINVAL;
723 goto err1;
724 }
725 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
726 gpio_direction_output(ulpi_config->reset_gpio, 0);
727 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
728 phy->ulpi->io_priv = regs + ULPI_VIEWPORT;
729 } else {
730 err = utmip_pad_open(phy);
731 if (err < 0)
732 goto err1;
733 }
734
735 return phy;
736
737err1:
738 clk_disable_unprepare(phy->pll_u);
739 clk_put(phy->pll_u);
740err0:
741 kfree(phy);
742 return ERR_PTR(err);
743}
744EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
745
746int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
747{
748 if (phy_is_ulpi(phy))
749 return ulpi_phy_power_on(phy);
750 else
751 return utmi_phy_power_on(phy);
752}
753EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on);
754
755void tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
756{
757 if (phy_is_ulpi(phy))
758 ulpi_phy_power_off(phy);
759 else
760 utmi_phy_power_off(phy);
761}
762EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off);
763
764void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
765{
766 if (!phy_is_ulpi(phy))
767 utmi_phy_preresume(phy);
768}
769EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
770
771void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
772{
773 if (!phy_is_ulpi(phy))
774 utmi_phy_postresume(phy);
775}
776EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
777
778void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
779 enum tegra_usb_phy_port_speed port_speed)
780{
781 if (!phy_is_ulpi(phy))
782 utmi_phy_restore_start(phy, port_speed);
783}
784EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
785
786void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
787{
788 if (!phy_is_ulpi(phy))
789 utmi_phy_restore_end(phy);
790}
791EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
792
793void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
794{
795 if (!phy_is_ulpi(phy))
796 utmi_phy_clk_disable(phy);
797}
798EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
799
800void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
801{
802 if (!phy_is_ulpi(phy))
803 utmi_phy_clk_enable(phy);
804}
805EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);
806
807void tegra_usb_phy_close(struct tegra_usb_phy *phy)
808{
809 if (phy_is_ulpi(phy))
810 clk_put(phy->clk);
811 else
812 utmip_pad_close(phy);
813 clk_disable_unprepare(phy->pll_u);
814 clk_put(phy->pll_u);
815 kfree(phy);
816}
817EXPORT_SYMBOL_GPL(tegra_usb_phy_close);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 20:52:09 -0500