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Diffstat (limited to 'arch/arm/mach-tegra/timer.c')
-rw-r--r--arch/arm/mach-tegra/timer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 90350420c4e9..e2272d263a83 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -62,9 +62,9 @@ static struct timespec persistent_ts;
62static u64 persistent_ms, last_persistent_ms; 62static u64 persistent_ms, last_persistent_ms;
63 63
64#define timer_writel(value, reg) \ 64#define timer_writel(value, reg) \
65 __raw_writel(value, (u32)timer_reg_base + (reg)) 65 __raw_writel(value, timer_reg_base + (reg))
66#define timer_readl(reg) \ 66#define timer_readl(reg) \
67 __raw_readl((u32)timer_reg_base + (reg)) 67 __raw_readl(timer_reg_base + (reg))
68 68
69static int tegra_timer_set_next_event(unsigned long cycles, 69static int tegra_timer_set_next_event(unsigned long cycles,
70 struct clock_event_device *evt) 70 struct clock_event_device *evt)
@@ -133,7 +133,7 @@ static void notrace tegra_update_sched_clock(void)
133 * tegra_rtc driver could be executing to avoid race conditions 133 * tegra_rtc driver could be executing to avoid race conditions
134 * on the RTC shadow register 134 * on the RTC shadow register
135 */ 135 */
136u64 tegra_rtc_read_ms(void) 136static u64 tegra_rtc_read_ms(void)
137{ 137{
138 u32 ms = readl(rtc_base + RTC_MILLISECONDS); 138 u32 ms = readl(rtc_base + RTC_MILLISECONDS);
139 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); 139 u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);