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Diffstat (limited to 'arch/arm/mach-tegra/tegra30_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index efc000e32e1c..d7147779f8ea 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2045,9 +2045,7 @@ struct clk_ops tegra30_periph_clk_ops = {
2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) 2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2046{ 2046{
2047 struct clk *d = clk_get_sys(NULL, "pll_d"); 2047 struct clk *d = clk_get_sys(NULL, "pll_d");
2048 /* The DSIB parent selection bit is in PLLD base 2048 /* The DSIB parent selection bit is in PLLD base register */
2049 register - can not do direct r-m-w, must be
2050 protected by PLLD lock */
2051 tegra_clk_cfg_ex( 2049 tegra_clk_cfg_ex(
2052 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); 2050 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2053 2051