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-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c2511
1 files changed, 851 insertions, 1660 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f100e16f..5cd502c27163 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c 2 * arch/arm/mach-tegra/tegra30_clocks.c
3 * 3 *
4 * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
35 35
36#include "clock.h" 36#include "clock.h"
37#include "fuse.h" 37#include "fuse.h"
38#include "tegra_cpu_car.h"
38 39
39#define USE_PLL_LOCK_BITS 0 40#define USE_PLL_LOCK_BITS 0
40 41
@@ -299,6 +300,16 @@
299/* FIXME: recommended safety delay after lock is detected */ 300/* FIXME: recommended safety delay after lock is detected */
300#define PLL_POST_LOCK_DELAY 100 301#define PLL_POST_LOCK_DELAY 100
301 302
303/* Tegra CPU clock and reset control regs */
304#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
305#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
306#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
307#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
308#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
309
310#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
311#define CPU_RESET(cpu) (0x1111ul << (cpu))
312
302/** 313/**
303* Structure defining the fields for USB UTMI clocks Parameters. 314* Structure defining the fields for USB UTMI clocks Parameters.
304*/ 315*/
@@ -365,30 +376,32 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
365static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; 376static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
366 377
367#define clk_writel(value, reg) \ 378#define clk_writel(value, reg) \
368 __raw_writel(value, (u32)reg_clk_base + (reg)) 379 __raw_writel(value, reg_clk_base + (reg))
369#define clk_readl(reg) \ 380#define clk_readl(reg) \
370 __raw_readl((u32)reg_clk_base + (reg)) 381 __raw_readl(reg_clk_base + (reg))
371#define pmc_writel(value, reg) \ 382#define pmc_writel(value, reg) \
372 __raw_writel(value, (u32)reg_pmc_base + (reg)) 383 __raw_writel(value, reg_pmc_base + (reg))
373#define pmc_readl(reg) \ 384#define pmc_readl(reg) \
374 __raw_readl((u32)reg_pmc_base + (reg)) 385 __raw_readl(reg_pmc_base + (reg))
375#define chipid_readl() \ 386#define chipid_readl() \
376 __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) 387 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
377 388
378#define clk_writel_delay(value, reg) \ 389#define clk_writel_delay(value, reg) \
379 do { \ 390 do { \
380 __raw_writel((value), (u32)reg_clk_base + (reg)); \ 391 __raw_writel((value), reg_clk_base + (reg)); \
381 udelay(2); \ 392 udelay(2); \
382 } while (0) 393 } while (0)
383 394
384 395static inline int clk_set_div(struct clk_tegra *c, u32 n)
385static inline int clk_set_div(struct clk *c, u32 n)
386{ 396{
387 return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); 397 struct clk *clk = c->hw.clk;
398
399 return clk_set_rate(clk,
400 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
388} 401}
389 402
390static inline u32 periph_clk_to_reg( 403static inline u32 periph_clk_to_reg(
391 struct clk *c, u32 reg_L, u32 reg_V, int offs) 404 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
392{ 405{
393 u32 reg = c->u.periph.clk_num / 32; 406 u32 reg = c->u.periph.clk_num / 32;
394 BUG_ON(reg >= RST_DEVICES_NUM); 407 BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
470 return divider_u16 - 1; 483 return divider_u16 - 1;
471} 484}
472 485
486static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
487 unsigned long parent_rate)
488{
489 return to_clk_tegra(hw)->fixed_rate;
490}
491
492struct clk_ops tegra30_clk_32k_ops = {
493 .recalc_rate = tegra30_clk_fixed_recalc_rate,
494};
495
473/* clk_m functions */ 496/* clk_m functions */
474static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c) 497static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
498 unsigned long parent_rate)
499{
500 if (!to_clk_tegra(hw)->fixed_rate)
501 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
502 return to_clk_tegra(hw)->fixed_rate;
503}
504
505static void tegra30_clk_m_init(struct clk_hw *hw)
475{ 506{
476 u32 osc_ctrl = clk_readl(OSC_CTRL); 507 u32 osc_ctrl = clk_readl(OSC_CTRL);
477 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; 508 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
478 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 509 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
479 510
480 c->rate = clk_measure_input_freq(); 511 switch (to_clk_tegra(hw)->fixed_rate) {
481 switch (c->rate) {
482 case 12000000: 512 case 12000000:
483 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; 513 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
484 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 514 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@ static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
508 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 538 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
509 break; 539 break;
510 default: 540 default:
511 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); 541 pr_err("%s: Unexpected clock rate %ld", __func__,
542 to_clk_tegra(hw)->fixed_rate);
512 BUG(); 543 BUG();
513 } 544 }
514 clk_writel(auto_clock_control, OSC_CTRL); 545 clk_writel(auto_clock_control, OSC_CTRL);
515 return c->rate;
516} 546}
517 547
518static void tegra30_clk_m_init(struct clk *c) 548struct clk_ops tegra30_clk_m_ops = {
519{ 549 .init = tegra30_clk_m_init,
520 pr_debug("%s on clock %s\n", __func__, c->name); 550 .recalc_rate = tegra30_clk_m_recalc_rate,
521 tegra30_clk_m_autodetect_rate(c); 551};
522}
523 552
524static int tegra30_clk_m_enable(struct clk *c) 553static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
554 unsigned long parent_rate)
525{ 555{
526 pr_debug("%s on clock %s\n", __func__, c->name); 556 struct clk_tegra *c = to_clk_tegra(hw);
527 return 0; 557 u64 rate = parent_rate;
528}
529 558
530static void tegra30_clk_m_disable(struct clk *c) 559 if (c->mul != 0 && c->div != 0) {
531{ 560 rate *= c->mul;
532 pr_debug("%s on clock %s\n", __func__, c->name); 561 rate += c->div - 1; /* round up */
533 WARN(1, "Attempting to disable main SoC clock\n"); 562 do_div(rate, c->div);
534} 563 }
535 564
536static struct clk_ops tegra_clk_m_ops = { 565 return rate;
537 .init = tegra30_clk_m_init, 566}
538 .enable = tegra30_clk_m_enable,
539 .disable = tegra30_clk_m_disable,
540};
541 567
542static struct clk_ops tegra_clk_m_div_ops = { 568struct clk_ops tegra_clk_m_div_ops = {
543 .enable = tegra30_clk_m_enable, 569 .recalc_rate = tegra30_clk_m_div_recalc_rate,
544}; 570};
545 571
546/* PLL reference divider functions */ 572/* PLL reference divider functions */
547static void tegra30_pll_ref_init(struct clk *c) 573static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
574 unsigned long parent_rate)
548{ 575{
576 struct clk_tegra *c = to_clk_tegra(hw);
577 unsigned long rate = parent_rate;
549 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; 578 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
550 pr_debug("%s on clock %s\n", __func__, c->name);
551 579
552 switch (pll_ref_div) { 580 switch (pll_ref_div) {
553 case OSC_CTRL_PLL_REF_DIV_1: 581 case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@ static void tegra30_pll_ref_init(struct clk *c)
564 BUG(); 592 BUG();
565 } 593 }
566 c->mul = 1; 594 c->mul = 1;
567 c->state = ON; 595
596 if (c->mul != 0 && c->div != 0) {
597 rate *= c->mul;
598 rate += c->div - 1; /* round up */
599 do_div(rate, c->div);
600 }
601
602 return rate;
568} 603}
569 604
570static struct clk_ops tegra_pll_ref_ops = { 605struct clk_ops tegra_pll_ref_ops = {
571 .init = tegra30_pll_ref_init, 606 .recalc_rate = tegra30_pll_ref_recalc_rate,
572 .enable = tegra30_clk_m_enable,
573 .disable = tegra30_clk_m_disable,
574}; 607};
575 608
576/* super clock functions */ 609/* super clock functions */
@@ -581,56 +614,50 @@ static struct clk_ops tegra_pll_ref_ops = {
581 * only when its parent is a fixed rate PLL, since we can't change PLL rate 614 * only when its parent is a fixed rate PLL, since we can't change PLL rate
582 * in this case. 615 * in this case.
583 */ 616 */
584static void tegra30_super_clk_init(struct clk *c) 617static void tegra30_super_clk_init(struct clk_hw *hw)
585{ 618{
586 u32 val; 619 struct clk_tegra *c = to_clk_tegra(hw);
587 int source; 620 struct clk_tegra *p =
588 int shift; 621 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
589 const struct clk_mux_sel *sel;
590 val = clk_readl(c->reg + SUPER_CLK_MUX);
591 c->state = ON;
592 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
593 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
594 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
595 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
596 source = (val >> shift) & SUPER_SOURCE_MASK;
597 if (c->flags & DIV_2)
598 source |= val & SUPER_LP_DIV2_BYPASS;
599 for (sel = c->inputs; sel->input != NULL; sel++) {
600 if (sel->value == source)
601 break;
602 }
603 BUG_ON(sel->input == NULL);
604 c->parent = sel->input;
605 622
623 c->state = ON;
606 if (c->flags & DIV_U71) { 624 if (c->flags & DIV_U71) {
607 /* Init safe 7.1 divider value (does not affect PLLX path) */ 625 /* Init safe 7.1 divider value (does not affect PLLX path) */
608 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, 626 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
609 c->reg + SUPER_CLK_DIVIDER); 627 c->reg + SUPER_CLK_DIVIDER);
610 c->mul = 2; 628 c->mul = 2;
611 c->div = 2; 629 c->div = 2;
612 if (!(c->parent->flags & PLLX)) 630 if (!(p->flags & PLLX))
613 c->div += SUPER_CLOCK_DIV_U71_MIN; 631 c->div += SUPER_CLOCK_DIV_U71_MIN;
614 } else 632 } else
615 clk_writel(0, c->reg + SUPER_CLK_DIVIDER); 633 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
616} 634}
617 635
618static int tegra30_super_clk_enable(struct clk *c) 636static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
619{ 637{
620 return 0; 638 struct clk_tegra *c = to_clk_tegra(hw);
621} 639 u32 val;
640 int source;
641 int shift;
622 642
623static void tegra30_super_clk_disable(struct clk *c) 643 val = clk_readl(c->reg + SUPER_CLK_MUX);
624{ 644 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
625 /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and 645 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
626 geared up g-mode super clock - mode switch may request to disable 646 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
627 either of them; accept request with no affect on h/w */ 647 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
648 source = (val >> shift) & SUPER_SOURCE_MASK;
649 if (c->flags & DIV_2)
650 source |= val & SUPER_LP_DIV2_BYPASS;
651
652 return source;
628} 653}
629 654
630static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p) 655static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
631{ 656{
657 struct clk_tegra *c = to_clk_tegra(hw);
658 struct clk_tegra *p =
659 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
632 u32 val; 660 u32 val;
633 const struct clk_mux_sel *sel;
634 int shift; 661 int shift;
635 662
636 val = clk_readl(c->reg + SUPER_CLK_MUX); 663 val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
638 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); 665 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
639 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? 666 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
640 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; 667 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
641 for (sel = c->inputs; sel->input != NULL; sel++) {
642 if (sel->input == p) {
643 /* For LP mode super-clock switch between PLLX direct
644 and divided-by-2 outputs is allowed only when other
645 than PLLX clock source is current parent */
646 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
647 ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
648 if (c->parent->flags & PLLX)
649 return -EINVAL;
650 val ^= SUPER_LP_DIV2_BYPASS;
651 clk_writel_delay(val, c->reg);
652 }
653 val &= ~(SUPER_SOURCE_MASK << shift);
654 val |= (sel->value & SUPER_SOURCE_MASK) << shift;
655
656 /* 7.1 divider for CPU super-clock does not affect
657 PLLX path */
658 if (c->flags & DIV_U71) {
659 u32 div = 0;
660 if (!(p->flags & PLLX)) {
661 div = clk_readl(c->reg +
662 SUPER_CLK_DIVIDER);
663 div &= SUPER_CLOCK_DIV_U71_MASK;
664 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
665 }
666 c->div = div + 2;
667 c->mul = 2;
668 }
669
670 if (c->refcnt)
671 clk_enable(p);
672
673 clk_writel_delay(val, c->reg);
674 668
675 if (c->refcnt && c->parent) 669 /* For LP mode super-clock switch between PLLX direct
676 clk_disable(c->parent); 670 and divided-by-2 outputs is allowed only when other
671 than PLLX clock source is current parent */
672 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
673 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
674 if (p->flags & PLLX)
675 return -EINVAL;
676 val ^= SUPER_LP_DIV2_BYPASS;
677 clk_writel_delay(val, c->reg);
678 }
679 val &= ~(SUPER_SOURCE_MASK << shift);
680 val |= (index & SUPER_SOURCE_MASK) << shift;
677 681
678 clk_reparent(c, p); 682 /* 7.1 divider for CPU super-clock does not affect
679 return 0; 683 PLLX path */
684 if (c->flags & DIV_U71) {
685 u32 div = 0;
686 if (!(p->flags & PLLX)) {
687 div = clk_readl(c->reg +
688 SUPER_CLK_DIVIDER);
689 div &= SUPER_CLOCK_DIV_U71_MASK;
690 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
680 } 691 }
692 c->div = div + 2;
693 c->mul = 2;
681 } 694 }
682 return -EINVAL; 695 clk_writel_delay(val, c->reg);
696
697 return 0;
683} 698}
684 699
685/* 700/*
@@ -691,10 +706,15 @@ static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
691 * rate of this PLL can't be changed, and it has many other children. In 706 * rate of this PLL can't be changed, and it has many other children. In
692 * this case use 7.1 fractional divider to adjust the super clock rate. 707 * this case use 7.1 fractional divider to adjust the super clock rate.
693 */ 708 */
694static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate) 709static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
710 unsigned long parent_rate)
695{ 711{
696 if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { 712 struct clk_tegra *c = to_clk_tegra(hw);
697 int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, 713 struct clk *parent = __clk_get_parent(hw->clk);
714 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
715
716 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
717 int div = clk_div71_get_divider(parent_rate,
698 rate, c->flags, ROUND_DIVIDER_DOWN); 718 rate, c->flags, ROUND_DIVIDER_DOWN);
699 div = max(div, SUPER_CLOCK_DIV_U71_MIN); 719 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
700 720
@@ -704,55 +724,86 @@ static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
704 c->mul = 2; 724 c->mul = 2;
705 return 0; 725 return 0;
706 } 726 }
707 return clk_set_rate(c->parent, rate); 727 return 0;
728}
729
730static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
731 unsigned long parent_rate)
732{
733 struct clk_tegra *c = to_clk_tegra(hw);
734 u64 rate = parent_rate;
735
736 if (c->mul != 0 && c->div != 0) {
737 rate *= c->mul;
738 rate += c->div - 1; /* round up */
739 do_div(rate, c->div);
740 }
741
742 return rate;
708} 743}
709 744
710static struct clk_ops tegra_super_ops = { 745static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
711 .init = tegra30_super_clk_init, 746 unsigned long *prate)
712 .enable = tegra30_super_clk_enable, 747{
713 .disable = tegra30_super_clk_disable, 748 struct clk_tegra *c = to_clk_tegra(hw);
714 .set_parent = tegra30_super_clk_set_parent, 749 struct clk *parent = __clk_get_parent(hw->clk);
715 .set_rate = tegra30_super_clk_set_rate, 750 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
751 int mul = 2;
752 int div;
753
754 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
755 div = clk_div71_get_divider(*prate,
756 rate, c->flags, ROUND_DIVIDER_DOWN);
757 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
758 rate = *prate * mul;
759 rate += div - 1; /* round up */
760 do_div(rate, c->div);
761
762 return rate;
763 }
764 return *prate;
765}
766
767struct clk_ops tegra30_super_ops = {
768 .init = tegra30_super_clk_init,
769 .set_parent = tegra30_super_clk_set_parent,
770 .get_parent = tegra30_super_clk_get_parent,
771 .recalc_rate = tegra30_super_clk_recalc_rate,
772 .round_rate = tegra30_super_clk_round_rate,
773 .set_rate = tegra30_super_clk_set_rate,
716}; 774};
717 775
718static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate) 776static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
777 unsigned long parent_rate)
719{ 778{
720 /* The input value 'rate' is the clock rate of the CPU complex. */ 779 struct clk_tegra *c = to_clk_tegra(hw);
721 c->rate = (rate * c->mul) / c->div; 780 u64 rate = parent_rate;
722 return 0; 781
782 if (c->mul != 0 && c->div != 0) {
783 rate *= c->mul;
784 rate += c->div - 1; /* round up */
785 do_div(rate, c->div);
786 }
787
788 return rate;
723} 789}
724 790
725static struct clk_ops tegra30_twd_ops = { 791struct clk_ops tegra30_twd_ops = {
726 .set_rate = tegra30_twd_clk_set_rate, 792 .recalc_rate = tegra30_twd_clk_recalc_rate,
727}; 793};
728 794
729/* Blink output functions */ 795/* Blink output functions */
730 796static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
731static void tegra30_blink_clk_init(struct clk *c)
732{ 797{
798 struct clk_tegra *c = to_clk_tegra(hw);
733 u32 val; 799 u32 val;
734 800
735 val = pmc_readl(PMC_CTRL); 801 val = pmc_readl(PMC_CTRL);
736 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; 802 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
737 c->mul = 1; 803 return c->state;
738 val = pmc_readl(c->reg);
739
740 if (val & PMC_BLINK_TIMER_ENB) {
741 unsigned int on_off;
742
743 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
744 PMC_BLINK_TIMER_DATA_ON_MASK;
745 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
746 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
747 on_off += val;
748 /* each tick in the blink timer is 4 32KHz clocks */
749 c->div = on_off * 4;
750 } else {
751 c->div = 1;
752 }
753} 804}
754 805
755static int tegra30_blink_clk_enable(struct clk *c) 806static int tegra30_blink_clk_enable(struct clk_hw *hw)
756{ 807{
757 u32 val; 808 u32 val;
758 809
@@ -765,7 +816,7 @@ static int tegra30_blink_clk_enable(struct clk *c)
765 return 0; 816 return 0;
766} 817}
767 818
768static void tegra30_blink_clk_disable(struct clk *c) 819static void tegra30_blink_clk_disable(struct clk_hw *hw)
769{ 820{
770 u32 val; 821 u32 val;
771 822
@@ -776,9 +827,11 @@ static void tegra30_blink_clk_disable(struct clk *c)
776 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); 827 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
777} 828}
778 829
779static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate) 830static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
831 unsigned long parent_rate)
780{ 832{
781 unsigned long parent_rate = clk_get_rate(c->parent); 833 struct clk_tegra *c = to_clk_tegra(hw);
834
782 if (rate >= parent_rate) { 835 if (rate >= parent_rate) {
783 c->div = 1; 836 c->div = 1;
784 pmc_writel(0, c->reg); 837 pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@ static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
801 return 0; 854 return 0;
802} 855}
803 856
804static struct clk_ops tegra_blink_clk_ops = { 857static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
805 .init = &tegra30_blink_clk_init, 858 unsigned long parent_rate)
806 .enable = &tegra30_blink_clk_enable, 859{
807 .disable = &tegra30_blink_clk_disable, 860 struct clk_tegra *c = to_clk_tegra(hw);
808 .set_rate = &tegra30_blink_clk_set_rate, 861 u64 rate = parent_rate;
809}; 862 u32 val;
863 u32 mul;
864 u32 div;
865 u32 on_off;
810 866
811/* PLL Functions */ 867 mul = 1;
812static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, 868 val = pmc_readl(c->reg);
813 u32 lock_bit) 869
870 if (val & PMC_BLINK_TIMER_ENB) {
871 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
872 PMC_BLINK_TIMER_DATA_ON_MASK;
873 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
874 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
875 on_off += val;
876 /* each tick in the blink timer is 4 32KHz clocks */
877 div = on_off * 4;
878 } else {
879 div = 1;
880 }
881
882 if (mul != 0 && div != 0) {
883 rate *= mul;
884 rate += div - 1; /* round up */
885 do_div(rate, div);
886 }
887 return rate;
888}
889
890static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
891 unsigned long *prate)
814{ 892{
815#if USE_PLL_LOCK_BITS 893 int div;
816 int i; 894 int mul;
817 for (i = 0; i < c->u.pll.lock_delay; i++) { 895 long round_rate = *prate;
818 if (clk_readl(lock_reg) & lock_bit) { 896
819 udelay(PLL_POST_LOCK_DELAY); 897 mul = 1;
820 return 0; 898
821 } 899 if (rate >= *prate) {
822 udelay(2); /* timeout = 2 * lock time */ 900 div = 1;
901 } else {
902 div = DIV_ROUND_UP(*prate / 8, rate);
903 div *= 8;
823 } 904 }
824 pr_err("Timed out waiting for lock bit on pll %s", c->name);
825 return -1;
826#endif
827 udelay(c->u.pll.lock_delay);
828 905
829 return 0; 906 round_rate *= mul;
907 round_rate += div - 1;
908 do_div(round_rate, div);
909
910 return round_rate;
830} 911}
831 912
913struct clk_ops tegra30_blink_clk_ops = {
914 .is_enabled = tegra30_blink_clk_is_enabled,
915 .enable = tegra30_blink_clk_enable,
916 .disable = tegra30_blink_clk_disable,
917 .recalc_rate = tegra30_blink_clk_recalc_rate,
918 .round_rate = tegra30_blink_clk_round_rate,
919 .set_rate = tegra30_blink_clk_set_rate,
920};
832 921
833static void tegra30_utmi_param_configure(struct clk *c) 922static void tegra30_utmi_param_configure(struct clk_hw *hw)
834{ 923{
924 unsigned long main_rate =
925 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
835 u32 reg; 926 u32 reg;
836 int i; 927 int i;
837 unsigned long main_rate =
838 clk_get_rate(c->parent->parent);
839 928
840 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 929 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
841 if (main_rate == utmi_parameters[i].osc_frequency) 930 if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@ static void tegra30_utmi_param_configure(struct clk *c)
886 clk_writel(reg, UTMIP_PLL_CFG1); 975 clk_writel(reg, UTMIP_PLL_CFG1);
887} 976}
888 977
889static void tegra30_pll_clk_init(struct clk *c) 978/* PLL Functions */
979static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
980 u32 lock_bit)
981{
982 int ret = 0;
983
984#if USE_PLL_LOCK_BITS
985 int i;
986 for (i = 0; i < c->u.pll.lock_delay; i++) {
987 if (clk_readl(lock_reg) & lock_bit) {
988 udelay(PLL_POST_LOCK_DELAY);
989 return 0;
990 }
991 udelay(2); /* timeout = 2 * lock time */
992 }
993 pr_err("Timed out waiting for lock bit on pll %s",
994 __clk_get_name(hw->clk));
995 ret = -1;
996#else
997 udelay(c->u.pll.lock_delay);
998#endif
999 return ret;
1000}
1001
1002static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
890{ 1003{
1004 struct clk_tegra *c = to_clk_tegra(hw);
891 u32 val = clk_readl(c->reg + PLL_BASE); 1005 u32 val = clk_readl(c->reg + PLL_BASE);
892 1006
893 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; 1007 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1008 return c->state;
1009}
894 1010
895 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { 1011static void tegra30_pll_clk_init(struct clk_hw *hw)
896 const struct clk_pll_freq_table *sel; 1012{
897 unsigned long input_rate = clk_get_rate(c->parent); 1013 struct clk_tegra *c = to_clk_tegra(hw);
898 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
899 if (sel->input_rate == input_rate &&
900 sel->output_rate == c->u.pll.fixed_rate) {
901 c->mul = sel->n;
902 c->div = sel->m * sel->p;
903 return;
904 }
905 }
906 pr_err("Clock %s has unknown fixed frequency\n", c->name);
907 BUG();
908 } else if (val & PLL_BASE_BYPASS) {
909 c->mul = 1;
910 c->div = 1;
911 } else {
912 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
913 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
914 if (c->flags & PLLU)
915 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
916 else
917 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
918 PLL_BASE_DIVP_SHIFT));
919 if (c->flags & PLL_FIXED) {
920 unsigned long rate = clk_get_rate_locked(c);
921 BUG_ON(rate != c->u.pll.fixed_rate);
922 }
923 }
924 1014
925 if (c->flags & PLLU) 1015 if (c->flags & PLLU)
926 tegra30_utmi_param_configure(c); 1016 tegra30_utmi_param_configure(hw);
927} 1017}
928 1018
929static int tegra30_pll_clk_enable(struct clk *c) 1019static int tegra30_pll_clk_enable(struct clk_hw *hw)
930{ 1020{
1021 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val; 1022 u32 val;
932 pr_debug("%s on clock %s\n", __func__, c->name); 1023 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
933 1024
934#if USE_PLL_LOCK_BITS 1025#if USE_PLL_LOCK_BITS
935 val = clk_readl(c->reg + PLL_MISC(c)); 1026 val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@ static int tegra30_pll_clk_enable(struct clk *c)
952 return 0; 1043 return 0;
953} 1044}
954 1045
955static void tegra30_pll_clk_disable(struct clk *c) 1046static void tegra30_pll_clk_disable(struct clk_hw *hw)
956{ 1047{
1048 struct clk_tegra *c = to_clk_tegra(hw);
957 u32 val; 1049 u32 val;
958 pr_debug("%s on clock %s\n", __func__, c->name); 1050 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
959 1051
960 val = clk_readl(c->reg); 1052 val = clk_readl(c->reg);
961 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1053 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@ static void tegra30_pll_clk_disable(struct clk *c)
968 } 1060 }
969} 1061}
970 1062
971static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate) 1063static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1064 unsigned long parent_rate)
972{ 1065{
1066 struct clk_tegra *c = to_clk_tegra(hw);
973 u32 val, p_div, old_base; 1067 u32 val, p_div, old_base;
974 unsigned long input_rate; 1068 unsigned long input_rate;
975 const struct clk_pll_freq_table *sel; 1069 const struct clk_pll_freq_table *sel;
976 struct clk_pll_freq_table cfg; 1070 struct clk_pll_freq_table cfg;
977 1071
978 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
979
980 if (c->flags & PLL_FIXED) { 1072 if (c->flags & PLL_FIXED) {
981 int ret = 0; 1073 int ret = 0;
982 if (rate != c->u.pll.fixed_rate) { 1074 if (rate != c->u.pll.fixed_rate) {
983 pr_err("%s: Can not change %s fixed rate %lu to %lu\n", 1075 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
984 __func__, c->name, c->u.pll.fixed_rate, rate); 1076 __func__, __clk_get_name(hw->clk),
1077 c->u.pll.fixed_rate, rate);
985 ret = -EINVAL; 1078 ret = -EINVAL;
986 } 1079 }
987 return ret; 1080 return ret;
988 } 1081 }
989 1082
990 if (c->flags & PLLM) { 1083 if (c->flags & PLLM) {
991 if (rate != clk_get_rate_locked(c)) { 1084 if (rate != __clk_get_rate(hw->clk)) {
992 pr_err("%s: Can not change memory %s rate in flight\n", 1085 pr_err("%s: Can not change memory %s rate in flight\n",
993 __func__, c->name); 1086 __func__, __clk_get_name(hw->clk));
994 return -EINVAL; 1087 return -EINVAL;
995 } 1088 }
996 return 0;
997 } 1089 }
998 1090
999 p_div = 0; 1091 p_div = 0;
1000 input_rate = clk_get_rate(c->parent); 1092 input_rate = parent_rate;
1001 1093
1002 /* Check if the target rate is tabulated */ 1094 /* Check if the target rate is tabulated */
1003 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1095 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1055 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || 1147 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1056 (cfg.output_rate > c->u.pll.vco_max)) { 1148 (cfg.output_rate > c->u.pll.vco_max)) {
1057 pr_err("%s: Failed to set %s out-of-table rate %lu\n", 1149 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1058 __func__, c->name, rate); 1150 __func__, __clk_get_name(hw->clk), rate);
1059 return -EINVAL; 1151 return -EINVAL;
1060 } 1152 }
1061 p_div <<= PLL_BASE_DIVP_SHIFT; 1153 p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1073 return 0; 1165 return 0;
1074 1166
1075 if (c->state == ON) { 1167 if (c->state == ON) {
1076 tegra30_pll_clk_disable(c); 1168 tegra30_pll_clk_disable(hw);
1077 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); 1169 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1078 } 1170 }
1079 clk_writel(val, c->reg + PLL_BASE); 1171 clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@ static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
1095 } 1187 }
1096 1188
1097 if (c->state == ON) 1189 if (c->state == ON)
1098 tegra30_pll_clk_enable(c); 1190 tegra30_pll_clk_enable(hw);
1191
1192 c->u.pll.fixed_rate = rate;
1099 1193
1100 return 0; 1194 return 0;
1101} 1195}
1102 1196
1103static struct clk_ops tegra_pll_ops = { 1197static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1104 .init = tegra30_pll_clk_init, 1198 unsigned long *prate)
1105 .enable = tegra30_pll_clk_enable, 1199{
1106 .disable = tegra30_pll_clk_disable, 1200 struct clk_tegra *c = to_clk_tegra(hw);
1107 .set_rate = tegra30_pll_clk_set_rate, 1201 unsigned long input_rate = *prate;
1202 unsigned long output_rate = *prate;
1203 const struct clk_pll_freq_table *sel;
1204 struct clk_pll_freq_table cfg;
1205 int mul;
1206 int div;
1207 u32 p_div;
1208 u32 val;
1209
1210 if (c->flags & PLL_FIXED)
1211 return c->u.pll.fixed_rate;
1212
1213 if (c->flags & PLLM)
1214 return __clk_get_rate(hw->clk);
1215
1216 p_div = 0;
1217 /* Check if the target rate is tabulated */
1218 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1219 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1220 if (c->flags & PLLU) {
1221 BUG_ON(sel->p < 1 || sel->p > 2);
1222 if (sel->p == 1)
1223 p_div = PLLU_BASE_POST_DIV;
1224 } else {
1225 BUG_ON(sel->p < 1);
1226 for (val = sel->p; val > 1; val >>= 1)
1227 p_div++;
1228 p_div <<= PLL_BASE_DIVP_SHIFT;
1229 }
1230 break;
1231 }
1232 }
1233
1234 if (sel->input_rate == 0) {
1235 unsigned long cfreq;
1236 BUG_ON(c->flags & PLLU);
1237 sel = &cfg;
1238
1239 switch (input_rate) {
1240 case 12000000:
1241 case 26000000:
1242 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1243 break;
1244 case 13000000:
1245 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1246 break;
1247 case 16800000:
1248 case 19200000:
1249 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1250 break;
1251 default:
1252 pr_err("%s: Unexpected reference rate %lu\n",
1253 __func__, input_rate);
1254 BUG();
1255 }
1256
1257 /* Raise VCO to guarantee 0.5% accuracy */
1258 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1259 cfg.output_rate <<= 1)
1260 p_div++;
1261
1262 cfg.p = 0x1 << p_div;
1263 cfg.m = input_rate / cfreq;
1264 cfg.n = cfg.output_rate / cfreq;
1265 }
1266
1267 mul = sel->n;
1268 div = sel->m * sel->p;
1269
1270 output_rate *= mul;
1271 output_rate += div - 1; /* round up */
1272 do_div(output_rate, div);
1273
1274 return output_rate;
1275}
1276
1277static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1278 unsigned long parent_rate)
1279{
1280 struct clk_tegra *c = to_clk_tegra(hw);
1281 u64 rate = parent_rate;
1282 u32 val = clk_readl(c->reg + PLL_BASE);
1283
1284 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1285 const struct clk_pll_freq_table *sel;
1286 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1287 if (sel->input_rate == parent_rate &&
1288 sel->output_rate == c->u.pll.fixed_rate) {
1289 c->mul = sel->n;
1290 c->div = sel->m * sel->p;
1291 break;
1292 }
1293 }
1294 pr_err("Clock %s has unknown fixed frequency\n",
1295 __clk_get_name(hw->clk));
1296 BUG();
1297 } else if (val & PLL_BASE_BYPASS) {
1298 c->mul = 1;
1299 c->div = 1;
1300 } else {
1301 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1302 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1303 if (c->flags & PLLU)
1304 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1305 else
1306 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1307 PLL_BASE_DIVP_SHIFT));
1308 }
1309
1310 if (c->mul != 0 && c->div != 0) {
1311 rate *= c->mul;
1312 rate += c->div - 1; /* round up */
1313 do_div(rate, c->div);
1314 }
1315
1316 return rate;
1317}
1318
1319struct clk_ops tegra30_pll_ops = {
1320 .is_enabled = tegra30_pll_clk_is_enabled,
1321 .init = tegra30_pll_clk_init,
1322 .enable = tegra30_pll_clk_enable,
1323 .disable = tegra30_pll_clk_disable,
1324 .recalc_rate = tegra30_pll_recalc_rate,
1325 .round_rate = tegra30_pll_round_rate,
1326 .set_rate = tegra30_pll_clk_set_rate,
1108}; 1327};
1109 1328
1110static int 1329int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1111tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1330 enum tegra_clk_ex_param p, u32 setting)
1112{ 1331{
1332 struct clk_tegra *c = to_clk_tegra(hw);
1113 u32 val, mask, reg; 1333 u32 val, mask, reg;
1114 1334
1115 switch (p) { 1335 switch (p) {
@@ -1141,41 +1361,27 @@ tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1141 return 0; 1361 return 0;
1142} 1362}
1143 1363
1144static struct clk_ops tegra_plld_ops = { 1364static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1145 .init = tegra30_pll_clk_init,
1146 .enable = tegra30_pll_clk_enable,
1147 .disable = tegra30_pll_clk_disable,
1148 .set_rate = tegra30_pll_clk_set_rate,
1149 .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
1150};
1151
1152static void tegra30_plle_clk_init(struct clk *c)
1153{ 1365{
1366 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val; 1367 u32 val;
1155 1368
1156 val = clk_readl(PLLE_AUX);
1157 c->parent = (val & PLLE_AUX_PLLP_SEL) ?
1158 tegra_get_clock_by_name("pll_p") :
1159 tegra_get_clock_by_name("pll_ref");
1160
1161 val = clk_readl(c->reg + PLL_BASE); 1369 val = clk_readl(c->reg + PLL_BASE);
1162 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; 1370 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1163 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; 1371 return c->state;
1164 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1165 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1166} 1372}
1167 1373
1168static void tegra30_plle_clk_disable(struct clk *c) 1374static void tegra30_plle_clk_disable(struct clk_hw *hw)
1169{ 1375{
1376 struct clk_tegra *c = to_clk_tegra(hw);
1170 u32 val; 1377 u32 val;
1171 pr_debug("%s on clock %s\n", __func__, c->name);
1172 1378
1173 val = clk_readl(c->reg + PLL_BASE); 1379 val = clk_readl(c->reg + PLL_BASE);
1174 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); 1380 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1175 clk_writel(val, c->reg + PLL_BASE); 1381 clk_writel(val, c->reg + PLL_BASE);
1176} 1382}
1177 1383
1178static void tegra30_plle_training(struct clk *c) 1384static void tegra30_plle_training(struct clk_tegra *c)
1179{ 1385{
1180 u32 val; 1386 u32 val;
1181 1387
@@ -1198,12 +1404,15 @@ static void tegra30_plle_training(struct clk *c)
1198 } while (!(val & PLLE_MISC_READY)); 1404 } while (!(val & PLLE_MISC_READY));
1199} 1405}
1200 1406
1201static int tegra30_plle_configure(struct clk *c, bool force_training) 1407static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1202{ 1408{
1203 u32 val; 1409 struct clk_tegra *c = to_clk_tegra(hw);
1410 struct clk *parent = __clk_get_parent(hw->clk);
1204 const struct clk_pll_freq_table *sel; 1411 const struct clk_pll_freq_table *sel;
1412 u32 val;
1413
1205 unsigned long rate = c->u.pll.fixed_rate; 1414 unsigned long rate = c->u.pll.fixed_rate;
1206 unsigned long input_rate = clk_get_rate(c->parent); 1415 unsigned long input_rate = __clk_get_rate(parent);
1207 1416
1208 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { 1417 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1209 if (sel->input_rate == input_rate && sel->output_rate == rate) 1418 if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1214 return -ENOSYS; 1423 return -ENOSYS;
1215 1424
1216 /* disable PLLE, clear setup fiels */ 1425 /* disable PLLE, clear setup fiels */
1217 tegra30_plle_clk_disable(c); 1426 tegra30_plle_clk_disable(hw);
1218 1427
1219 val = clk_readl(c->reg + PLL_MISC(c)); 1428 val = clk_readl(c->reg + PLL_MISC(c));
1220 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); 1429 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@ static int tegra30_plle_configure(struct clk *c, bool force_training)
1252 return 0; 1461 return 0;
1253} 1462}
1254 1463
1255static int tegra30_plle_clk_enable(struct clk *c) 1464static int tegra30_plle_clk_enable(struct clk_hw *hw)
1465{
1466 struct clk_tegra *c = to_clk_tegra(hw);
1467
1468 return tegra30_plle_configure(hw, !c->set);
1469}
1470
1471static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1472 unsigned long parent_rate)
1256{ 1473{
1257 pr_debug("%s on clock %s\n", __func__, c->name); 1474 struct clk_tegra *c = to_clk_tegra(hw);
1258 return tegra30_plle_configure(c, !c->set); 1475 unsigned long rate = parent_rate;
1476 u32 val;
1477
1478 val = clk_readl(c->reg + PLL_BASE);
1479 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1480 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1481 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1482
1483 if (c->mul != 0 && c->div != 0) {
1484 rate *= c->mul;
1485 rate += c->div - 1; /* round up */
1486 do_div(rate, c->div);
1487 }
1488 return rate;
1259} 1489}
1260 1490
1261static struct clk_ops tegra_plle_ops = { 1491struct clk_ops tegra30_plle_ops = {
1262 .init = tegra30_plle_clk_init, 1492 .is_enabled = tegra30_plle_clk_is_enabled,
1263 .enable = tegra30_plle_clk_enable, 1493 .enable = tegra30_plle_clk_enable,
1264 .disable = tegra30_plle_clk_disable, 1494 .disable = tegra30_plle_clk_disable,
1495 .recalc_rate = tegra30_plle_clk_recalc_rate,
1265}; 1496};
1266 1497
1267/* Clock divider ops */ 1498/* Clock divider ops */
1268static void tegra30_pll_div_clk_init(struct clk *c) 1499static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1269{ 1500{
1501 struct clk_tegra *c = to_clk_tegra(hw);
1502
1270 if (c->flags & DIV_U71) { 1503 if (c->flags & DIV_U71) {
1271 u32 divu71;
1272 u32 val = clk_readl(c->reg); 1504 u32 val = clk_readl(c->reg);
1273 val >>= c->reg_shift; 1505 val >>= c->reg_shift;
1274 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; 1506 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1275 if (!(val & PLL_OUT_RESET_DISABLE)) 1507 if (!(val & PLL_OUT_RESET_DISABLE))
1276 c->state = OFF; 1508 c->state = OFF;
1277
1278 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1279 c->div = (divu71 + 2);
1280 c->mul = 2;
1281 } else if (c->flags & DIV_2) {
1282 c->state = ON;
1283 if (c->flags & (PLLD | PLLX)) {
1284 c->div = 2;
1285 c->mul = 1;
1286 } else
1287 BUG();
1288 } else { 1509 } else {
1289 c->state = ON; 1510 c->state = ON;
1290 c->div = 1;
1291 c->mul = 1;
1292 } 1511 }
1512 return c->state;
1293} 1513}
1294 1514
1295static int tegra30_pll_div_clk_enable(struct clk *c) 1515static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1296{ 1516{
1517 struct clk_tegra *c = to_clk_tegra(hw);
1297 u32 val; 1518 u32 val;
1298 u32 new_val; 1519 u32 new_val;
1299 1520
1300 pr_debug("%s: %s\n", __func__, c->name); 1521 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1301 if (c->flags & DIV_U71) { 1522 if (c->flags & DIV_U71) {
1302 val = clk_readl(c->reg); 1523 val = clk_readl(c->reg);
1303 new_val = val >> c->reg_shift; 1524 new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@ static int tegra30_pll_div_clk_enable(struct clk *c)
1315 return -EINVAL; 1536 return -EINVAL;
1316} 1537}
1317 1538
1318static void tegra30_pll_div_clk_disable(struct clk *c) 1539static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1319{ 1540{
1541 struct clk_tegra *c = to_clk_tegra(hw);
1320 u32 val; 1542 u32 val;
1321 u32 new_val; 1543 u32 new_val;
1322 1544
1323 pr_debug("%s: %s\n", __func__, c->name); 1545 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1324 if (c->flags & DIV_U71) { 1546 if (c->flags & DIV_U71) {
1325 val = clk_readl(c->reg); 1547 val = clk_readl(c->reg);
1326 new_val = val >> c->reg_shift; 1548 new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@ static void tegra30_pll_div_clk_disable(struct clk *c)
1334 } 1556 }
1335} 1557}
1336 1558
1337static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate) 1559static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1560 unsigned long parent_rate)
1338{ 1561{
1562 struct clk_tegra *c = to_clk_tegra(hw);
1339 u32 val; 1563 u32 val;
1340 u32 new_val; 1564 u32 new_val;
1341 int divider_u71; 1565 int divider_u71;
1342 unsigned long parent_rate = clk_get_rate(c->parent);
1343 1566
1344 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1345 if (c->flags & DIV_U71) { 1567 if (c->flags & DIV_U71) {
1346 divider_u71 = clk_div71_get_divider( 1568 divider_u71 = clk_div71_get_divider(
1347 parent_rate, rate, c->flags, ROUND_DIVIDER_UP); 1569 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@ static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
1359 clk_writel_delay(val, c->reg); 1581 clk_writel_delay(val, c->reg);
1360 c->div = divider_u71 + 2; 1582 c->div = divider_u71 + 2;
1361 c->mul = 2; 1583 c->mul = 2;
1584 c->fixed_rate = rate;
1362 return 0; 1585 return 0;
1363 } 1586 }
1364 } else if (c->flags & DIV_2) 1587 } else if (c->flags & DIV_2) {
1365 return clk_set_rate(c->parent, rate * 2); 1588 c->fixed_rate = rate;
1589 return 0;
1590 }
1366 1591
1367 return -EINVAL; 1592 return -EINVAL;
1368} 1593}
1369 1594
1370static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate) 1595static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1596 unsigned long parent_rate)
1597{
1598 struct clk_tegra *c = to_clk_tegra(hw);
1599 u64 rate = parent_rate;
1600
1601 if (c->flags & DIV_U71) {
1602 u32 divu71;
1603 u32 val = clk_readl(c->reg);
1604 val >>= c->reg_shift;
1605
1606 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1607 c->div = (divu71 + 2);
1608 c->mul = 2;
1609 } else if (c->flags & DIV_2) {
1610 if (c->flags & (PLLD | PLLX)) {
1611 c->div = 2;
1612 c->mul = 1;
1613 } else
1614 BUG();
1615 } else {
1616 c->div = 1;
1617 c->mul = 1;
1618 }
1619 if (c->mul != 0 && c->div != 0) {
1620 rate *= c->mul;
1621 rate += c->div - 1; /* round up */
1622 do_div(rate, c->div);
1623 }
1624
1625 return rate;
1626}
1627
1628static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1629 unsigned long rate, unsigned long *prate)
1371{ 1630{
1631 struct clk_tegra *c = to_clk_tegra(hw);
1632 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1372 int divider; 1633 int divider;
1373 unsigned long parent_rate = clk_get_rate(c->parent); 1634
1374 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1635 if (prate)
1636 parent_rate = *prate;
1375 1637
1376 if (c->flags & DIV_U71) { 1638 if (c->flags & DIV_U71) {
1377 divider = clk_div71_get_divider( 1639 divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@ static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
1379 if (divider < 0) 1641 if (divider < 0)
1380 return divider; 1642 return divider;
1381 return DIV_ROUND_UP(parent_rate * 2, divider + 2); 1643 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1382 } else if (c->flags & DIV_2) 1644 } else if (c->flags & DIV_2) {
1383 /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ 1645 *prate = rate * 2;
1384 return rate; 1646 return rate;
1647 }
1385 1648
1386 return -EINVAL; 1649 return -EINVAL;
1387} 1650}
1388 1651
1389static struct clk_ops tegra_pll_div_ops = { 1652struct clk_ops tegra30_pll_div_ops = {
1390 .init = tegra30_pll_div_clk_init, 1653 .is_enabled = tegra30_pll_div_clk_is_enabled,
1391 .enable = tegra30_pll_div_clk_enable, 1654 .enable = tegra30_pll_div_clk_enable,
1392 .disable = tegra30_pll_div_clk_disable, 1655 .disable = tegra30_pll_div_clk_disable,
1393 .set_rate = tegra30_pll_div_clk_set_rate, 1656 .set_rate = tegra30_pll_div_clk_set_rate,
1394 .round_rate = tegra30_pll_div_clk_round_rate, 1657 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1658 .round_rate = tegra30_pll_div_clk_round_rate,
1395}; 1659};
1396 1660
1397/* Periph clk ops */ 1661/* Periph clk ops */
1398static inline u32 periph_clk_source_mask(struct clk *c) 1662static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1399{ 1663{
1400 if (c->flags & MUX8) 1664 if (c->flags & MUX8)
1401 return 7 << 29; 1665 return 7 << 29;
@@ -1409,7 +1673,7 @@ static inline u32 periph_clk_source_mask(struct clk *c)
1409 return 3 << 30; 1673 return 3 << 30;
1410} 1674}
1411 1675
1412static inline u32 periph_clk_source_shift(struct clk *c) 1676static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1413{ 1677{
1414 if (c->flags & MUX8) 1678 if (c->flags & MUX8)
1415 return 29; 1679 return 29;
@@ -1423,47 +1687,9 @@ static inline u32 periph_clk_source_shift(struct clk *c)
1423 return 30; 1687 return 30;
1424} 1688}
1425 1689
1426static void tegra30_periph_clk_init(struct clk *c) 1690static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1427{ 1691{
1428 u32 val = clk_readl(c->reg); 1692 struct clk_tegra *c = to_clk_tegra(hw);
1429 const struct clk_mux_sel *mux = 0;
1430 const struct clk_mux_sel *sel;
1431 if (c->flags & MUX) {
1432 for (sel = c->inputs; sel->input != NULL; sel++) {
1433 if (((val & periph_clk_source_mask(c)) >>
1434 periph_clk_source_shift(c)) == sel->value)
1435 mux = sel;
1436 }
1437 BUG_ON(!mux);
1438
1439 c->parent = mux->input;
1440 } else {
1441 c->parent = c->inputs[0].input;
1442 }
1443
1444 if (c->flags & DIV_U71) {
1445 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1446 if ((c->flags & DIV_U71_UART) &&
1447 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1448 divu71 = 0;
1449 }
1450 if (c->flags & DIV_U71_IDLE) {
1451 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1452 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1453 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1454 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1455 clk_writel(val, c->reg);
1456 }
1457 c->div = divu71 + 2;
1458 c->mul = 2;
1459 } else if (c->flags & DIV_U16) {
1460 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1461 c->div = divu16 + 1;
1462 c->mul = 1;
1463 } else {
1464 c->div = 1;
1465 c->mul = 1;
1466 }
1467 1693
1468 c->state = ON; 1694 c->state = ON;
1469 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 1695 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@ static void tegra30_periph_clk_init(struct clk *c)
1471 if (!(c->flags & PERIPH_NO_RESET)) 1697 if (!(c->flags & PERIPH_NO_RESET))
1472 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) 1698 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1473 c->state = OFF; 1699 c->state = OFF;
1700 return c->state;
1474} 1701}
1475 1702
1476static int tegra30_periph_clk_enable(struct clk *c) 1703static int tegra30_periph_clk_enable(struct clk_hw *hw)
1477{ 1704{
1478 pr_debug("%s on clock %s\n", __func__, c->name); 1705 struct clk_tegra *c = to_clk_tegra(hw);
1479 1706
1480 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; 1707 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1481 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) 1708 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@ static int tegra30_periph_clk_enable(struct clk *c)
1494 return 0; 1721 return 0;
1495} 1722}
1496 1723
1497static void tegra30_periph_clk_disable(struct clk *c) 1724static void tegra30_periph_clk_disable(struct clk_hw *hw)
1498{ 1725{
1726 struct clk_tegra *c = to_clk_tegra(hw);
1499 unsigned long val; 1727 unsigned long val;
1500 pr_debug("%s on clock %s\n", __func__, c->name);
1501 1728
1502 if (c->refcnt) 1729 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1503 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; 1730
1731 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1732 return;
1504 1733
1505 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { 1734 /* If peripheral is in the APB bus then read the APB bus to
1506 /* If peripheral is in the APB bus then read the APB bus to 1735 * flush the write operation in apb bus. This will avoid the
1507 * flush the write operation in apb bus. This will avoid the 1736 * peripheral access after disabling clock*/
1508 * peripheral access after disabling clock*/ 1737 if (c->flags & PERIPH_ON_APB)
1509 if (c->flags & PERIPH_ON_APB) 1738 val = chipid_readl();
1510 val = chipid_readl();
1511 1739
1512 clk_writel_delay( 1740 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1513 PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1514 }
1515} 1741}
1516 1742
1517static void tegra30_periph_clk_reset(struct clk *c, bool assert) 1743void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1518{ 1744{
1745 struct clk_tegra *c = to_clk_tegra(hw);
1519 unsigned long val; 1746 unsigned long val;
1520 pr_debug("%s %s on clock %s\n", __func__,
1521 assert ? "assert" : "deassert", c->name);
1522 1747
1523 if (!(c->flags & PERIPH_NO_RESET)) { 1748 if (!(c->flags & PERIPH_NO_RESET)) {
1524 if (assert) { 1749 if (assert) {
@@ -1537,42 +1762,40 @@ static void tegra30_periph_clk_reset(struct clk *c, bool assert)
1537 } 1762 }
1538} 1763}
1539 1764
1540static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p) 1765static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1541{ 1766{
1767 struct clk_tegra *c = to_clk_tegra(hw);
1542 u32 val; 1768 u32 val;
1543 const struct clk_mux_sel *sel;
1544 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1545 1769
1546 if (!(c->flags & MUX)) 1770 if (!(c->flags & MUX))
1547 return (p == c->parent) ? 0 : (-EINVAL); 1771 return (index == 0) ? 0 : (-EINVAL);
1548
1549 for (sel = c->inputs; sel->input != NULL; sel++) {
1550 if (sel->input == p) {
1551 val = clk_readl(c->reg);
1552 val &= ~periph_clk_source_mask(c);
1553 val |= (sel->value << periph_clk_source_shift(c));
1554
1555 if (c->refcnt)
1556 clk_enable(p);
1557 1772
1558 clk_writel_delay(val, c->reg); 1773 val = clk_readl(c->reg);
1774 val &= ~periph_clk_source_mask(c);
1775 val |= (index << periph_clk_source_shift(c));
1776 clk_writel_delay(val, c->reg);
1777 return 0;
1778}
1559 1779
1560 if (c->refcnt && c->parent) 1780static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1561 clk_disable(c->parent); 1781{
1782 struct clk_tegra *c = to_clk_tegra(hw);
1783 u32 val = clk_readl(c->reg);
1784 int source = (val & periph_clk_source_mask(c)) >>
1785 periph_clk_source_shift(c);
1562 1786
1563 clk_reparent(c, p); 1787 if (!(c->flags & MUX))
1564 return 0; 1788 return 0;
1565 }
1566 }
1567 1789
1568 return -EINVAL; 1790 return source;
1569} 1791}
1570 1792
1571static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate) 1793static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1794 unsigned long parent_rate)
1572{ 1795{
1796 struct clk_tegra *c = to_clk_tegra(hw);
1573 u32 val; 1797 u32 val;
1574 int divider; 1798 int divider;
1575 unsigned long parent_rate = clk_get_rate(c->parent);
1576 1799
1577 if (c->flags & DIV_U71) { 1800 if (c->flags & DIV_U71) {
1578 divider = clk_div71_get_divider( 1801 divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@ static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
1611 return -EINVAL; 1834 return -EINVAL;
1612} 1835}
1613 1836
1614static long tegra30_periph_clk_round_rate(struct clk *c, 1837static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1615 unsigned long rate) 1838 unsigned long *prate)
1616{ 1839{
1840 struct clk_tegra *c = to_clk_tegra(hw);
1841 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1617 int divider; 1842 int divider;
1618 unsigned long parent_rate = clk_get_rate(c->parent); 1843
1619 pr_debug("%s: %s %lu\n", __func__, c->name, rate); 1844 if (prate)
1845 parent_rate = *prate;
1620 1846
1621 if (c->flags & DIV_U71) { 1847 if (c->flags & DIV_U71) {
1622 divider = clk_div71_get_divider( 1848 divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@ static long tegra30_periph_clk_round_rate(struct clk *c,
1634 return -EINVAL; 1860 return -EINVAL;
1635} 1861}
1636 1862
1637static struct clk_ops tegra_periph_clk_ops = { 1863static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1638 .init = &tegra30_periph_clk_init, 1864 unsigned long parent_rate)
1865{
1866 struct clk_tegra *c = to_clk_tegra(hw);
1867 u64 rate = parent_rate;
1868 u32 val = clk_readl(c->reg);
1869
1870 if (c->flags & DIV_U71) {
1871 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1872 if ((c->flags & DIV_U71_UART) &&
1873 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
1874 divu71 = 0;
1875 }
1876 if (c->flags & DIV_U71_IDLE) {
1877 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
1878 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1879 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
1880 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
1881 clk_writel(val, c->reg);
1882 }
1883 c->div = divu71 + 2;
1884 c->mul = 2;
1885 } else if (c->flags & DIV_U16) {
1886 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1887 c->div = divu16 + 1;
1888 c->mul = 1;
1889 } else {
1890 c->div = 1;
1891 c->mul = 1;
1892 }
1893
1894 if (c->mul != 0 && c->div != 0) {
1895 rate *= c->mul;
1896 rate += c->div - 1; /* round up */
1897 do_div(rate, c->div);
1898 }
1899 return rate;
1900}
1901
1902struct clk_ops tegra30_periph_clk_ops = {
1903 .is_enabled = tegra30_periph_clk_is_enabled,
1904 .enable = tegra30_periph_clk_enable,
1905 .disable = tegra30_periph_clk_disable,
1906 .set_parent = tegra30_periph_clk_set_parent,
1907 .get_parent = tegra30_periph_clk_get_parent,
1908 .set_rate = tegra30_periph_clk_set_rate,
1909 .round_rate = tegra30_periph_clk_round_rate,
1910 .recalc_rate = tegra30_periph_clk_recalc_rate,
1911};
1912
1913static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
1914{
1915 struct clk *d = clk_get_sys(NULL, "pll_d");
1916 /* The DSIB parent selection bit is in PLLD base
1917 register - can not do direct r-m-w, must be
1918 protected by PLLD lock */
1919 tegra_clk_cfg_ex(
1920 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
1921
1922 return 0;
1923}
1924
1925struct clk_ops tegra30_dsib_clk_ops = {
1926 .is_enabled = tegra30_periph_clk_is_enabled,
1639 .enable = &tegra30_periph_clk_enable, 1927 .enable = &tegra30_periph_clk_enable,
1640 .disable = &tegra30_periph_clk_disable, 1928 .disable = &tegra30_periph_clk_disable,
1641 .set_parent = &tegra30_periph_clk_set_parent, 1929 .set_parent = &tegra30_dsib_clk_set_parent,
1930 .get_parent = &tegra30_periph_clk_get_parent,
1642 .set_rate = &tegra30_periph_clk_set_rate, 1931 .set_rate = &tegra30_periph_clk_set_rate,
1643 .round_rate = &tegra30_periph_clk_round_rate, 1932 .round_rate = &tegra30_periph_clk_round_rate,
1644 .reset = &tegra30_periph_clk_reset, 1933 .recalc_rate = &tegra30_periph_clk_recalc_rate,
1645}; 1934};
1646 1935
1647
1648/* Periph extended clock configuration ops */ 1936/* Periph extended clock configuration ops */
1649static int 1937int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
1650tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) 1938 enum tegra_clk_ex_param p, u32 setting)
1651{ 1939{
1940 struct clk_tegra *c = to_clk_tegra(hw);
1941
1652 if (p == TEGRA_CLK_VI_INP_SEL) { 1942 if (p == TEGRA_CLK_VI_INP_SEL) {
1653 u32 val = clk_readl(c->reg); 1943 u32 val = clk_readl(c->reg);
1654 val &= ~PERIPH_CLK_VI_SEL_EX_MASK; 1944 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@ tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1660 return -EINVAL; 1950 return -EINVAL;
1661} 1951}
1662 1952
1663static struct clk_ops tegra_vi_clk_ops = { 1953int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
1664 .init = &tegra30_periph_clk_init, 1954 enum tegra_clk_ex_param p, u32 setting)
1665 .enable = &tegra30_periph_clk_enable,
1666 .disable = &tegra30_periph_clk_disable,
1667 .set_parent = &tegra30_periph_clk_set_parent,
1668 .set_rate = &tegra30_periph_clk_set_rate,
1669 .round_rate = &tegra30_periph_clk_round_rate,
1670 .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
1671 .reset = &tegra30_periph_clk_reset,
1672};
1673
1674static int
1675tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1676{ 1955{
1956 struct clk_tegra *c = to_clk_tegra(hw);
1957
1677 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { 1958 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
1678 u32 val = clk_readl(c->reg); 1959 u32 val = clk_readl(c->reg);
1679 if (setting) 1960 if (setting)
@@ -1686,21 +1967,11 @@ tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1686 return -EINVAL; 1967 return -EINVAL;
1687} 1968}
1688 1969
1689static struct clk_ops tegra_nand_clk_ops = { 1970int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
1690 .init = &tegra30_periph_clk_init, 1971 enum tegra_clk_ex_param p, u32 setting)
1691 .enable = &tegra30_periph_clk_enable,
1692 .disable = &tegra30_periph_clk_disable,
1693 .set_parent = &tegra30_periph_clk_set_parent,
1694 .set_rate = &tegra30_periph_clk_set_rate,
1695 .round_rate = &tegra30_periph_clk_round_rate,
1696 .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
1697 .reset = &tegra30_periph_clk_reset,
1698};
1699
1700
1701static int
1702tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1703{ 1972{
1973 struct clk_tegra *c = to_clk_tegra(hw);
1974
1704 if (p == TEGRA_CLK_DTV_INVERT) { 1975 if (p == TEGRA_CLK_DTV_INVERT) {
1705 u32 val = clk_readl(c->reg); 1976 u32 val = clk_readl(c->reg);
1706 if (setting) 1977 if (setting)
@@ -1713,91 +1984,27 @@ tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
1713 return -EINVAL; 1984 return -EINVAL;
1714} 1985}
1715 1986
1716static struct clk_ops tegra_dtv_clk_ops = {
1717 .init = &tegra30_periph_clk_init,
1718 .enable = &tegra30_periph_clk_enable,
1719 .disable = &tegra30_periph_clk_disable,
1720 .set_parent = &tegra30_periph_clk_set_parent,
1721 .set_rate = &tegra30_periph_clk_set_rate,
1722 .round_rate = &tegra30_periph_clk_round_rate,
1723 .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
1724 .reset = &tegra30_periph_clk_reset,
1725};
1726
1727static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
1728{
1729 const struct clk_mux_sel *sel;
1730 struct clk *d = tegra_get_clock_by_name("pll_d");
1731
1732 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
1733
1734 for (sel = c->inputs; sel->input != NULL; sel++) {
1735 if (sel->input == p) {
1736 if (c->refcnt)
1737 clk_enable(p);
1738
1739 /* The DSIB parent selection bit is in PLLD base
1740 register - can not do direct r-m-w, must be
1741 protected by PLLD lock */
1742 tegra_clk_cfg_ex(
1743 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
1744
1745 if (c->refcnt && c->parent)
1746 clk_disable(c->parent);
1747
1748 clk_reparent(c, p);
1749 return 0;
1750 }
1751 }
1752
1753 return -EINVAL;
1754}
1755
1756static struct clk_ops tegra_dsib_clk_ops = {
1757 .init = &tegra30_periph_clk_init,
1758 .enable = &tegra30_periph_clk_enable,
1759 .disable = &tegra30_periph_clk_disable,
1760 .set_parent = &tegra30_dsib_clk_set_parent,
1761 .set_rate = &tegra30_periph_clk_set_rate,
1762 .round_rate = &tegra30_periph_clk_round_rate,
1763 .reset = &tegra30_periph_clk_reset,
1764};
1765
1766/* pciex clock support only reset function */
1767static struct clk_ops tegra_pciex_clk_ops = {
1768 .reset = tegra30_periph_clk_reset,
1769};
1770
1771/* Output clock ops */ 1987/* Output clock ops */
1772 1988
1773static DEFINE_SPINLOCK(clk_out_lock); 1989static DEFINE_SPINLOCK(clk_out_lock);
1774 1990
1775static void tegra30_clk_out_init(struct clk *c) 1991static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
1776{ 1992{
1777 const struct clk_mux_sel *mux = 0; 1993 struct clk_tegra *c = to_clk_tegra(hw);
1778 const struct clk_mux_sel *sel;
1779 u32 val = pmc_readl(c->reg); 1994 u32 val = pmc_readl(c->reg);
1780 1995
1781 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; 1996 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
1782 c->mul = 1; 1997 c->mul = 1;
1783 c->div = 1; 1998 c->div = 1;
1784 1999 return c->state;
1785 for (sel = c->inputs; sel->input != NULL; sel++) {
1786 if (((val & periph_clk_source_mask(c)) >>
1787 periph_clk_source_shift(c)) == sel->value)
1788 mux = sel;
1789 }
1790 BUG_ON(!mux);
1791 c->parent = mux->input;
1792} 2000}
1793 2001
1794static int tegra30_clk_out_enable(struct clk *c) 2002static int tegra30_clk_out_enable(struct clk_hw *hw)
1795{ 2003{
2004 struct clk_tegra *c = to_clk_tegra(hw);
1796 u32 val; 2005 u32 val;
1797 unsigned long flags; 2006 unsigned long flags;
1798 2007
1799 pr_debug("%s on clock %s\n", __func__, c->name);
1800
1801 spin_lock_irqsave(&clk_out_lock, flags); 2008 spin_lock_irqsave(&clk_out_lock, flags);
1802 val = pmc_readl(c->reg); 2009 val = pmc_readl(c->reg);
1803 val |= (0x1 << c->u.periph.clk_num); 2010 val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@ static int tegra30_clk_out_enable(struct clk *c)
1807 return 0; 2014 return 0;
1808} 2015}
1809 2016
1810static void tegra30_clk_out_disable(struct clk *c) 2017static void tegra30_clk_out_disable(struct clk_hw *hw)
1811{ 2018{
2019 struct clk_tegra *c = to_clk_tegra(hw);
1812 u32 val; 2020 u32 val;
1813 unsigned long flags; 2021 unsigned long flags;
1814 2022
1815 pr_debug("%s on clock %s\n", __func__, c->name);
1816
1817 spin_lock_irqsave(&clk_out_lock, flags); 2023 spin_lock_irqsave(&clk_out_lock, flags);
1818 val = pmc_readl(c->reg); 2024 val = pmc_readl(c->reg);
1819 val &= ~(0x1 << c->u.periph.clk_num); 2025 val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@ static void tegra30_clk_out_disable(struct clk *c)
1821 spin_unlock_irqrestore(&clk_out_lock, flags); 2027 spin_unlock_irqrestore(&clk_out_lock, flags);
1822} 2028}
1823 2029
1824static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p) 2030static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
1825{ 2031{
2032 struct clk_tegra *c = to_clk_tegra(hw);
1826 u32 val; 2033 u32 val;
1827 unsigned long flags; 2034 unsigned long flags;
1828 const struct clk_mux_sel *sel;
1829 2035
1830 pr_debug("%s: %s %s\n", __func__, c->name, p->name); 2036 spin_lock_irqsave(&clk_out_lock, flags);
1831 2037 val = pmc_readl(c->reg);
1832 for (sel = c->inputs; sel->input != NULL; sel++) { 2038 val &= ~periph_clk_source_mask(c);
1833 if (sel->input == p) { 2039 val |= (index << periph_clk_source_shift(c));
1834 if (c->refcnt) 2040 pmc_writel(val, c->reg);
1835 clk_enable(p); 2041 spin_unlock_irqrestore(&clk_out_lock, flags);
1836 2042
1837 spin_lock_irqsave(&clk_out_lock, flags); 2043 return 0;
1838 val = pmc_readl(c->reg); 2044}
1839 val &= ~periph_clk_source_mask(c);
1840 val |= (sel->value << periph_clk_source_shift(c));
1841 pmc_writel(val, c->reg);
1842 spin_unlock_irqrestore(&clk_out_lock, flags);
1843 2045
1844 if (c->refcnt && c->parent) 2046static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
1845 clk_disable(c->parent); 2047{
2048 struct clk_tegra *c = to_clk_tegra(hw);
2049 u32 val = pmc_readl(c->reg);
2050 int source;
1846 2051
1847 clk_reparent(c, p); 2052 source = (val & periph_clk_source_mask(c)) >>
1848 return 0; 2053 periph_clk_source_shift(c);
1849 } 2054 return source;
1850 }
1851 return -EINVAL;
1852} 2055}
1853 2056
1854static struct clk_ops tegra_clk_out_ops = { 2057struct clk_ops tegra_clk_out_ops = {
1855 .init = &tegra30_clk_out_init, 2058 .is_enabled = tegra30_clk_out_is_enabled,
1856 .enable = &tegra30_clk_out_enable, 2059 .enable = tegra30_clk_out_enable,
1857 .disable = &tegra30_clk_out_disable, 2060 .disable = tegra30_clk_out_disable,
1858 .set_parent = &tegra30_clk_out_set_parent, 2061 .set_parent = tegra30_clk_out_set_parent,
2062 .get_parent = tegra30_clk_out_get_parent,
2063 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1859}; 2064};
1860 2065
1861
1862/* Clock doubler ops */ 2066/* Clock doubler ops */
1863static void tegra30_clk_double_init(struct clk *c) 2067static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
1864{ 2068{
1865 u32 val = clk_readl(c->reg); 2069 struct clk_tegra *c = to_clk_tegra(hw);
1866 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; 2070
1867 c->div = 1;
1868 c->state = ON; 2071 c->state = ON;
1869 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) 2072 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1870 c->state = OFF; 2073 c->state = OFF;
2074 return c->state;
1871}; 2075};
1872 2076
1873static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate) 2077static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2078 unsigned long parent_rate)
1874{ 2079{
2080 struct clk_tegra *c = to_clk_tegra(hw);
1875 u32 val; 2081 u32 val;
1876 unsigned long parent_rate = clk_get_rate(c->parent); 2082
1877 if (rate == parent_rate) { 2083 if (rate == parent_rate) {
1878 val = clk_readl(c->reg) | (0x1 << c->reg_shift); 2084 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
1879 clk_writel(val, c->reg); 2085 clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@ static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
1890 return -EINVAL; 2096 return -EINVAL;
1891} 2097}
1892 2098
1893static struct clk_ops tegra_clk_double_ops = { 2099static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
1894 .init = &tegra30_clk_double_init, 2100 unsigned long parent_rate)
1895 .enable = &tegra30_periph_clk_enable, 2101{
1896 .disable = &tegra30_periph_clk_disable, 2102 struct clk_tegra *c = to_clk_tegra(hw);
1897 .set_rate = &tegra30_clk_double_set_rate, 2103 u64 rate = parent_rate;
1898};
1899 2104
1900/* Audio sync clock ops */ 2105 u32 val = clk_readl(c->reg);
1901static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate) 2106 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2107 c->div = 1;
2108
2109 if (c->mul != 0 && c->div != 0) {
2110 rate *= c->mul;
2111 rate += c->div - 1; /* round up */
2112 do_div(rate, c->div);
2113 }
2114
2115 return rate;
2116}
2117
2118static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2119 unsigned long *prate)
1902{ 2120{
1903 c->rate = rate; 2121 unsigned long output_rate = *prate;
1904 return 0; 2122
2123 do_div(output_rate, 2);
2124 return output_rate;
1905} 2125}
1906 2126
1907static struct clk_ops tegra_sync_source_ops = { 2127struct clk_ops tegra30_clk_double_ops = {
1908 .set_rate = &tegra30_sync_source_set_rate, 2128 .is_enabled = tegra30_clk_double_is_enabled,
2129 .enable = tegra30_periph_clk_enable,
2130 .disable = tegra30_periph_clk_disable,
2131 .recalc_rate = tegra30_clk_double_recalc_rate,
2132 .round_rate = tegra30_clk_double_round_rate,
2133 .set_rate = tegra30_clk_double_set_rate,
2134};
2135
2136/* Audio sync clock ops */
2137struct clk_ops tegra_sync_source_ops = {
2138 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1909}; 2139};
1910 2140
1911static void tegra30_audio_sync_clk_init(struct clk *c) 2141static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
1912{ 2142{
1913 int source; 2143 struct clk_tegra *c = to_clk_tegra(hw);
1914 const struct clk_mux_sel *sel;
1915 u32 val = clk_readl(c->reg); 2144 u32 val = clk_readl(c->reg);
1916 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; 2145 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
1917 source = val & AUDIO_SYNC_SOURCE_MASK; 2146 return c->state;
1918 for (sel = c->inputs; sel->input != NULL; sel++)
1919 if (sel->value == source)
1920 break;
1921 BUG_ON(sel->input == NULL);
1922 c->parent = sel->input;
1923} 2147}
1924 2148
1925static int tegra30_audio_sync_clk_enable(struct clk *c) 2149static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
1926{ 2150{
2151 struct clk_tegra *c = to_clk_tegra(hw);
1927 u32 val = clk_readl(c->reg); 2152 u32 val = clk_readl(c->reg);
1928 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); 2153 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
1929 return 0; 2154 return 0;
1930} 2155}
1931 2156
1932static void tegra30_audio_sync_clk_disable(struct clk *c) 2157static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
1933{ 2158{
2159 struct clk_tegra *c = to_clk_tegra(hw);
1934 u32 val = clk_readl(c->reg); 2160 u32 val = clk_readl(c->reg);
1935 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); 2161 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
1936} 2162}
1937 2163
1938static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p) 2164static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1939{ 2165{
2166 struct clk_tegra *c = to_clk_tegra(hw);
1940 u32 val; 2167 u32 val;
1941 const struct clk_mux_sel *sel;
1942 for (sel = c->inputs; sel->input != NULL; sel++) {
1943 if (sel->input == p) {
1944 val = clk_readl(c->reg);
1945 val &= ~AUDIO_SYNC_SOURCE_MASK;
1946 val |= sel->value;
1947
1948 if (c->refcnt)
1949 clk_enable(p);
1950 2168
1951 clk_writel(val, c->reg); 2169 val = clk_readl(c->reg);
2170 val &= ~AUDIO_SYNC_SOURCE_MASK;
2171 val |= index;
1952 2172
1953 if (c->refcnt && c->parent) 2173 clk_writel(val, c->reg);
1954 clk_disable(c->parent); 2174 return 0;
2175}
1955 2176
1956 clk_reparent(c, p); 2177static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
1957 return 0; 2178{
1958 } 2179 struct clk_tegra *c = to_clk_tegra(hw);
1959 } 2180 u32 val = clk_readl(c->reg);
2181 int source;
1960 2182
1961 return -EINVAL; 2183 source = val & AUDIO_SYNC_SOURCE_MASK;
2184 return source;
1962} 2185}
1963 2186
1964static struct clk_ops tegra_audio_sync_clk_ops = { 2187struct clk_ops tegra30_audio_sync_clk_ops = {
1965 .init = tegra30_audio_sync_clk_init, 2188 .is_enabled = tegra30_audio_sync_clk_is_enabled,
1966 .enable = tegra30_audio_sync_clk_enable, 2189 .enable = tegra30_audio_sync_clk_enable,
1967 .disable = tegra30_audio_sync_clk_disable, 2190 .disable = tegra30_audio_sync_clk_disable,
1968 .set_parent = tegra30_audio_sync_clk_set_parent, 2191 .set_parent = tegra30_audio_sync_clk_set_parent,
2192 .get_parent = tegra30_audio_sync_clk_get_parent,
2193 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1969}; 2194};
1970 2195
1971/* cml0 (pcie), and cml1 (sata) clock ops */ 2196/* cml0 (pcie), and cml1 (sata) clock ops */
1972static void tegra30_cml_clk_init(struct clk *c) 2197static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
1973{ 2198{
2199 struct clk_tegra *c = to_clk_tegra(hw);
1974 u32 val = clk_readl(c->reg); 2200 u32 val = clk_readl(c->reg);
1975 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; 2201 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2202 return c->state;
1976} 2203}
1977 2204
1978static int tegra30_cml_clk_enable(struct clk *c) 2205static int tegra30_cml_clk_enable(struct clk_hw *hw)
1979{ 2206{
2207 struct clk_tegra *c = to_clk_tegra(hw);
2208
1980 u32 val = clk_readl(c->reg); 2209 u32 val = clk_readl(c->reg);
1981 val |= (0x1 << c->u.periph.clk_num); 2210 val |= (0x1 << c->u.periph.clk_num);
1982 clk_writel(val, c->reg); 2211 clk_writel(val, c->reg);
2212
1983 return 0; 2213 return 0;
1984} 2214}
1985 2215
1986static void tegra30_cml_clk_disable(struct clk *c) 2216static void tegra30_cml_clk_disable(struct clk_hw *hw)
1987{ 2217{
2218 struct clk_tegra *c = to_clk_tegra(hw);
2219
1988 u32 val = clk_readl(c->reg); 2220 u32 val = clk_readl(c->reg);
1989 val &= ~(0x1 << c->u.periph.clk_num); 2221 val &= ~(0x1 << c->u.periph.clk_num);
1990 clk_writel(val, c->reg); 2222 clk_writel(val, c->reg);
1991} 2223}
1992 2224
1993static struct clk_ops tegra_cml_clk_ops = { 2225struct clk_ops tegra_cml_clk_ops = {
1994 .init = &tegra30_cml_clk_init, 2226 .is_enabled = tegra30_cml_clk_is_enabled,
1995 .enable = &tegra30_cml_clk_enable, 2227 .enable = tegra30_cml_clk_enable,
1996 .disable = &tegra30_cml_clk_disable, 2228 .disable = tegra30_cml_clk_disable,
1997}; 2229 .recalc_rate = tegra30_clk_fixed_recalc_rate,
1998
1999/* Clock definitions */
2000static struct clk tegra_clk_32k = {
2001 .name = "clk_32k",
2002 .rate = 32768,
2003 .ops = NULL,
2004 .max_rate = 32768,
2005};
2006
2007static struct clk tegra_clk_m = {
2008 .name = "clk_m",
2009 .flags = ENABLE_ON_INIT,
2010 .ops = &tegra_clk_m_ops,
2011 .reg = 0x1fc,
2012 .reg_shift = 28,
2013 .max_rate = 48000000,
2014};
2015
2016static struct clk tegra_clk_m_div2 = {
2017 .name = "clk_m_div2",
2018 .ops = &tegra_clk_m_div_ops,
2019 .parent = &tegra_clk_m,
2020 .mul = 1,
2021 .div = 2,
2022 .state = ON,
2023 .max_rate = 24000000,
2024};
2025
2026static struct clk tegra_clk_m_div4 = {
2027 .name = "clk_m_div4",
2028 .ops = &tegra_clk_m_div_ops,
2029 .parent = &tegra_clk_m,
2030 .mul = 1,
2031 .div = 4,
2032 .state = ON,
2033 .max_rate = 12000000,
2034};
2035
2036static struct clk tegra_pll_ref = {
2037 .name = "pll_ref",
2038 .flags = ENABLE_ON_INIT,
2039 .ops = &tegra_pll_ref_ops,
2040 .parent = &tegra_clk_m,
2041 .max_rate = 26000000,
2042};
2043
2044static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
2045 { 12000000, 1040000000, 520, 6, 1, 8},
2046 { 13000000, 1040000000, 480, 6, 1, 8},
2047 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
2048 { 19200000, 1040000000, 325, 6, 1, 6},
2049 { 26000000, 1040000000, 520, 13, 1, 8},
2050
2051 { 12000000, 832000000, 416, 6, 1, 8},
2052 { 13000000, 832000000, 832, 13, 1, 8},
2053 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
2054 { 19200000, 832000000, 260, 6, 1, 8},
2055 { 26000000, 832000000, 416, 13, 1, 8},
2056
2057 { 12000000, 624000000, 624, 12, 1, 8},
2058 { 13000000, 624000000, 624, 13, 1, 8},
2059 { 16800000, 600000000, 520, 14, 1, 8},
2060 { 19200000, 624000000, 520, 16, 1, 8},
2061 { 26000000, 624000000, 624, 26, 1, 8},
2062
2063 { 12000000, 600000000, 600, 12, 1, 8},
2064 { 13000000, 600000000, 600, 13, 1, 8},
2065 { 16800000, 600000000, 500, 14, 1, 8},
2066 { 19200000, 600000000, 375, 12, 1, 6},
2067 { 26000000, 600000000, 600, 26, 1, 8},
2068
2069 { 12000000, 520000000, 520, 12, 1, 8},
2070 { 13000000, 520000000, 520, 13, 1, 8},
2071 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
2072 { 19200000, 520000000, 325, 12, 1, 6},
2073 { 26000000, 520000000, 520, 26, 1, 8},
2074
2075 { 12000000, 416000000, 416, 12, 1, 8},
2076 { 13000000, 416000000, 416, 13, 1, 8},
2077 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
2078 { 19200000, 416000000, 260, 12, 1, 6},
2079 { 26000000, 416000000, 416, 26, 1, 8},
2080 { 0, 0, 0, 0, 0, 0 },
2081};
2082
2083static struct clk tegra_pll_c = {
2084 .name = "pll_c",
2085 .flags = PLL_HAS_CPCON,
2086 .ops = &tegra_pll_ops,
2087 .reg = 0x80,
2088 .parent = &tegra_pll_ref,
2089 .max_rate = 1400000000,
2090 .u.pll = {
2091 .input_min = 2000000,
2092 .input_max = 31000000,
2093 .cf_min = 1000000,
2094 .cf_max = 6000000,
2095 .vco_min = 20000000,
2096 .vco_max = 1400000000,
2097 .freq_table = tegra_pll_c_freq_table,
2098 .lock_delay = 300,
2099 },
2100};
2101
2102static struct clk tegra_pll_c_out1 = {
2103 .name = "pll_c_out1",
2104 .ops = &tegra_pll_div_ops,
2105 .flags = DIV_U71,
2106 .parent = &tegra_pll_c,
2107 .reg = 0x84,
2108 .reg_shift = 0,
2109 .max_rate = 700000000,
2110};
2111
2112static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
2113 { 12000000, 666000000, 666, 12, 1, 8},
2114 { 13000000, 666000000, 666, 13, 1, 8},
2115 { 16800000, 666000000, 555, 14, 1, 8},
2116 { 19200000, 666000000, 555, 16, 1, 8},
2117 { 26000000, 666000000, 666, 26, 1, 8},
2118 { 12000000, 600000000, 600, 12, 1, 8},
2119 { 13000000, 600000000, 600, 13, 1, 8},
2120 { 16800000, 600000000, 500, 14, 1, 8},
2121 { 19200000, 600000000, 375, 12, 1, 6},
2122 { 26000000, 600000000, 600, 26, 1, 8},
2123 { 0, 0, 0, 0, 0, 0 },
2124};
2125
2126static struct clk tegra_pll_m = {
2127 .name = "pll_m",
2128 .flags = PLL_HAS_CPCON | PLLM,
2129 .ops = &tegra_pll_ops,
2130 .reg = 0x90,
2131 .parent = &tegra_pll_ref,
2132 .max_rate = 800000000,
2133 .u.pll = {
2134 .input_min = 2000000,
2135 .input_max = 31000000,
2136 .cf_min = 1000000,
2137 .cf_max = 6000000,
2138 .vco_min = 20000000,
2139 .vco_max = 1200000000,
2140 .freq_table = tegra_pll_m_freq_table,
2141 .lock_delay = 300,
2142 },
2143};
2144
2145static struct clk tegra_pll_m_out1 = {
2146 .name = "pll_m_out1",
2147 .ops = &tegra_pll_div_ops,
2148 .flags = DIV_U71,
2149 .parent = &tegra_pll_m,
2150 .reg = 0x94,
2151 .reg_shift = 0,
2152 .max_rate = 600000000,
2153};
2154
2155static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
2156 { 12000000, 216000000, 432, 12, 2, 8},
2157 { 13000000, 216000000, 432, 13, 2, 8},
2158 { 16800000, 216000000, 360, 14, 2, 8},
2159 { 19200000, 216000000, 360, 16, 2, 8},
2160 { 26000000, 216000000, 432, 26, 2, 8},
2161 { 0, 0, 0, 0, 0, 0 },
2162};
2163
2164static struct clk tegra_pll_p = {
2165 .name = "pll_p",
2166 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
2167 .ops = &tegra_pll_ops,
2168 .reg = 0xa0,
2169 .parent = &tegra_pll_ref,
2170 .max_rate = 432000000,
2171 .u.pll = {
2172 .input_min = 2000000,
2173 .input_max = 31000000,
2174 .cf_min = 1000000,
2175 .cf_max = 6000000,
2176 .vco_min = 20000000,
2177 .vco_max = 1400000000,
2178 .freq_table = tegra_pll_p_freq_table,
2179 .lock_delay = 300,
2180 .fixed_rate = 408000000,
2181 },
2182};
2183
2184static struct clk tegra_pll_p_out1 = {
2185 .name = "pll_p_out1",
2186 .ops = &tegra_pll_div_ops,
2187 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2188 .parent = &tegra_pll_p,
2189 .reg = 0xa4,
2190 .reg_shift = 0,
2191 .max_rate = 432000000,
2192};
2193
2194static struct clk tegra_pll_p_out2 = {
2195 .name = "pll_p_out2",
2196 .ops = &tegra_pll_div_ops,
2197 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2198 .parent = &tegra_pll_p,
2199 .reg = 0xa4,
2200 .reg_shift = 16,
2201 .max_rate = 432000000,
2202};
2203
2204static struct clk tegra_pll_p_out3 = {
2205 .name = "pll_p_out3",
2206 .ops = &tegra_pll_div_ops,
2207 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2208 .parent = &tegra_pll_p,
2209 .reg = 0xa8,
2210 .reg_shift = 0,
2211 .max_rate = 432000000,
2212};
2213
2214static struct clk tegra_pll_p_out4 = {
2215 .name = "pll_p_out4",
2216 .ops = &tegra_pll_div_ops,
2217 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
2218 .parent = &tegra_pll_p,
2219 .reg = 0xa8,
2220 .reg_shift = 16,
2221 .max_rate = 432000000,
2222};
2223
2224static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
2225 { 9600000, 564480000, 294, 5, 1, 4},
2226 { 9600000, 552960000, 288, 5, 1, 4},
2227 { 9600000, 24000000, 5, 2, 1, 1},
2228
2229 { 28800000, 56448000, 49, 25, 1, 1},
2230 { 28800000, 73728000, 64, 25, 1, 1},
2231 { 28800000, 24000000, 5, 6, 1, 1},
2232 { 0, 0, 0, 0, 0, 0 },
2233};
2234
2235static struct clk tegra_pll_a = {
2236 .name = "pll_a",
2237 .flags = PLL_HAS_CPCON,
2238 .ops = &tegra_pll_ops,
2239 .reg = 0xb0,
2240 .parent = &tegra_pll_p_out1,
2241 .max_rate = 700000000,
2242 .u.pll = {
2243 .input_min = 2000000,
2244 .input_max = 31000000,
2245 .cf_min = 1000000,
2246 .cf_max = 6000000,
2247 .vco_min = 20000000,
2248 .vco_max = 1400000000,
2249 .freq_table = tegra_pll_a_freq_table,
2250 .lock_delay = 300,
2251 },
2252};
2253
2254static struct clk tegra_pll_a_out0 = {
2255 .name = "pll_a_out0",
2256 .ops = &tegra_pll_div_ops,
2257 .flags = DIV_U71,
2258 .parent = &tegra_pll_a,
2259 .reg = 0xb4,
2260 .reg_shift = 0,
2261 .max_rate = 100000000,
2262};
2263
2264static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
2265 { 12000000, 216000000, 216, 12, 1, 4},
2266 { 13000000, 216000000, 216, 13, 1, 4},
2267 { 16800000, 216000000, 180, 14, 1, 4},
2268 { 19200000, 216000000, 180, 16, 1, 4},
2269 { 26000000, 216000000, 216, 26, 1, 4},
2270
2271 { 12000000, 594000000, 594, 12, 1, 8},
2272 { 13000000, 594000000, 594, 13, 1, 8},
2273 { 16800000, 594000000, 495, 14, 1, 8},
2274 { 19200000, 594000000, 495, 16, 1, 8},
2275 { 26000000, 594000000, 594, 26, 1, 8},
2276
2277 { 12000000, 1000000000, 1000, 12, 1, 12},
2278 { 13000000, 1000000000, 1000, 13, 1, 12},
2279 { 19200000, 1000000000, 625, 12, 1, 8},
2280 { 26000000, 1000000000, 1000, 26, 1, 12},
2281
2282 { 0, 0, 0, 0, 0, 0 },
2283};
2284
2285static struct clk tegra_pll_d = {
2286 .name = "pll_d",
2287 .flags = PLL_HAS_CPCON | PLLD,
2288 .ops = &tegra_plld_ops,
2289 .reg = 0xd0,
2290 .parent = &tegra_pll_ref,
2291 .max_rate = 1000000000,
2292 .u.pll = {
2293 .input_min = 2000000,
2294 .input_max = 40000000,
2295 .cf_min = 1000000,
2296 .cf_max = 6000000,
2297 .vco_min = 40000000,
2298 .vco_max = 1000000000,
2299 .freq_table = tegra_pll_d_freq_table,
2300 .lock_delay = 1000,
2301 },
2302};
2303
2304static struct clk tegra_pll_d_out0 = {
2305 .name = "pll_d_out0",
2306 .ops = &tegra_pll_div_ops,
2307 .flags = DIV_2 | PLLD,
2308 .parent = &tegra_pll_d,
2309 .max_rate = 500000000,
2310};
2311
2312static struct clk tegra_pll_d2 = {
2313 .name = "pll_d2",
2314 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
2315 .ops = &tegra_plld_ops,
2316 .reg = 0x4b8,
2317 .parent = &tegra_pll_ref,
2318 .max_rate = 1000000000,
2319 .u.pll = {
2320 .input_min = 2000000,
2321 .input_max = 40000000,
2322 .cf_min = 1000000,
2323 .cf_max = 6000000,
2324 .vco_min = 40000000,
2325 .vco_max = 1000000000,
2326 .freq_table = tegra_pll_d_freq_table,
2327 .lock_delay = 1000,
2328 },
2329};
2330
2331static struct clk tegra_pll_d2_out0 = {
2332 .name = "pll_d2_out0",
2333 .ops = &tegra_pll_div_ops,
2334 .flags = DIV_2 | PLLD,
2335 .parent = &tegra_pll_d2,
2336 .max_rate = 500000000,
2337};
2338
2339static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
2340 { 12000000, 480000000, 960, 12, 2, 12},
2341 { 13000000, 480000000, 960, 13, 2, 12},
2342 { 16800000, 480000000, 400, 7, 2, 5},
2343 { 19200000, 480000000, 200, 4, 2, 3},
2344 { 26000000, 480000000, 960, 26, 2, 12},
2345 { 0, 0, 0, 0, 0, 0 },
2346};
2347
2348static struct clk tegra_pll_u = {
2349 .name = "pll_u",
2350 .flags = PLL_HAS_CPCON | PLLU,
2351 .ops = &tegra_pll_ops,
2352 .reg = 0xc0,
2353 .parent = &tegra_pll_ref,
2354 .max_rate = 480000000,
2355 .u.pll = {
2356 .input_min = 2000000,
2357 .input_max = 40000000,
2358 .cf_min = 1000000,
2359 .cf_max = 6000000,
2360 .vco_min = 480000000,
2361 .vco_max = 960000000,
2362 .freq_table = tegra_pll_u_freq_table,
2363 .lock_delay = 1000,
2364 },
2365};
2366
2367static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
2368 /* 1.7 GHz */
2369 { 12000000, 1700000000, 850, 6, 1, 8},
2370 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
2371 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
2372 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
2373 { 26000000, 1700000000, 850, 13, 1, 8},
2374
2375 /* 1.6 GHz */
2376 { 12000000, 1600000000, 800, 6, 1, 8},
2377 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
2378 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
2379 { 19200000, 1600000000, 500, 6, 1, 8},
2380 { 26000000, 1600000000, 800, 13, 1, 8},
2381
2382 /* 1.5 GHz */
2383 { 12000000, 1500000000, 750, 6, 1, 8},
2384 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
2385 { 16800000, 1500000000, 625, 7, 1, 8},
2386 { 19200000, 1500000000, 625, 8, 1, 8},
2387 { 26000000, 1500000000, 750, 13, 1, 8},
2388
2389 /* 1.4 GHz */
2390 { 12000000, 1400000000, 700, 6, 1, 8},
2391 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
2392 { 16800000, 1400000000, 1000, 12, 1, 8},
2393 { 19200000, 1400000000, 875, 12, 1, 8},
2394 { 26000000, 1400000000, 700, 13, 1, 8},
2395
2396 /* 1.3 GHz */
2397 { 12000000, 1300000000, 975, 9, 1, 8},
2398 { 13000000, 1300000000, 1000, 10, 1, 8},
2399 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
2400 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
2401 { 26000000, 1300000000, 650, 13, 1, 8},
2402
2403 /* 1.2 GHz */
2404 { 12000000, 1200000000, 1000, 10, 1, 8},
2405 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
2406 { 16800000, 1200000000, 1000, 14, 1, 8},
2407 { 19200000, 1200000000, 1000, 16, 1, 8},
2408 { 26000000, 1200000000, 600, 13, 1, 8},
2409
2410 /* 1.1 GHz */
2411 { 12000000, 1100000000, 825, 9, 1, 8},
2412 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
2413 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
2414 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
2415 { 26000000, 1100000000, 550, 13, 1, 8},
2416
2417 /* 1 GHz */
2418 { 12000000, 1000000000, 1000, 12, 1, 8},
2419 { 13000000, 1000000000, 1000, 13, 1, 8},
2420 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
2421 { 19200000, 1000000000, 625, 12, 1, 8},
2422 { 26000000, 1000000000, 1000, 26, 1, 8},
2423
2424 { 0, 0, 0, 0, 0, 0 },
2425};
2426
2427static struct clk tegra_pll_x = {
2428 .name = "pll_x",
2429 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
2430 .ops = &tegra_pll_ops,
2431 .reg = 0xe0,
2432 .parent = &tegra_pll_ref,
2433 .max_rate = 1700000000,
2434 .u.pll = {
2435 .input_min = 2000000,
2436 .input_max = 31000000,
2437 .cf_min = 1000000,
2438 .cf_max = 6000000,
2439 .vco_min = 20000000,
2440 .vco_max = 1700000000,
2441 .freq_table = tegra_pll_x_freq_table,
2442 .lock_delay = 300,
2443 },
2444};
2445
2446static struct clk tegra_pll_x_out0 = {
2447 .name = "pll_x_out0",
2448 .ops = &tegra_pll_div_ops,
2449 .flags = DIV_2 | PLLX,
2450 .parent = &tegra_pll_x,
2451 .max_rate = 850000000,
2452};
2453
2454
2455static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
2456 /* PLLE special case: use cpcon field to store cml divider value */
2457 { 12000000, 100000000, 150, 1, 18, 11},
2458 { 216000000, 100000000, 200, 18, 24, 13},
2459 { 0, 0, 0, 0, 0, 0 },
2460};
2461
2462static struct clk tegra_pll_e = {
2463 .name = "pll_e",
2464 .flags = PLL_ALT_MISC_REG,
2465 .ops = &tegra_plle_ops,
2466 .reg = 0xe8,
2467 .max_rate = 100000000,
2468 .u.pll = {
2469 .input_min = 12000000,
2470 .input_max = 216000000,
2471 .cf_min = 12000000,
2472 .cf_max = 12000000,
2473 .vco_min = 1200000000,
2474 .vco_max = 2400000000U,
2475 .freq_table = tegra_pll_e_freq_table,
2476 .lock_delay = 300,
2477 .fixed_rate = 100000000,
2478 },
2479};
2480
2481static struct clk tegra_cml0_clk = {
2482 .name = "cml0",
2483 .parent = &tegra_pll_e,
2484 .ops = &tegra_cml_clk_ops,
2485 .reg = PLLE_AUX,
2486 .max_rate = 100000000,
2487 .u.periph = {
2488 .clk_num = 0,
2489 },
2490};
2491
2492static struct clk tegra_cml1_clk = {
2493 .name = "cml1",
2494 .parent = &tegra_pll_e,
2495 .ops = &tegra_cml_clk_ops,
2496 .reg = PLLE_AUX,
2497 .max_rate = 100000000,
2498 .u.periph = {
2499 .clk_num = 1,
2500 },
2501};
2502
2503static struct clk tegra_pciex_clk = {
2504 .name = "pciex",
2505 .parent = &tegra_pll_e,
2506 .ops = &tegra_pciex_clk_ops,
2507 .max_rate = 100000000,
2508 .u.periph = {
2509 .clk_num = 74,
2510 },
2511};
2512
2513/* Audio sync clocks */
2514#define SYNC_SOURCE(_id) \
2515 { \
2516 .name = #_id "_sync", \
2517 .rate = 24000000, \
2518 .max_rate = 24000000, \
2519 .ops = &tegra_sync_source_ops \
2520 }
2521static struct clk tegra_sync_source_list[] = {
2522 SYNC_SOURCE(spdif_in),
2523 SYNC_SOURCE(i2s0),
2524 SYNC_SOURCE(i2s1),
2525 SYNC_SOURCE(i2s2),
2526 SYNC_SOURCE(i2s3),
2527 SYNC_SOURCE(i2s4),
2528 SYNC_SOURCE(vimclk),
2529};
2530
2531static struct clk_mux_sel mux_audio_sync_clk[] = {
2532 { .input = &tegra_sync_source_list[0], .value = 0},
2533 { .input = &tegra_sync_source_list[1], .value = 1},
2534 { .input = &tegra_sync_source_list[2], .value = 2},
2535 { .input = &tegra_sync_source_list[3], .value = 3},
2536 { .input = &tegra_sync_source_list[4], .value = 4},
2537 { .input = &tegra_sync_source_list[5], .value = 5},
2538 { .input = &tegra_pll_a_out0, .value = 6},
2539 { .input = &tegra_sync_source_list[6], .value = 7},
2540 { 0, 0 }
2541}; 2230};
2542 2231
2543#define AUDIO_SYNC_CLK(_id, _index) \ 2232struct clk_ops tegra_pciex_clk_ops = {
2544 { \ 2233 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2545 .name = #_id, \
2546 .inputs = mux_audio_sync_clk, \
2547 .reg = 0x4A0 + (_index) * 4, \
2548 .max_rate = 24000000, \
2549 .ops = &tegra_audio_sync_clk_ops \
2550 }
2551static struct clk tegra_clk_audio_list[] = {
2552 AUDIO_SYNC_CLK(audio0, 0),
2553 AUDIO_SYNC_CLK(audio1, 1),
2554 AUDIO_SYNC_CLK(audio2, 2),
2555 AUDIO_SYNC_CLK(audio3, 3),
2556 AUDIO_SYNC_CLK(audio4, 4),
2557 AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
2558}; 2234};
2559 2235
2560#define AUDIO_SYNC_2X_CLK(_id, _index) \ 2236/* Tegra30 CPU clock and reset control functions */
2561 { \ 2237static void tegra30_wait_cpu_in_reset(u32 cpu)
2562 .name = #_id "_2x", \ 2238{
2563 .flags = PERIPH_NO_RESET, \ 2239 unsigned int reg;
2564 .max_rate = 48000000, \
2565 .ops = &tegra_clk_double_ops, \
2566 .reg = 0x49C, \
2567 .reg_shift = 24 + (_index), \
2568 .parent = &tegra_clk_audio_list[(_index)], \
2569 .u.periph = { \
2570 .clk_num = 113 + (_index), \
2571 }, \
2572 }
2573static struct clk tegra_clk_audio_2x_list[] = {
2574 AUDIO_SYNC_2X_CLK(audio0, 0),
2575 AUDIO_SYNC_2X_CLK(audio1, 1),
2576 AUDIO_SYNC_2X_CLK(audio2, 2),
2577 AUDIO_SYNC_2X_CLK(audio3, 3),
2578 AUDIO_SYNC_2X_CLK(audio4, 4),
2579 AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
2580};
2581 2240
2582#define MUX_I2S_SPDIF(_id, _index) \ 2241 do {
2583static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ 2242 reg = readl(reg_clk_base +
2584 {.input = &tegra_pll_a_out0, .value = 0}, \ 2243 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2585 {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ 2244 cpu_relax();
2586 {.input = &tegra_pll_p, .value = 2}, \ 2245 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2587 {.input = &tegra_clk_m, .value = 3}, \
2588 { 0, 0}, \
2589}
2590MUX_I2S_SPDIF(audio0, 0);
2591MUX_I2S_SPDIF(audio1, 1);
2592MUX_I2S_SPDIF(audio2, 2);
2593MUX_I2S_SPDIF(audio3, 3);
2594MUX_I2S_SPDIF(audio4, 4);
2595MUX_I2S_SPDIF(audio, 5); /* SPDIF */
2596
2597/* External clock outputs (through PMC) */
2598#define MUX_EXTERN_OUT(_id) \
2599static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
2600 {.input = &tegra_clk_m, .value = 0}, \
2601 {.input = &tegra_clk_m_div2, .value = 1}, \
2602 {.input = &tegra_clk_m_div4, .value = 2}, \
2603 {.input = NULL, .value = 3}, /* placeholder */ \
2604 { 0, 0}, \
2605}
2606MUX_EXTERN_OUT(1);
2607MUX_EXTERN_OUT(2);
2608MUX_EXTERN_OUT(3);
2609
2610static struct clk_mux_sel *mux_extern_out_list[] = {
2611 mux_clkm_clkm2_clkm4_extern1,
2612 mux_clkm_clkm2_clkm4_extern2,
2613 mux_clkm_clkm2_clkm4_extern3,
2614};
2615 2246
2616#define CLK_OUT_CLK(_id) \ 2247 return;
2617 { \ 2248}
2618 .name = "clk_out_" #_id, \
2619 .lookup = { \
2620 .dev_id = "clk_out_" #_id, \
2621 .con_id = "extern" #_id, \
2622 }, \
2623 .ops = &tegra_clk_out_ops, \
2624 .reg = 0x1a8, \
2625 .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
2626 .flags = MUX_CLK_OUT, \
2627 .max_rate = 216000000, \
2628 .u.periph = { \
2629 .clk_num = (_id - 1) * 8 + 2, \
2630 }, \
2631 }
2632static struct clk tegra_clk_out_list[] = {
2633 CLK_OUT_CLK(1),
2634 CLK_OUT_CLK(2),
2635 CLK_OUT_CLK(3),
2636};
2637 2249
2638/* called after peripheral external clocks are initialized */ 2250static void tegra30_put_cpu_in_reset(u32 cpu)
2639static void init_clk_out_mux(void)
2640{ 2251{
2641 int i; 2252 writel(CPU_RESET(cpu),
2642 struct clk *c; 2253 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2643 2254 dmb();
2644 /* output clock con_id is the name of peripheral
2645 external clock connected to input 3 of the output mux */
2646 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
2647 c = tegra_get_clock_by_name(
2648 tegra_clk_out_list[i].lookup.con_id);
2649 if (!c)
2650 pr_err("%s: could not find clk %s\n", __func__,
2651 tegra_clk_out_list[i].lookup.con_id);
2652 mux_extern_out_list[i][3].input = c;
2653 }
2654} 2255}
2655 2256
2656/* Peripheral muxes */ 2257static void tegra30_cpu_out_of_reset(u32 cpu)
2657static struct clk_mux_sel mux_sclk[] = {
2658 { .input = &tegra_clk_m, .value = 0},
2659 { .input = &tegra_pll_c_out1, .value = 1},
2660 { .input = &tegra_pll_p_out4, .value = 2},
2661 { .input = &tegra_pll_p_out3, .value = 3},
2662 { .input = &tegra_pll_p_out2, .value = 4},
2663 /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
2664 { .input = &tegra_clk_32k, .value = 6},
2665 { .input = &tegra_pll_m_out1, .value = 7},
2666 { 0, 0},
2667};
2668
2669static struct clk tegra_clk_sclk = {
2670 .name = "sclk",
2671 .inputs = mux_sclk,
2672 .reg = 0x28,
2673 .ops = &tegra_super_ops,
2674 .max_rate = 334000000,
2675 .min_rate = 40000000,
2676};
2677
2678static struct clk tegra_clk_blink = {
2679 .name = "blink",
2680 .parent = &tegra_clk_32k,
2681 .reg = 0x40,
2682 .ops = &tegra_blink_clk_ops,
2683 .max_rate = 32768,
2684};
2685
2686static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
2687 { .input = &tegra_pll_m, .value = 0},
2688 { .input = &tegra_pll_c, .value = 1},
2689 { .input = &tegra_pll_p, .value = 2},
2690 { .input = &tegra_pll_a_out0, .value = 3},
2691 { 0, 0},
2692};
2693
2694static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
2695 { .input = &tegra_pll_p, .value = 0},
2696 { .input = &tegra_pll_c, .value = 1},
2697 { .input = &tegra_pll_m, .value = 2},
2698 { .input = &tegra_clk_m, .value = 3},
2699 { 0, 0},
2700};
2701
2702static struct clk_mux_sel mux_pllp_clkm[] = {
2703 { .input = &tegra_pll_p, .value = 0},
2704 { .input = &tegra_clk_m, .value = 3},
2705 { 0, 0},
2706};
2707
2708static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
2709 {.input = &tegra_pll_p, .value = 0},
2710 {.input = &tegra_pll_d_out0, .value = 1},
2711 {.input = &tegra_pll_c, .value = 2},
2712 {.input = &tegra_clk_m, .value = 3},
2713 { 0, 0},
2714};
2715
2716static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
2717 {.input = &tegra_pll_p, .value = 0},
2718 {.input = &tegra_pll_m, .value = 1},
2719 {.input = &tegra_pll_d_out0, .value = 2},
2720 {.input = &tegra_pll_a_out0, .value = 3},
2721 {.input = &tegra_pll_c, .value = 4},
2722 {.input = &tegra_pll_d2_out0, .value = 5},
2723 {.input = &tegra_clk_m, .value = 6},
2724 { 0, 0},
2725};
2726
2727static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
2728 { .input = &tegra_pll_a_out0, .value = 0},
2729 /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
2730 { .input = &tegra_pll_p, .value = 2},
2731 { .input = &tegra_clk_m, .value = 3},
2732 { 0, 0},
2733};
2734
2735static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
2736 {.input = &tegra_pll_p, .value = 0},
2737 {.input = &tegra_pll_c, .value = 1},
2738 {.input = &tegra_clk_32k, .value = 2},
2739 {.input = &tegra_clk_m, .value = 3},
2740 { 0, 0},
2741};
2742
2743static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
2744 {.input = &tegra_pll_p, .value = 0},
2745 {.input = &tegra_pll_c, .value = 1},
2746 {.input = &tegra_clk_m, .value = 2},
2747 {.input = &tegra_clk_32k, .value = 3},
2748 { 0, 0},
2749};
2750
2751static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
2752 {.input = &tegra_pll_p, .value = 0},
2753 {.input = &tegra_pll_c, .value = 1},
2754 {.input = &tegra_pll_m, .value = 2},
2755 { 0, 0},
2756};
2757
2758static struct clk_mux_sel mux_clk_m[] = {
2759 { .input = &tegra_clk_m, .value = 0},
2760 { 0, 0},
2761};
2762
2763static struct clk_mux_sel mux_pllp_out3[] = {
2764 { .input = &tegra_pll_p_out3, .value = 0},
2765 { 0, 0},
2766};
2767
2768static struct clk_mux_sel mux_plld_out0[] = {
2769 { .input = &tegra_pll_d_out0, .value = 0},
2770 { 0, 0},
2771};
2772
2773static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
2774 { .input = &tegra_pll_d_out0, .value = 0},
2775 { .input = &tegra_pll_d2_out0, .value = 1},
2776 { 0, 0},
2777};
2778
2779static struct clk_mux_sel mux_clk_32k[] = {
2780 { .input = &tegra_clk_32k, .value = 0},
2781 { 0, 0},
2782};
2783
2784static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
2785 { .input = &tegra_pll_a_out0, .value = 0},
2786 { .input = &tegra_clk_32k, .value = 1},
2787 { .input = &tegra_pll_p, .value = 2},
2788 { .input = &tegra_clk_m, .value = 3},
2789 { .input = &tegra_pll_e, .value = 4},
2790 { 0, 0},
2791};
2792
2793static struct clk_mux_sel mux_cclk_g[] = {
2794 { .input = &tegra_clk_m, .value = 0},
2795 { .input = &tegra_pll_c, .value = 1},
2796 { .input = &tegra_clk_32k, .value = 2},
2797 { .input = &tegra_pll_m, .value = 3},
2798 { .input = &tegra_pll_p, .value = 4},
2799 { .input = &tegra_pll_p_out4, .value = 5},
2800 { .input = &tegra_pll_p_out3, .value = 6},
2801 { .input = &tegra_pll_x, .value = 8},
2802 { 0, 0},
2803};
2804
2805static struct clk tegra_clk_cclk_g = {
2806 .name = "cclk_g",
2807 .flags = DIV_U71 | DIV_U71_INT,
2808 .inputs = mux_cclk_g,
2809 .reg = 0x368,
2810 .ops = &tegra_super_ops,
2811 .max_rate = 1700000000,
2812};
2813
2814static struct clk tegra30_clk_twd = {
2815 .parent = &tegra_clk_cclk_g,
2816 .name = "twd",
2817 .ops = &tegra30_twd_ops,
2818 .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
2819 .mul = 1,
2820 .div = 2,
2821};
2822
2823#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
2824 { \
2825 .name = _name, \
2826 .lookup = { \
2827 .dev_id = _dev, \
2828 .con_id = _con, \
2829 }, \
2830 .ops = &tegra_periph_clk_ops, \
2831 .reg = _reg, \
2832 .inputs = _inputs, \
2833 .flags = _flags, \
2834 .max_rate = _max, \
2835 .u.periph = { \
2836 .clk_num = _clk_num, \
2837 }, \
2838 }
2839
2840#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
2841 _flags, _ops) \
2842 { \
2843 .name = _name, \
2844 .lookup = { \
2845 .dev_id = _dev, \
2846 .con_id = _con, \
2847 }, \
2848 .ops = _ops, \
2849 .reg = _reg, \
2850 .inputs = _inputs, \
2851 .flags = _flags, \
2852 .max_rate = _max, \
2853 .u.periph = { \
2854 .clk_num = _clk_num, \
2855 }, \
2856 }
2857
2858#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
2859 { \
2860 .name = _name, \
2861 .lookup = { \
2862 .dev_id = _dev, \
2863 .con_id = _con, \
2864 }, \
2865 .ops = &tegra_clk_shared_bus_ops, \
2866 .parent = _parent, \
2867 .u.shared_bus_user = { \
2868 .client_id = _id, \
2869 .client_div = _div, \
2870 .mode = _mode, \
2871 }, \
2872 }
2873struct clk tegra_list_clks[] = {
2874 PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
2875 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2876 PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
2877 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
2878 PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
2879 PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2880 PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
2881 PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
2882 PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2883 PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2884 PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2885 PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2886 PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2887 PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2888 PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
2889 PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
2890 PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2891 PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2892 PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2893 PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
2894 PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2895 PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2896 PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
2897 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2898 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2899 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2900 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2901 PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2902 PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2903 PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2904 PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2905 PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
2906 PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
2907 PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2908 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2909 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2910 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2911 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2912 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
2913 PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
2914 PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
2915 PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
2916 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2917 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
2918 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
2919 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2920 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
2921 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
2922 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2923 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2924 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2925 PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2926 PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
2927 PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2928 PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2929 PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2930 PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2931 PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
2932 PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
2933 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2934 PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
2935 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
2936 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
2937 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2938 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2939 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
2940 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2941 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2942 PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
2943 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
2944 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
2945 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2946 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
2947 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2948 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2949 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
2950 PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
2951 PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
2952 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
2953 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
2954 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
2955
2956 PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
2957 PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
2958 PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2959 PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2960 PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
2961 PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
2962 PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
2963 PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
2964 PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
2965};
2966
2967#define CLK_DUPLICATE(_name, _dev, _con) \
2968 { \
2969 .name = _name, \
2970 .lookup = { \
2971 .dev_id = _dev, \
2972 .con_id = _con, \
2973 }, \
2974 }
2975
2976/* Some clocks may be used by different drivers depending on the board
2977 * configuration. List those here to register them twice in the clock lookup
2978 * table under two names.
2979 */
2980struct clk_duplicate tegra_clk_duplicates[] = {
2981 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
2982 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
2983 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
2984 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
2985 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
2986 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
2987 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
2988 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
2989 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
2990 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
2991 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
2992 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
2993 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
2994 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
2995 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
2996 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
2997 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
2998 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
2999 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
3000 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
3001 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
3002 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
3003 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
3004 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
3005 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
3006 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
3007 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
3008 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
3009 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
3010 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
3011 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3012 CLK_DUPLICATE("twd", "smp_twd", NULL),
3013 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3014 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
3015 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
3016 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
3017 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
3018 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
3019 CLK_DUPLICATE("dam0", NULL, "dam0"),
3020 CLK_DUPLICATE("dam1", NULL, "dam1"),
3021 CLK_DUPLICATE("dam2", NULL, "dam2"),
3022 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
3023};
3024
3025struct clk *tegra_ptr_clks[] = {
3026 &tegra_clk_32k,
3027 &tegra_clk_m,
3028 &tegra_clk_m_div2,
3029 &tegra_clk_m_div4,
3030 &tegra_pll_ref,
3031 &tegra_pll_m,
3032 &tegra_pll_m_out1,
3033 &tegra_pll_c,
3034 &tegra_pll_c_out1,
3035 &tegra_pll_p,
3036 &tegra_pll_p_out1,
3037 &tegra_pll_p_out2,
3038 &tegra_pll_p_out3,
3039 &tegra_pll_p_out4,
3040 &tegra_pll_a,
3041 &tegra_pll_a_out0,
3042 &tegra_pll_d,
3043 &tegra_pll_d_out0,
3044 &tegra_pll_d2,
3045 &tegra_pll_d2_out0,
3046 &tegra_pll_u,
3047 &tegra_pll_x,
3048 &tegra_pll_x_out0,
3049 &tegra_pll_e,
3050 &tegra_clk_cclk_g,
3051 &tegra_cml0_clk,
3052 &tegra_cml1_clk,
3053 &tegra_pciex_clk,
3054 &tegra_clk_sclk,
3055 &tegra_clk_blink,
3056 &tegra30_clk_twd,
3057};
3058
3059
3060static void tegra30_init_one_clock(struct clk *c)
3061{ 2258{
3062 clk_init(c); 2259 writel(CPU_RESET(cpu),
3063 INIT_LIST_HEAD(&c->shared_bus_list); 2260 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
3064 if (!c->lookup.dev_id && !c->lookup.con_id) 2261 wmb();
3065 c->lookup.con_id = c->name;
3066 c->lookup.clk = c;
3067 clkdev_add(&c->lookup);
3068} 2262}
3069 2263
3070void __init tegra30_init_clocks(void) 2264static void tegra30_enable_cpu_clock(u32 cpu)
3071{ 2265{
3072 int i; 2266 unsigned int reg;
3073 struct clk *c;
3074 2267
3075 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) 2268 writel(CPU_CLOCK(cpu),
3076 tegra30_init_one_clock(tegra_ptr_clks[i]); 2269 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
3077 2270 reg = readl(reg_clk_base +
3078 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) 2271 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
3079 tegra30_init_one_clock(&tegra_list_clks[i]); 2272}
3080 2273
3081 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { 2274static void tegra30_disable_cpu_clock(u32 cpu)
3082 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); 2275{
3083 if (!c) {
3084 pr_err("%s: Unknown duplicate clock %s\n", __func__,
3085 tegra_clk_duplicates[i].name);
3086 continue;
3087 }
3088 2276
3089 tegra_clk_duplicates[i].lookup.clk = c; 2277 unsigned int reg;
3090 clkdev_add(&tegra_clk_duplicates[i].lookup);
3091 }
3092 2278
3093 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) 2279 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
3094 tegra30_init_one_clock(&tegra_sync_source_list[i]); 2280 writel(reg | CPU_CLOCK(cpu),
3095 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) 2281 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
3096 tegra30_init_one_clock(&tegra_clk_audio_list[i]); 2282}
3097 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
3098 tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
3099 2283
3100 init_clk_out_mux(); 2284static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
3101 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) 2285 .wait_for_reset = tegra30_wait_cpu_in_reset,
3102 tegra30_init_one_clock(&tegra_clk_out_list[i]); 2286 .put_in_reset = tegra30_put_cpu_in_reset,
2287 .out_of_reset = tegra30_cpu_out_of_reset,
2288 .enable_clock = tegra30_enable_cpu_clock,
2289 .disable_clock = tegra30_disable_cpu_clock,
2290};
3103 2291
2292void __init tegra30_cpu_car_ops_init(void)
2293{
2294 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
3104} 2295}