1 files changed, 96 insertions, 41 deletions

diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 7d2b5d03c1df..1a208dbf682f 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -24,19 +24,31 @@
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
 
+#include <mach/clk.h>
 #include <mach/iomap.h>
+#include <mach/powergate.h>
+
+#include "fuse.h"
+#include "flowctrl.h"
+#include "reset.h"
 
 extern void tegra_secondary_startup(void);
 
-static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 #define EVP_CPU_RESET_VECTOR \
         (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
 #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
+        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
 #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
         (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
+        (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
+
+#define CPU_CLOCK(cpu)  (0x1<<(8+cpu))
+#define CPU_RESET(cpu)  (0x1111ul<<(cpu))
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
@@ -47,63 +59,106 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
          */
         gic_secondary_init(0);
 
-        /*
-         * Synchronise with the boot thread.
-         */
-        spin_lock(&boot_lock);
-        spin_unlock(&boot_lock);
 }
 
-int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int tegra20_power_up_cpu(unsigned int cpu)
 {
-        unsigned long old_boot_vector;
-        unsigned long boot_vector;
-        unsigned long timeout;
         u32 reg;
 
-        /*
-         * set synchronisation state between this boot processor
-         * and the secondary one
-         */
-        spin_lock(&boot_lock);
+        /* Enable the CPU clock. */
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        barrier();
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
 
+        /* Clear flow controller CSR. */
+        flowctrl_write_cpu_csr(cpu, 0);
 
-        /* set the reset vector to point to the secondary_startup routine */
+        return 0;
+}
 
-        boot_vector = virt_to_phys(tegra_secondary_startup);
-        old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
-        writel(boot_vector, EVP_CPU_RESET_VECTOR);
+static int tegra30_power_up_cpu(unsigned int cpu)
+{
+        u32 reg;
+        int ret, pwrgateid;
+        unsigned long timeout;
 
-        /* enable cpu clock on cpu1 */
-        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
-        writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+        pwrgateid = tegra_cpu_powergate_id(cpu);
+        if (pwrgateid < 0)
+                return pwrgateid;
+
+        /* If this is the first boot, toggle powergates directly. */
+        if (!tegra_powergate_is_powered(pwrgateid)) {
+                ret = tegra_powergate_power_on(pwrgateid);
+                if (ret)
+                        return ret;
+
+                /* Wait for the power to come up. */
+                timeout = jiffies + 10*HZ;
+                while (tegra_powergate_is_powered(pwrgateid)) {
+                        if (time_after(jiffies, timeout))
+                                return -ETIMEDOUT;
+                        udelay(10);
+                }
+        }
 
-        reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
-        writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        /* CPU partition is powered. Enable the CPU clock. */
+        writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+        udelay(10);
 
-        smp_wmb();
-        flush_cache_all();
+        /* Remove I/O clamps. */
+        ret = tegra_powergate_remove_clamping(pwrgateid);
+        udelay(10);
 
-        /* unhalt the cpu */
-        writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
+        /* Clear flow controller CSR. */
+        flowctrl_write_cpu_csr(cpu, 0);
 
-        timeout = jiffies + (1 * HZ);
-        while (time_before(jiffies, timeout)) {
-                if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
-                        break;
-                udelay(10);
-        }
+        return 0;
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        int status;
 
-        /* put the old boot vector back */
-        writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when the
+         * flow controller state is cleared (which will cause the flow
+         * controller to stop driving reset if the CPU has been power-gated
+         * via the flow controller). This will have no effect on first boot
+         * of the CPU since it should already be in reset.
+         */
+        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+        dmb();
 
         /*
-         * now the secondary core is starting up let it run its
-         * calibrations, then wait for it to finish
+         * Unhalt the CPU. If the flow controller was used to power-gate the
+         * CPU this will cause the flow controller to stop driving reset.
+         * The CPU will remain in reset because the clock and reset block
+         * is now driving reset.
          */
-        spin_unlock(&boot_lock);
+        flowctrl_write_cpu_halt(cpu, 0);
+
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                status = tegra20_power_up_cpu(cpu);
+                break;
+        case TEGRA30:
+                status = tegra30_power_up_cpu(cpu);
+                break;
+        default:
+                status = -EINVAL;
+                break;
+        }
 
-        return 0;
+        if (status)
+                goto done;
+
+        /* Take the CPU out of reset. */
+        writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+        wmb();
+done:
+        return status;
 }
 
 /*
@@ -128,6 +183,6 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-
+        tegra_cpu_reset_handler_init();
         scu_enable(scu_base);
 }