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-rw-r--r--arch/arm/mach-tegra/pinmux.c354
1 files changed, 117 insertions, 237 deletions
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
index 13ae10237e84..f80d507671bc 100644
--- a/arch/arm/mach-tegra/pinmux.c
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -14,7 +14,8 @@
14 * 14 *
15 */ 15 */
16 16
17 17#include <linux/init.h>
18#include <linux/module.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/errno.h> 20#include <linux/errno.h>
20#include <linux/spinlock.h> 21#include <linux/spinlock.h>
@@ -23,21 +24,6 @@
23#include <mach/iomap.h> 24#include <mach/iomap.h>
24#include <mach/pinmux.h> 25#include <mach/pinmux.h>
25 26
26
27#define TEGRA_TRI_STATE(x) (0x14 + (4 * (x)))
28#define TEGRA_PP_MUX_CTL(x) (0x80 + (4 * (x)))
29#define TEGRA_PP_PU_PD(x) (0xa0 + (4 * (x)))
30
31#define REG_A 0
32#define REG_B 1
33#define REG_C 2
34#define REG_D 3
35#define REG_E 4
36#define REG_F 5
37#define REG_G 6
38
39#define REG_N -1
40
41#define HSM_EN(reg) (((reg) >> 2) & 0x1) 27#define HSM_EN(reg) (((reg) >> 2) & 0x1)
42#define SCHMT_EN(reg) (((reg) >> 3) & 0x1) 28#define SCHMT_EN(reg) (((reg) >> 3) & 0x1)
43#define LPMD(reg) (((reg) >> 4) & 0x3) 29#define LPMD(reg) (((reg) >> 4) & 0x3)
@@ -46,154 +32,8 @@
46#define SLWR(reg) (((reg) >> 28) & 0x3) 32#define SLWR(reg) (((reg) >> 28) & 0x3)
47#define SLWF(reg) (((reg) >> 30) & 0x3) 33#define SLWF(reg) (((reg) >> 30) & 0x3)
48 34
49struct tegra_pingroup_desc { 35static const struct tegra_pingroup_desc *const pingroups = tegra_soc_pingroups;
50 const char *name; 36static const struct tegra_drive_pingroup_desc *const drive_pingroups = tegra_soc_drive_pingroups;
51 int funcs[4];
52 s8 tri_reg; /* offset into the TRISTATE_REG_* register bank */
53 s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
54 s8 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
55 s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
56 s8 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
57 s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
58};
59
60#define PINGROUP(pg_name, f0, f1, f2, f3, \
61 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b) \
62 [TEGRA_PINGROUP_ ## pg_name] = { \
63 .name = #pg_name, \
64 .funcs = { \
65 TEGRA_MUX_ ## f0, \
66 TEGRA_MUX_ ## f1, \
67 TEGRA_MUX_ ## f2, \
68 TEGRA_MUX_ ## f3, \
69 }, \
70 .tri_reg = REG_ ## tri_r, \
71 .tri_bit = tri_b, \
72 .mux_reg = REG_ ## mux_r, \
73 .mux_bit = mux_b, \
74 .pupd_reg = REG_ ## pupd_r, \
75 .pupd_bit = pupd_b, \
76 }
77
78static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = {
79 PINGROUP(ATA, IDE, NAND, GMI, RSVD, A, 0, A, 24, A, 0),
80 PINGROUP(ATB, IDE, NAND, GMI, SDIO4, A, 1, A, 16, A, 2),
81 PINGROUP(ATC, IDE, NAND, GMI, SDIO4, A, 2, A, 22, A, 4),
82 PINGROUP(ATD, IDE, NAND, GMI, SDIO4, A, 3, A, 20, A, 6),
83 PINGROUP(ATE, IDE, NAND, GMI, RSVD, B, 25, A, 12, A, 8),
84 PINGROUP(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, A, 4, C, 2, C, 0),
85 PINGROUP(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, A, 5, C, 4, C, 2),
86 PINGROUP(CRTP, CRT, RSVD, RSVD, RSVD, D, 14, G, 20, B, 24),
87 PINGROUP(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6, C, 6, D, 24),
88 PINGROUP(DAP1, DAP1, RSVD, GMI, SDIO2, A, 7, C, 20, A, 10),
89 PINGROUP(DAP2, DAP2, TWC, RSVD, GMI, A, 8, C, 22, A, 12),
90 PINGROUP(DAP3, DAP3, RSVD, RSVD, RSVD, A, 9, C, 24, A, 14),
91 PINGROUP(DAP4, DAP4, RSVD, GMI, RSVD, A, 10, C, 26, A, 16),
92 PINGROUP(DDC, I2C2, RSVD, RSVD, RSVD, B, 31, C, 0, E, 28),
93 PINGROUP(DTA, RSVD, SDIO2, VI, RSVD, A, 11, B, 20, A, 18),
94 PINGROUP(DTB, RSVD, RSVD, VI, SPI1, A, 12, B, 22, A, 20),
95 PINGROUP(DTC, RSVD, RSVD, VI, RSVD, A, 13, B, 26, A, 22),
96 PINGROUP(DTD, RSVD, SDIO2, VI, RSVD, A, 14, B, 28, A, 24),
97 PINGROUP(DTE, RSVD, RSVD, VI, SPI1, A, 15, B, 30, A, 26),
98 PINGROUP(DTF, I2C3, RSVD, VI, RSVD, D, 12, G, 30, A, 28),
99 PINGROUP(GMA, UARTE, SPI3, GMI, SDIO4, A, 28, B, 0, E, 20),
100 PINGROUP(GMB, IDE, NAND, GMI, GMI_INT, B, 29, C, 28, E, 22),
101 PINGROUP(GMC, UARTD, SPI4, GMI, SFLASH, A, 29, B, 2, E, 24),
102 PINGROUP(GMD, RSVD, NAND, GMI, SFLASH, B, 30, C, 30, E, 26),
103 PINGROUP(GME, RSVD, DAP5, GMI, SDIO4, B, 0, D, 0, C, 24),
104 PINGROUP(GPU, PWM, UARTA, GMI, RSVD, A, 16, D, 4, B, 20),
105 PINGROUP(GPU7, RTCK, RSVD, RSVD, RSVD, D, 11, G, 28, B, 6),
106 PINGROUP(GPV, PCIE, RSVD, RSVD, RSVD, A, 17, D, 2, A, 30),
107 PINGROUP(HDINT, HDMI, RSVD, RSVD, RSVD, C, 23, B, 4, D, 22),
108 PINGROUP(I2CP, I2C, RSVD, RSVD, RSVD, A, 18, C, 8, B, 2),
109 PINGROUP(IRRX, UARTA, UARTB, GMI, SPI4, A, 20, C, 18, C, 22),
110 PINGROUP(IRTX, UARTA, UARTB, GMI, SPI4, A, 19, C, 16, C, 20),
111 PINGROUP(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL, A, 22, C, 10, B, 8),
112 PINGROUP(KBCB, KBC, NAND, SDIO2, MIO, A, 21, C, 12, B, 10),
113 PINGROUP(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL, B, 26, C, 14, B, 12),
114 PINGROUP(KBCD, KBC, NAND, SDIO2, MIO, D, 10, G, 26, B, 14),
115 PINGROUP(KBCE, KBC, NAND, OWR, RSVD, A, 26, A, 28, E, 2),
116 PINGROUP(KBCF, KBC, NAND, TRACE, MIO, A, 27, A, 26, E, 0),
117 PINGROUP(LCSN, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 31, E, 12, D, 20),
118 PINGROUP(LD0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 0, F, 0, D, 12),
119 PINGROUP(LD1, DISPLAYA, DISPLAYB, XIO, RSVD, C, 1, F, 2, D, 12),
120 PINGROUP(LD10, DISPLAYA, DISPLAYB, XIO, RSVD, C, 10, F, 20, D, 12),
121 PINGROUP(LD11, DISPLAYA, DISPLAYB, XIO, RSVD, C, 11, F, 22, D, 12),
122 PINGROUP(LD12, DISPLAYA, DISPLAYB, XIO, RSVD, C, 12, F, 24, D, 12),
123 PINGROUP(LD13, DISPLAYA, DISPLAYB, XIO, RSVD, C, 13, F, 26, D, 12),
124 PINGROUP(LD14, DISPLAYA, DISPLAYB, XIO, RSVD, C, 14, F, 28, D, 12),
125 PINGROUP(LD15, DISPLAYA, DISPLAYB, XIO, RSVD, C, 15, F, 30, D, 12),
126 PINGROUP(LD16, DISPLAYA, DISPLAYB, XIO, RSVD, C, 16, G, 0, D, 12),
127 PINGROUP(LD17, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 17, G, 2, D, 12),
128 PINGROUP(LD2, DISPLAYA, DISPLAYB, XIO, RSVD, C, 2, F, 4, D, 12),
129 PINGROUP(LD3, DISPLAYA, DISPLAYB, XIO, RSVD, C, 3, F, 6, D, 12),
130 PINGROUP(LD4, DISPLAYA, DISPLAYB, XIO, RSVD, C, 4, F, 8, D, 12),
131 PINGROUP(LD5, DISPLAYA, DISPLAYB, XIO, RSVD, C, 5, F, 10, D, 12),
132 PINGROUP(LD6, DISPLAYA, DISPLAYB, XIO, RSVD, C, 6, F, 12, D, 12),
133 PINGROUP(LD7, DISPLAYA, DISPLAYB, XIO, RSVD, C, 7, F, 14, D, 12),
134 PINGROUP(LD8, DISPLAYA, DISPLAYB, XIO, RSVD, C, 8, F, 16, D, 12),
135 PINGROUP(LD9, DISPLAYA, DISPLAYB, XIO, RSVD, C, 9, F, 18, D, 12),
136 PINGROUP(LDC, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 30, E, 14, D, 20),
137 PINGROUP(LDI, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 6, G, 16, D, 18),
138 PINGROUP(LHP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 18, G, 10, D, 16),
139 PINGROUP(LHP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 19, G, 4, D, 14),
140 PINGROUP(LHP2, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 20, G, 6, D, 14),
141 PINGROUP(LHS, DISPLAYA, DISPLAYB, XIO, RSVD, D, 7, E, 22, D, 22),
142 PINGROUP(LM0, DISPLAYA, DISPLAYB, SPI3, RSVD, C, 24, E, 26, D, 22),
143 PINGROUP(LM1, DISPLAYA, DISPLAYB, RSVD, CRT, C, 25, E, 28, D, 22),
144 PINGROUP(LPP, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 8, G, 14, D, 18),
145 PINGROUP(LPW0, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 3, E, 0, D, 20),
146 PINGROUP(LPW1, DISPLAYA, DISPLAYB, RSVD, RSVD, D, 4, E, 2, D, 20),
147 PINGROUP(LPW2, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 5, E, 4, D, 20),
148 PINGROUP(LSC0, DISPLAYA, DISPLAYB, XIO, RSVD, C, 27, E, 18, D, 22),
149 PINGROUP(LSC1, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 28, E, 20, D, 20),
150 PINGROUP(LSCK, DISPLAYA, DISPLAYB, SPI3, HDMI, C, 29, E, 16, D, 20),
151 PINGROUP(LSDA, DISPLAYA, DISPLAYB, SPI3, HDMI, D, 1, E, 8, D, 20),
152 PINGROUP(LSDI, DISPLAYA, DISPLAYB, SPI3, RSVD, D, 2, E, 6, D, 20),
153 PINGROUP(LSPI, DISPLAYA, DISPLAYB, XIO, HDMI, D, 0, E, 10, D, 22),
154 PINGROUP(LVP0, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 21, E, 30, D, 22),
155 PINGROUP(LVP1, DISPLAYA, DISPLAYB, RSVD, RSVD, C, 22, G, 8, D, 16),
156 PINGROUP(LVS, DISPLAYA, DISPLAYB, XIO, RSVD, C, 26, E, 24, D, 22),
157 PINGROUP(OWC, OWR, RSVD, RSVD, RSVD, A, 31, B, 8, E, 30),
158 PINGROUP(PMC, PWR_ON, PWR_INTR, RSVD, RSVD, A, 23, G, 18, N, -1),
159 PINGROUP(PTA, I2C2, HDMI, GMI, RSVD, A, 24, G, 22, B, 4),
160 PINGROUP(RM, I2C, RSVD, RSVD, RSVD, A, 25, A, 14, B, 0),
161 PINGROUP(SDB, UARTA, PWM, SDIO3, SPI2, D, 15, D, 10, N, -1),
162 PINGROUP(SDC, PWM, TWC, SDIO3, SPI3, B, 1, D, 12, D, 28),
163 PINGROUP(SDD, UARTA, PWM, SDIO3, SPI3, B, 2, D, 14, D, 30),
164 PINGROUP(SDIO1, SDIO1, RSVD, UARTE, UARTA, A, 30, A, 30, E, 18),
165 PINGROUP(SLXA, PCIE, SPI4, SDIO3, SPI2, B, 3, B, 6, B, 22),
166 PINGROUP(SLXC, SPDIF, SPI4, SDIO3, SPI2, B, 5, B, 10, B, 26),
167 PINGROUP(SLXD, SPDIF, SPI4, SDIO3, SPI2, B, 6, B, 12, B, 28),
168 PINGROUP(SLXK, PCIE, SPI4, SDIO3, SPI2, B, 7, B, 14, B, 30),
169 PINGROUP(SPDI, SPDIF, RSVD, I2C, SDIO2, B, 8, D, 8, B, 16),
170 PINGROUP(SPDO, SPDIF, RSVD, I2C, SDIO2, B, 9, D, 6, B, 18),
171 PINGROUP(SPIA, SPI1, SPI2, SPI3, GMI, B, 10, D, 30, C, 4),
172 PINGROUP(SPIB, SPI1, SPI2, SPI3, GMI, B, 11, D, 28, C, 6),
173 PINGROUP(SPIC, SPI1, SPI2, SPI3, GMI, B, 12, D, 26, C, 8),
174 PINGROUP(SPID, SPI2, SPI1, SPI2_ALT, GMI, B, 13, D, 24, C, 10),
175 PINGROUP(SPIE, SPI2, SPI1, SPI2_ALT, GMI, B, 14, D, 22, C, 12),
176 PINGROUP(SPIF, SPI3, SPI1, SPI2, RSVD, B, 15, D, 20, C, 14),
177 PINGROUP(SPIG, SPI3, SPI2, SPI2_ALT, I2C, B, 16, D, 18, C, 16),
178 PINGROUP(SPIH, SPI3, SPI2, SPI2_ALT, I2C, B, 17, D, 16, C, 18),
179 PINGROUP(UAA, SPI3, MIPI_HS, UARTA, ULPI, B, 18, A, 0, D, 0),
180 PINGROUP(UAB, SPI2, MIPI_HS, UARTA, ULPI, B, 19, A, 2, D, 2),
181 PINGROUP(UAC, OWR, RSVD, RSVD, RSVD, B, 20, A, 4, D, 4),
182 PINGROUP(UAD, IRDA, SPDIF, UARTA, SPI4, B, 21, A, 6, D, 6),
183 PINGROUP(UCA, UARTC, RSVD, GMI, RSVD, B, 22, B, 16, D, 8),
184 PINGROUP(UCB, UARTC, PWM, GMI, RSVD, B, 23, B, 18, D, 10),
185 PINGROUP(UDA, SPI1, RSVD, UARTD, ULPI, D, 13, A, 8, E, 16),
186 /* these pin groups only have pullup and pull down control */
187 PINGROUP(CK32, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 14),
188 PINGROUP(DDRC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, D, 26),
189 PINGROUP(PMCA, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 4),
190 PINGROUP(PMCB, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 6),
191 PINGROUP(PMCC, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 8),
192 PINGROUP(PMCD, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 10),
193 PINGROUP(PMCE, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, E, 12),
194 PINGROUP(XM2C, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 30),
195 PINGROUP(XM2D, RSVD, RSVD, RSVD, RSVD, N, -1, N, -1, C, 28),
196};
197 37
198static char *tegra_mux_names[TEGRA_MAX_MUX] = { 38static char *tegra_mux_names[TEGRA_MAX_MUX] = {
199 [TEGRA_MUX_AHB_CLK] = "AHB_CLK", 39 [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
@@ -256,48 +96,7 @@ static char *tegra_mux_names[TEGRA_MAX_MUX] = {
256 [TEGRA_MUX_VI] = "VI", 96 [TEGRA_MUX_VI] = "VI",
257 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK", 97 [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
258 [TEGRA_MUX_XIO] = "XIO", 98 [TEGRA_MUX_XIO] = "XIO",
259}; 99 [TEGRA_MUX_SAFE] = "<safe>",
260
261struct tegra_drive_pingroup_desc {
262 const char *name;
263 s16 reg;
264};
265
266#define DRIVE_PINGROUP(pg_name, r) \
267 [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \
268 .name = #pg_name, \
269 .reg = r \
270 }
271
272static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = {
273 DRIVE_PINGROUP(AO1, 0x868),
274 DRIVE_PINGROUP(AO2, 0x86c),
275 DRIVE_PINGROUP(AT1, 0x870),
276 DRIVE_PINGROUP(AT2, 0x874),
277 DRIVE_PINGROUP(CDEV1, 0x878),
278 DRIVE_PINGROUP(CDEV2, 0x87c),
279 DRIVE_PINGROUP(CSUS, 0x880),
280 DRIVE_PINGROUP(DAP1, 0x884),
281 DRIVE_PINGROUP(DAP2, 0x888),
282 DRIVE_PINGROUP(DAP3, 0x88c),
283 DRIVE_PINGROUP(DAP4, 0x890),
284 DRIVE_PINGROUP(DBG, 0x894),
285 DRIVE_PINGROUP(LCD1, 0x898),
286 DRIVE_PINGROUP(LCD2, 0x89c),
287 DRIVE_PINGROUP(SDMMC2, 0x8a0),
288 DRIVE_PINGROUP(SDMMC3, 0x8a4),
289 DRIVE_PINGROUP(SPI, 0x8a8),
290 DRIVE_PINGROUP(UAA, 0x8ac),
291 DRIVE_PINGROUP(UAB, 0x8b0),
292 DRIVE_PINGROUP(UART2, 0x8b4),
293 DRIVE_PINGROUP(UART3, 0x8b8),
294 DRIVE_PINGROUP(VI1, 0x8bc),
295 DRIVE_PINGROUP(VI2, 0x8c0),
296 DRIVE_PINGROUP(XM2A, 0x8c4),
297 DRIVE_PINGROUP(XM2C, 0x8c8),
298 DRIVE_PINGROUP(XM2D, 0x8cc),
299 DRIVE_PINGROUP(XM2CLK, 0x8d0),
300 DRIVE_PINGROUP(MEMCOMP, 0x8d4),
301}; 100};
302 101
303static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = { 102static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
@@ -381,22 +180,27 @@ static inline void pg_writel(unsigned long value, unsigned long offset)
381 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); 180 writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
382} 181}
383 182
384int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func) 183static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
385{ 184{
386 int mux = -1; 185 int mux = -1;
387 int i; 186 int i;
388 unsigned long reg; 187 unsigned long reg;
389 unsigned long flags; 188 unsigned long flags;
189 enum tegra_pingroup pg = config->pingroup;
190 enum tegra_mux_func func = config->func;
390 191
391 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 192 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
392 return -ERANGE; 193 return -ERANGE;
393 194
394 if (pingroups[pg].mux_reg == REG_N) 195 if (pingroups[pg].mux_reg < 0)
395 return -EINVAL; 196 return -EINVAL;
396 197
397 if (func < 0) 198 if (func < 0)
398 return -ERANGE; 199 return -ERANGE;
399 200
201 if (func == TEGRA_MUX_SAFE)
202 func = pingroups[pg].func_safe;
203
400 if (func & TEGRA_MUX_RSVD) { 204 if (func & TEGRA_MUX_RSVD) {
401 mux = func & 0x3; 205 mux = func & 0x3;
402 } else { 206 } else {
@@ -413,10 +217,10 @@ int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
413 217
414 spin_lock_irqsave(&mux_lock, flags); 218 spin_lock_irqsave(&mux_lock, flags);
415 219
416 reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); 220 reg = pg_readl(pingroups[pg].mux_reg);
417 reg &= ~(0x3 << pingroups[pg].mux_bit); 221 reg &= ~(0x3 << pingroups[pg].mux_bit);
418 reg |= mux << pingroups[pg].mux_bit; 222 reg |= mux << pingroups[pg].mux_bit;
419 pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg)); 223 pg_writel(reg, pingroups[pg].mux_reg);
420 224
421 spin_unlock_irqrestore(&mux_lock, flags); 225 spin_unlock_irqrestore(&mux_lock, flags);
422 226
@@ -432,16 +236,16 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
432 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 236 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
433 return -ERANGE; 237 return -ERANGE;
434 238
435 if (pingroups[pg].tri_reg == REG_N) 239 if (pingroups[pg].tri_reg < 0)
436 return -EINVAL; 240 return -EINVAL;
437 241
438 spin_lock_irqsave(&mux_lock, flags); 242 spin_lock_irqsave(&mux_lock, flags);
439 243
440 reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg)); 244 reg = pg_readl(pingroups[pg].tri_reg);
441 reg &= ~(0x1 << pingroups[pg].tri_bit); 245 reg &= ~(0x1 << pingroups[pg].tri_bit);
442 if (tristate) 246 if (tristate)
443 reg |= 1 << pingroups[pg].tri_bit; 247 reg |= 1 << pingroups[pg].tri_bit;
444 pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg)); 248 pg_writel(reg, pingroups[pg].tri_reg);
445 249
446 spin_unlock_irqrestore(&mux_lock, flags); 250 spin_unlock_irqrestore(&mux_lock, flags);
447 251
@@ -457,7 +261,7 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
457 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP) 261 if (pg < 0 || pg >= TEGRA_MAX_PINGROUP)
458 return -ERANGE; 262 return -ERANGE;
459 263
460 if (pingroups[pg].pupd_reg == REG_N) 264 if (pingroups[pg].pupd_reg < 0)
461 return -EINVAL; 265 return -EINVAL;
462 266
463 if (pupd != TEGRA_PUPD_NORMAL && 267 if (pupd != TEGRA_PUPD_NORMAL &&
@@ -468,38 +272,39 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
468 272
469 spin_lock_irqsave(&mux_lock, flags); 273 spin_lock_irqsave(&mux_lock, flags);
470 274
471 reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); 275 reg = pg_readl(pingroups[pg].pupd_reg);
472 reg &= ~(0x3 << pingroups[pg].pupd_bit); 276 reg &= ~(0x3 << pingroups[pg].pupd_bit);
473 reg |= pupd << pingroups[pg].pupd_bit; 277 reg |= pupd << pingroups[pg].pupd_bit;
474 pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg)); 278 pg_writel(reg, pingroups[pg].pupd_reg);
475 279
476 spin_unlock_irqrestore(&mux_lock, flags); 280 spin_unlock_irqrestore(&mux_lock, flags);
477 281
478 return 0; 282 return 0;
479} 283}
480 284
481void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup, 285static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
482 enum tegra_mux_func func,
483 enum tegra_pullupdown pupd,
484 enum tegra_tristate tristate)
485{ 286{
287 enum tegra_pingroup pingroup = config->pingroup;
288 enum tegra_mux_func func = config->func;
289 enum tegra_pullupdown pupd = config->pupd;
290 enum tegra_tristate tristate = config->tristate;
486 int err; 291 int err;
487 292
488 if (pingroups[pingroup].mux_reg != REG_N) { 293 if (pingroups[pingroup].mux_reg >= 0) {
489 err = tegra_pinmux_set_func(pingroup, func); 294 err = tegra_pinmux_set_func(config);
490 if (err < 0) 295 if (err < 0)
491 pr_err("pinmux: can't set pingroup %s func to %s: %d\n", 296 pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
492 pingroup_name(pingroup), func_name(func), err); 297 pingroup_name(pingroup), func_name(func), err);
493 } 298 }
494 299
495 if (pingroups[pingroup].pupd_reg != REG_N) { 300 if (pingroups[pingroup].pupd_reg >= 0) {
496 err = tegra_pinmux_set_pullupdown(pingroup, pupd); 301 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
497 if (err < 0) 302 if (err < 0)
498 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n", 303 pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
499 pingroup_name(pingroup), pupd_name(pupd), err); 304 pingroup_name(pingroup), pupd_name(pupd), err);
500 } 305 }
501 306
502 if (pingroups[pingroup].tri_reg != REG_N) { 307 if (pingroups[pingroup].tri_reg >= 0) {
503 err = tegra_pinmux_set_tristate(pingroup, tristate); 308 err = tegra_pinmux_set_tristate(pingroup, tristate);
504 if (err < 0) 309 if (err < 0)
505 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n", 310 pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
@@ -507,17 +312,12 @@ void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
507 } 312 }
508} 313}
509 314
510 315void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
511
512void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len)
513{ 316{
514 int i; 317 int i;
515 318
516 for (i = 0; i < len; i++) 319 for (i = 0; i < len; i++)
517 tegra_pinmux_config_pingroup(config[i].pingroup, 320 tegra_pinmux_config_pingroup(&config[i]);
518 config[i].func,
519 config[i].pupd,
520 config[i].tristate);
521} 321}
522 322
523static const char *drive_pinmux_name(enum tegra_drive_pingroup pg) 323static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
@@ -784,6 +584,86 @@ void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
784 config[i].slew_falling); 584 config[i].slew_falling);
785} 585}
786 586
587void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
588 int len)
589{
590 int i;
591 struct tegra_pingroup_config c;
592
593 for (i = 0; i < len; i++) {
594 int err;
595 c = config[i];
596 if (c.pingroup < 0 || c.pingroup >= TEGRA_MAX_PINGROUP) {
597 WARN_ON(1);
598 continue;
599 }
600 c.func = pingroups[c.pingroup].func_safe;
601 err = tegra_pinmux_set_func(&c);
602 if (err < 0)
603 pr_err("%s: tegra_pinmux_set_func returned %d setting "
604 "%s to %s\n", __func__, err,
605 pingroup_name(c.pingroup), func_name(c.func));
606 }
607}
608
609void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
610 int len)
611{
612 int i;
613
614 for (i = 0; i < len; i++) {
615 int err;
616 if (config[i].pingroup < 0 ||
617 config[i].pingroup >= TEGRA_MAX_PINGROUP) {
618 WARN_ON(1);
619 continue;
620 }
621 err = tegra_pinmux_set_func(&config[i]);
622 if (err < 0)
623 pr_err("%s: tegra_pinmux_set_func returned %d setting "
624 "%s to %s\n", __func__, err,
625 pingroup_name(config[i].pingroup),
626 func_name(config[i].func));
627 }
628}
629
630void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
631 int len, enum tegra_tristate tristate)
632{
633 int i;
634 int err;
635 enum tegra_pingroup pingroup;
636
637 for (i = 0; i < len; i++) {
638 pingroup = config[i].pingroup;
639 if (pingroups[pingroup].tri_reg >= 0) {
640 err = tegra_pinmux_set_tristate(pingroup, tristate);
641 if (err < 0)
642 pr_err("pinmux: can't set pingroup %s tristate"
643 " to %s: %d\n", pingroup_name(pingroup),
644 tri_name(tristate), err);
645 }
646 }
647}
648
649void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
650 int len, enum tegra_pullupdown pupd)
651{
652 int i;
653 int err;
654 enum tegra_pingroup pingroup;
655
656 for (i = 0; i < len; i++) {
657 pingroup = config[i].pingroup;
658 if (pingroups[pingroup].pupd_reg >= 0) {
659 err = tegra_pinmux_set_pullupdown(pingroup, pupd);
660 if (err < 0)
661 pr_err("pinmux: can't set pingroup %s pullupdown"
662 " to %s: %d\n", pingroup_name(pingroup),
663 pupd_name(pupd), err);
664 }
665 }
666}
787 667
788#ifdef CONFIG_DEBUG_FS 668#ifdef CONFIG_DEBUG_FS
789 669
@@ -812,11 +692,11 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
812 len = strlen(pingroups[i].name); 692 len = strlen(pingroups[i].name);
813 dbg_pad_field(s, 5 - len); 693 dbg_pad_field(s, 5 - len);
814 694
815 if (pingroups[i].mux_reg == REG_N) { 695 if (pingroups[i].mux_reg < 0) {
816 seq_printf(s, "TEGRA_MUX_NONE"); 696 seq_printf(s, "TEGRA_MUX_NONE");
817 len = strlen("NONE"); 697 len = strlen("NONE");
818 } else { 698 } else {
819 mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >> 699 mux = (pg_readl(pingroups[i].mux_reg) >>
820 pingroups[i].mux_bit) & 0x3; 700 pingroups[i].mux_bit) & 0x3;
821 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { 701 if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
822 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); 702 seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
@@ -829,21 +709,21 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused)
829 } 709 }
830 dbg_pad_field(s, 13-len); 710 dbg_pad_field(s, 13-len);
831 711
832 if (pingroups[i].mux_reg == REG_N) { 712 if (pingroups[i].pupd_reg < 0) {
833 seq_printf(s, "TEGRA_PUPD_NORMAL"); 713 seq_printf(s, "TEGRA_PUPD_NORMAL");
834 len = strlen("NORMAL"); 714 len = strlen("NORMAL");
835 } else { 715 } else {
836 pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >> 716 pupd = (pg_readl(pingroups[i].pupd_reg) >>
837 pingroups[i].pupd_bit) & 0x3; 717 pingroups[i].pupd_bit) & 0x3;
838 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); 718 seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
839 len = strlen(pupd_name(pupd)); 719 len = strlen(pupd_name(pupd));
840 } 720 }
841 dbg_pad_field(s, 9 - len); 721 dbg_pad_field(s, 9 - len);
842 722
843 if (pingroups[i].tri_reg == REG_N) { 723 if (pingroups[i].tri_reg < 0) {
844 seq_printf(s, "TEGRA_TRI_NORMAL"); 724 seq_printf(s, "TEGRA_TRI_NORMAL");
845 } else { 725 } else {
846 tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >> 726 tri = (pg_readl(pingroups[i].tri_reg) >>
847 pingroups[i].tri_bit) & 0x1; 727 pingroups[i].tri_bit) & 0x1;
848 728
849 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); 729 seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 23:34:50 -0500