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Diffstat (limited to 'arch/arm/mach-tegra/pcie.c')
-rw-r--r--arch/arm/mach-tegra/pcie.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab5d8f0..54a816ff3847 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
585 afi_writel(0, AFI_MSI_BAR_SZ); 585 afi_writel(0, AFI_MSI_BAR_SZ);
586} 586}
587 587
588static void tegra_pcie_enable_controller(void) 588static int tegra_pcie_enable_controller(void)
589{ 589{
590 u32 val, reg; 590 u32 val, reg;
591 int i; 591 int i, timeout;
592 592
593 /* Enable slot clock and pulse the reset signals */ 593 /* Enable slot clock and pulse the reset signals */
594 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) { 594 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
639 pads_writel(0xfa5cfa5c, 0xc8); 639 pads_writel(0xfa5cfa5c, 0xc8);
640 640
641 /* Wait for the PLL to lock */ 641 /* Wait for the PLL to lock */
642 timeout = 300;
642 do { 643 do {
643 val = pads_readl(PADS_PLL_CTL); 644 val = pads_readl(PADS_PLL_CTL);
645 usleep_range(1000, 1000);
646 if (--timeout == 0) {
647 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
648 return -EBUSY;
649 }
644 } while (!(val & PADS_PLL_CTL_LOCKDET)); 650 } while (!(val & PADS_PLL_CTL_LOCKDET));
645 651
646 /* turn off IDDQ override */ 652 /* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
671 /* Disable all execptions */ 677 /* Disable all execptions */
672 afi_writel(0, AFI_FPCI_ERROR_MASKS); 678 afi_writel(0, AFI_FPCI_ERROR_MASKS);
673 679
674 return; 680 return 0;
675} 681}
676 682
677static void tegra_pcie_xclk_clamp(bool clamp) 683static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
921 if (err) 927 if (err)
922 return err; 928 return err;
923 929
924 tegra_pcie_enable_controller(); 930 err = tegra_pcie_enable_controller();
931 if (err)
932 return err;
925 933
926 /* setup the AFI address translations */ 934 /* setup the AFI address translations */
927 tegra_pcie_setup_translations(); 935 tegra_pcie_setup_translations();