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-rw-r--r--arch/arm/mach-tegra/irq.c174
1 files changed, 74 insertions, 100 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d8995b27..4956c3cea731 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 2010 Google, Inc. 2 * Copyright (C) 2011 Google, Inc.
3 * 3 *
4 * Author: 4 * Author:
5 * Colin Cross <ccross@google.com> 5 * Colin Cross <ccross@android.com>
6 * 6 *
7 * Copyright (C) 2010, NVIDIA Corporation 7 * Copyright (C) 2010, NVIDIA Corporation
8 * 8 *
@@ -18,8 +18,6 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/interrupt.h> 21#include <linux/interrupt.h>
24#include <linux/irq.h> 22#include <linux/irq.h>
25#include <linux/io.h> 23#include <linux/io.h>
@@ -27,134 +25,110 @@
27#include <asm/hardware/gic.h> 25#include <asm/hardware/gic.h>
28 26
29#include <mach/iomap.h> 27#include <mach/iomap.h>
30#include <mach/legacy_irq.h>
31#include <mach/suspend.h>
32 28
33#include "board.h" 29#include "board.h"
34 30
35#define PMC_CTRL 0x0 31#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
36#define PMC_CTRL_LATCH_WAKEUPS (1 << 5) 32#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
37#define PMC_WAKE_MASK 0xc 33#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
38#define PMC_WAKE_LEVEL 0x10 34
39#define PMC_WAKE_STATUS 0x14 35#define ICTLR_CPU_IEP_VFIQ 0x08
40#define PMC_SW_WAKE_STATUS 0x18 36#define ICTLR_CPU_IEP_FIR 0x14
41#define PMC_DPD_SAMPLE 0x20 37#define ICTLR_CPU_IEP_FIR_SET 0x18
38#define ICTLR_CPU_IEP_FIR_CLR 0x1c
39
40#define ICTLR_CPU_IER 0x20
41#define ICTLR_CPU_IER_SET 0x24
42#define ICTLR_CPU_IER_CLR 0x28
43#define ICTLR_CPU_IEP_CLASS 0x2C
44
45#define ICTLR_COP_IER 0x30
46#define ICTLR_COP_IER_SET 0x34
47#define ICTLR_COP_IER_CLR 0x38
48#define ICTLR_COP_IEP_CLASS 0x3c
49
50#define NUM_ICTLRS 4
51#define FIRST_LEGACY_IRQ 32
52
53static void __iomem *ictlr_reg_base[] = {
54 IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
55 IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
56 IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
57 IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
58};
42 59
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); 60static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
61{
62 void __iomem *base;
63 u32 mask;
44 64
45static u32 tegra_lp0_wake_enb; 65 BUG_ON(irq < FIRST_LEGACY_IRQ ||
46static u32 tegra_lp0_wake_level; 66 irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
47static u32 tegra_lp0_wake_level_any;
48 67
49static void (*tegra_gic_mask_irq)(struct irq_data *d); 68 base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
50static void (*tegra_gic_unmask_irq)(struct irq_data *d); 69 mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
51static void (*tegra_gic_ack_irq)(struct irq_data *d);
52 70
53/* ensures that sufficient time is passed for a register write to 71 __raw_writel(mask, base + reg);
54 * serialize into the 32KHz domain */
55static void pmc_32kwritel(u32 val, unsigned long offs)
56{
57 writel(val, pmc + offs);
58 udelay(130);
59} 72}
60 73
61int tegra_set_lp1_wake(int irq, int enable) 74static void tegra_mask(struct irq_data *d)
62{ 75{
63 return tegra_legacy_irq_set_wake(irq, enable); 76 if (d->irq < FIRST_LEGACY_IRQ)
77 return;
78
79 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
64} 80}
65 81
66void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any) 82static void tegra_unmask(struct irq_data *d)
67{ 83{
68 u32 temp; 84 if (d->irq < FIRST_LEGACY_IRQ)
69 u32 status; 85 return;
70 u32 lvl;
71
72 wake_level &= wake_enb;
73 wake_any &= wake_enb;
74 86
75 wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb); 87 tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
76 wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
77
78 wake_enb |= tegra_lp0_wake_enb;
79
80 pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
81 temp = readl(pmc + PMC_CTRL);
82 temp |= PMC_CTRL_LATCH_WAKEUPS;
83 pmc_32kwritel(temp, PMC_CTRL);
84 temp &= ~PMC_CTRL_LATCH_WAKEUPS;
85 pmc_32kwritel(temp, PMC_CTRL);
86 status = readl(pmc + PMC_SW_WAKE_STATUS);
87 lvl = readl(pmc + PMC_WAKE_LEVEL);
88
89 /* flip the wakeup trigger for any-edge triggered pads
90 * which are currently asserting as wakeups */
91 lvl ^= status;
92 lvl &= wake_any;
93
94 wake_level |= lvl;
95
96 writel(wake_level, pmc + PMC_WAKE_LEVEL);
97 /* Enable DPD sample to trigger sampling pads data and direction
98 * in which pad will be driven during lp0 mode*/
99 writel(0x1, pmc + PMC_DPD_SAMPLE);
100
101 writel(wake_enb, pmc + PMC_WAKE_MASK);
102} 88}
103 89
104static void tegra_mask(struct irq_data *d) 90static void tegra_ack(struct irq_data *d)
105{ 91{
106 tegra_gic_mask_irq(d); 92 if (d->irq < FIRST_LEGACY_IRQ)
107 tegra_legacy_mask_irq(d->irq); 93 return;
108}
109 94
110static void tegra_unmask(struct irq_data *d) 95 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
111{
112 tegra_gic_unmask_irq(d);
113 tegra_legacy_unmask_irq(d->irq);
114} 96}
115 97
116static void tegra_ack(struct irq_data *d) 98static void tegra_eoi(struct irq_data *d)
117{ 99{
118 tegra_legacy_force_irq_clr(d->irq); 100 if (d->irq < FIRST_LEGACY_IRQ)
119 tegra_gic_ack_irq(d); 101 return;
102
103 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
120} 104}
121 105
122static int tegra_retrigger(struct irq_data *d) 106static int tegra_retrigger(struct irq_data *d)
123{ 107{
124 tegra_legacy_force_irq_set(d->irq); 108 if (d->irq < FIRST_LEGACY_IRQ)
109 return 0;
110
111 tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
112
125 return 1; 113 return 1;
126} 114}
127 115
128static struct irq_chip tegra_irq = {
129 .name = "PPI",
130 .irq_ack = tegra_ack,
131 .irq_mask = tegra_mask,
132 .irq_unmask = tegra_unmask,
133 .irq_retrigger = tegra_retrigger,
134};
135
136void __init tegra_init_irq(void) 116void __init tegra_init_irq(void)
137{ 117{
138 struct irq_chip *gic; 118 int i;
139 unsigned int i;
140 int irq;
141 119
142 tegra_init_legacy_irq(); 120 for (i = 0; i < NUM_ICTLRS; i++) {
121 void __iomem *ictlr = ictlr_reg_base[i];
122 writel(~0, ictlr + ICTLR_CPU_IER_CLR);
123 writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
124 }
125
126 gic_arch_extn.irq_ack = tegra_ack;
127 gic_arch_extn.irq_eoi = tegra_eoi;
128 gic_arch_extn.irq_mask = tegra_mask;
129 gic_arch_extn.irq_unmask = tegra_unmask;
130 gic_arch_extn.irq_retrigger = tegra_retrigger;
143 131
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 132 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 133 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146
147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack;
151#ifdef CONFIG_SMP
152 tegra_irq.irq_set_affinity = gic->irq_set_affinity;
153#endif
154
155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i;
157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 set_irq_flags(irq, IRQF_VALID);
159 }
160} 134}