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-rw-r--r--arch/arm/mach-tegra/irq.c66
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 567b75c4c67b..4fa7a37ea5e4 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -28,75 +28,9 @@
28 28
29#include <mach/iomap.h> 29#include <mach/iomap.h>
30#include <mach/legacy_irq.h> 30#include <mach/legacy_irq.h>
31#include <mach/suspend.h>
32 31
33#include "board.h" 32#include "board.h"
34 33
35#define PMC_CTRL 0x0
36#define PMC_CTRL_LATCH_WAKEUPS (1 << 5)
37#define PMC_WAKE_MASK 0xc
38#define PMC_WAKE_LEVEL 0x10
39#define PMC_WAKE_STATUS 0x14
40#define PMC_SW_WAKE_STATUS 0x18
41#define PMC_DPD_SAMPLE 0x20
42
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
44
45static u32 tegra_lp0_wake_enb;
46static u32 tegra_lp0_wake_level;
47static u32 tegra_lp0_wake_level_any;
48
49/* ensures that sufficient time is passed for a register write to
50 * serialize into the 32KHz domain */
51static void pmc_32kwritel(u32 val, unsigned long offs)
52{
53 writel(val, pmc + offs);
54 udelay(130);
55}
56
57int tegra_set_lp1_wake(int irq, int enable)
58{
59 return tegra_legacy_irq_set_wake(irq, enable);
60}
61
62void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
63{
64 u32 temp;
65 u32 status;
66 u32 lvl;
67
68 wake_level &= wake_enb;
69 wake_any &= wake_enb;
70
71 wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
72 wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
73
74 wake_enb |= tegra_lp0_wake_enb;
75
76 pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
77 temp = readl(pmc + PMC_CTRL);
78 temp |= PMC_CTRL_LATCH_WAKEUPS;
79 pmc_32kwritel(temp, PMC_CTRL);
80 temp &= ~PMC_CTRL_LATCH_WAKEUPS;
81 pmc_32kwritel(temp, PMC_CTRL);
82 status = readl(pmc + PMC_SW_WAKE_STATUS);
83 lvl = readl(pmc + PMC_WAKE_LEVEL);
84
85 /* flip the wakeup trigger for any-edge triggered pads
86 * which are currently asserting as wakeups */
87 lvl ^= status;
88 lvl &= wake_any;
89
90 wake_level |= lvl;
91
92 writel(wake_level, pmc + PMC_WAKE_LEVEL);
93 /* Enable DPD sample to trigger sampling pads data and direction
94 * in which pad will be driven during lp0 mode*/
95 writel(0x1, pmc + PMC_DPD_SAMPLE);
96
97 writel(wake_enb, pmc + PMC_WAKE_MASK);
98}
99
100static void tegra_mask(struct irq_data *d) 34static void tegra_mask(struct irq_data *d)
101{ 35{
102 if (d->irq >= 32) 36 if (d->irq >= 32)