aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-tegra/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-tegra/include')
-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S100
-rw-r--r--arch/arm/mach-tegra/include/mach/dma.h54
-rw-r--r--arch/arm/mach-tegra/include/mach/iomap.h325
-rw-r--r--arch/arm/mach-tegra/include/mach/irammap.h35
-rw-r--r--arch/arm/mach-tegra/include/mach/irqs.h182
-rw-r--r--arch/arm/mach-tegra/include/mach/powergate.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/tegra-ahb.h19
-rw-r--r--arch/arm/mach-tegra/include/mach/uncompress.h67
8 files changed, 7 insertions, 777 deletions
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
deleted file mode 100644
index 8ce0661b8a3d..000000000000
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2010,2011 Google, Inc.
5 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 * Erik Gilling <konkers@google.com>
10 * Doug Anderson <dianders@chromium.org>
11 * Stephen Warren <swarren@nvidia.com>
12 *
13 * Portions based on mach-omap2's debug-macro.S
14 * Copyright (C) 1994-1999 Russell King
15 *
16 * This software is licensed under the terms of the GNU General Public
17 * License version 2, as published by the Free Software Foundation, and
18 * may be copied, distributed, and modified under those terms.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 */
26
27#include <linux/serial_reg.h>
28
29#include <mach/iomap.h>
30#include <mach/irammap.h>
31
32 .macro addruart, rp, rv, tmp
33 adr \rp, 99f @ actual addr of 99f
34 ldr \rv, [\rp] @ linked addr is stored there
35 sub \rv, \rv, \rp @ offset between the two
36 ldr \rp, [\rp, #4] @ linked tegra_uart_config
37 sub \tmp, \rp, \rv @ actual tegra_uart_config
38 ldr \rp, [\tmp] @ Load tegra_uart_config
39 cmp \rp, #1 @ needs intitialization?
40 bne 100f @ no; go load the addresses
41 mov \rv, #0 @ yes; record init is done
42 str \rv, [\tmp]
43 mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM
44 ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET]
45 movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff
46 movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16
47 cmp \rv, \rp @ Cookie present?
48 bne 100f @ No, use default UART
49 mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM
50 ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4]
51 str \rv, [\tmp, #4] @ Store in tegra_uart_phys
52 sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address
53 add \rv, \rv, #IO_APB_VIRT
54 str \rv, [\tmp, #8] @ Store in tegra_uart_virt
55 b 100f
56
57 .align
5899: .word .
59 .word tegra_uart_config
60 .ltorg
61
62100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
63 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
64 .endm
65
66#define UART_SHIFT 2
67
68/*
69 * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra
70 * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case.
71 * We use the fact that all 5 valid UART addresses all have something in the
72 * 2nd-to-lowest byte.
73 */
74
75 .macro senduart, rd, rx
76 tst \rx, #0x0000ff00
77 strneb \rd, [\rx, #UART_TX << UART_SHIFT]
781001:
79 .endm
80
81 .macro busyuart, rd, rx
82 tst \rx, #0x0000ff00
83 beq 1002f
841001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT]
85 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
86 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
87 bne 1001b
881002:
89 .endm
90
91 .macro waituart, rd, rx
92#ifdef FLOW_CONTROL
93 tst \rx, #0x0000ff00
94 beq 1002f
951001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT]
96 tst \rd, #UART_MSR_CTS
97 beq 1001b
981002:
99#endif
100 .endm
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
deleted file mode 100644
index 3081cc6dda3b..000000000000
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/dma.h
3 *
4 * Copyright (c) 2008-2009, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_TEGRA_DMA_H
22#define __MACH_TEGRA_DMA_H
23
24#include <linux/list.h>
25
26#define TEGRA_DMA_REQ_SEL_CNTR 0
27#define TEGRA_DMA_REQ_SEL_I2S_2 1
28#define TEGRA_DMA_REQ_SEL_I2S_1 2
29#define TEGRA_DMA_REQ_SEL_SPD_I 3
30#define TEGRA_DMA_REQ_SEL_UI_I 4
31#define TEGRA_DMA_REQ_SEL_MIPI 5
32#define TEGRA_DMA_REQ_SEL_I2S2_2 6
33#define TEGRA_DMA_REQ_SEL_I2S2_1 7
34#define TEGRA_DMA_REQ_SEL_UARTA 8
35#define TEGRA_DMA_REQ_SEL_UARTB 9
36#define TEGRA_DMA_REQ_SEL_UARTC 10
37#define TEGRA_DMA_REQ_SEL_SPI 11
38#define TEGRA_DMA_REQ_SEL_AC97 12
39#define TEGRA_DMA_REQ_SEL_ACMODEM 13
40#define TEGRA_DMA_REQ_SEL_SL4B 14
41#define TEGRA_DMA_REQ_SEL_SL2B1 15
42#define TEGRA_DMA_REQ_SEL_SL2B2 16
43#define TEGRA_DMA_REQ_SEL_SL2B3 17
44#define TEGRA_DMA_REQ_SEL_SL2B4 18
45#define TEGRA_DMA_REQ_SEL_UARTD 19
46#define TEGRA_DMA_REQ_SEL_UARTE 20
47#define TEGRA_DMA_REQ_SEL_I2C 21
48#define TEGRA_DMA_REQ_SEL_I2C2 22
49#define TEGRA_DMA_REQ_SEL_I2C3 23
50#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
51#define TEGRA_DMA_REQ_SEL_OWR 25
52#define TEGRA_DMA_REQ_SEL_INVALID 31
53
54#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
deleted file mode 100644
index fee3a94c4549..000000000000
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ /dev/null
@@ -1,325 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/iomap.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IOMAP_H
22#define __MACH_TEGRA_IOMAP_H
23
24#include <asm/sizes.h>
25
26#define TEGRA_IRAM_BASE 0x40000000
27#define TEGRA_IRAM_SIZE SZ_256K
28
29#define TEGRA_HOST1X_BASE 0x50000000
30#define TEGRA_HOST1X_SIZE 0x24000
31
32#define TEGRA_ARM_PERIF_BASE 0x50040000
33#define TEGRA_ARM_PERIF_SIZE SZ_8K
34
35#define TEGRA_ARM_PL310_BASE 0x50043000
36#define TEGRA_ARM_PL310_SIZE SZ_4K
37
38#define TEGRA_ARM_INT_DIST_BASE 0x50041000
39#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
40
41#define TEGRA_MPE_BASE 0x54040000
42#define TEGRA_MPE_SIZE SZ_256K
43
44#define TEGRA_VI_BASE 0x54080000
45#define TEGRA_VI_SIZE SZ_256K
46
47#define TEGRA_ISP_BASE 0x54100000
48#define TEGRA_ISP_SIZE SZ_256K
49
50#define TEGRA_DISPLAY_BASE 0x54200000
51#define TEGRA_DISPLAY_SIZE SZ_256K
52
53#define TEGRA_DISPLAY2_BASE 0x54240000
54#define TEGRA_DISPLAY2_SIZE SZ_256K
55
56#define TEGRA_HDMI_BASE 0x54280000
57#define TEGRA_HDMI_SIZE SZ_256K
58
59#define TEGRA_GART_BASE 0x58000000
60#define TEGRA_GART_SIZE SZ_32M
61
62#define TEGRA_RES_SEMA_BASE 0x60001000
63#define TEGRA_RES_SEMA_SIZE SZ_4K
64
65#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
66#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64
67
68#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
69#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64
70
71#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
72#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64
73
74#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
75#define TEGRA_QUATERNARY_ICTLR_SIZE SZ_64
76
77#define TEGRA_QUINARY_ICTLR_BASE 0x60004400
78#define TEGRA_QUINARY_ICTLR_SIZE SZ_64
79
80#define TEGRA_TMR1_BASE 0x60005000
81#define TEGRA_TMR1_SIZE SZ_8
82
83#define TEGRA_TMR2_BASE 0x60005008
84#define TEGRA_TMR2_SIZE SZ_8
85
86#define TEGRA_TMRUS_BASE 0x60005010
87#define TEGRA_TMRUS_SIZE SZ_64
88
89#define TEGRA_TMR3_BASE 0x60005050
90#define TEGRA_TMR3_SIZE SZ_8
91
92#define TEGRA_TMR4_BASE 0x60005058
93#define TEGRA_TMR4_SIZE SZ_8
94
95#define TEGRA_CLK_RESET_BASE 0x60006000
96#define TEGRA_CLK_RESET_SIZE SZ_4K
97
98#define TEGRA_FLOW_CTRL_BASE 0x60007000
99#define TEGRA_FLOW_CTRL_SIZE 20
100
101#define TEGRA_AHB_DMA_BASE 0x60008000
102#define TEGRA_AHB_DMA_SIZE SZ_4K
103
104#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
105#define TEGRA_AHB_DMA_CH0_SIZE 32
106
107#define TEGRA_APB_DMA_BASE 0x6000A000
108#define TEGRA_APB_DMA_SIZE SZ_4K
109
110#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
111#define TEGRA_APB_DMA_CH0_SIZE 32
112
113#define TEGRA_AHB_GIZMO_BASE 0x6000C004
114#define TEGRA_AHB_GIZMO_SIZE 0x10C
115
116#define TEGRA_SB_BASE 0x6000C200
117#define TEGRA_SB_SIZE 256
118
119#define TEGRA_STATMON_BASE 0x6000C400
120#define TEGRA_STATMON_SIZE SZ_1K
121
122#define TEGRA_GPIO_BASE 0x6000D000
123#define TEGRA_GPIO_SIZE SZ_4K
124
125#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
126#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
127
128#define TEGRA_APB_MISC_BASE 0x70000000
129#define TEGRA_APB_MISC_SIZE SZ_4K
130
131#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
132#define TEGRA_APB_MISC_DAS_SIZE SZ_128
133
134#define TEGRA_AC97_BASE 0x70002000
135#define TEGRA_AC97_SIZE SZ_512
136
137#define TEGRA_SPDIF_BASE 0x70002400
138#define TEGRA_SPDIF_SIZE SZ_512
139
140#define TEGRA_I2S1_BASE 0x70002800
141#define TEGRA_I2S1_SIZE SZ_256
142
143#define TEGRA_I2S2_BASE 0x70002A00
144#define TEGRA_I2S2_SIZE SZ_256
145
146#define TEGRA_UARTA_BASE 0x70006000
147#define TEGRA_UARTA_SIZE SZ_64
148
149#define TEGRA_UARTB_BASE 0x70006040
150#define TEGRA_UARTB_SIZE SZ_64
151
152#define TEGRA_UARTC_BASE 0x70006200
153#define TEGRA_UARTC_SIZE SZ_256
154
155#define TEGRA_UARTD_BASE 0x70006300
156#define TEGRA_UARTD_SIZE SZ_256
157
158#define TEGRA_UARTE_BASE 0x70006400
159#define TEGRA_UARTE_SIZE SZ_256
160
161#define TEGRA_NAND_BASE 0x70008000
162#define TEGRA_NAND_SIZE SZ_256
163
164#define TEGRA_HSMMC_BASE 0x70008500
165#define TEGRA_HSMMC_SIZE SZ_256
166
167#define TEGRA_SNOR_BASE 0x70009000
168#define TEGRA_SNOR_SIZE SZ_4K
169
170#define TEGRA_PWFM_BASE 0x7000A000
171#define TEGRA_PWFM_SIZE SZ_256
172
173#define TEGRA_PWFM0_BASE 0x7000A000
174#define TEGRA_PWFM0_SIZE 4
175
176#define TEGRA_PWFM1_BASE 0x7000A010
177#define TEGRA_PWFM1_SIZE 4
178
179#define TEGRA_PWFM2_BASE 0x7000A020
180#define TEGRA_PWFM2_SIZE 4
181
182#define TEGRA_PWFM3_BASE 0x7000A030
183#define TEGRA_PWFM3_SIZE 4
184
185#define TEGRA_MIPI_BASE 0x7000B000
186#define TEGRA_MIPI_SIZE SZ_256
187
188#define TEGRA_I2C_BASE 0x7000C000
189#define TEGRA_I2C_SIZE SZ_256
190
191#define TEGRA_TWC_BASE 0x7000C100
192#define TEGRA_TWC_SIZE SZ_256
193
194#define TEGRA_SPI_BASE 0x7000C380
195#define TEGRA_SPI_SIZE 48
196
197#define TEGRA_I2C2_BASE 0x7000C400
198#define TEGRA_I2C2_SIZE SZ_256
199
200#define TEGRA_I2C3_BASE 0x7000C500
201#define TEGRA_I2C3_SIZE SZ_256
202
203#define TEGRA_OWR_BASE 0x7000C600
204#define TEGRA_OWR_SIZE 80
205
206#define TEGRA_DVC_BASE 0x7000D000
207#define TEGRA_DVC_SIZE SZ_512
208
209#define TEGRA_SPI1_BASE 0x7000D400
210#define TEGRA_SPI1_SIZE SZ_512
211
212#define TEGRA_SPI2_BASE 0x7000D600
213#define TEGRA_SPI2_SIZE SZ_512
214
215#define TEGRA_SPI3_BASE 0x7000D800
216#define TEGRA_SPI3_SIZE SZ_512
217
218#define TEGRA_SPI4_BASE 0x7000DA00
219#define TEGRA_SPI4_SIZE SZ_512
220
221#define TEGRA_RTC_BASE 0x7000E000
222#define TEGRA_RTC_SIZE SZ_256
223
224#define TEGRA_KBC_BASE 0x7000E200
225#define TEGRA_KBC_SIZE SZ_256
226
227#define TEGRA_PMC_BASE 0x7000E400
228#define TEGRA_PMC_SIZE SZ_256
229
230#define TEGRA_MC_BASE 0x7000F000
231#define TEGRA_MC_SIZE SZ_1K
232
233#define TEGRA_EMC_BASE 0x7000F400
234#define TEGRA_EMC_SIZE SZ_1K
235
236#define TEGRA_FUSE_BASE 0x7000F800
237#define TEGRA_FUSE_SIZE SZ_1K
238
239#define TEGRA_KFUSE_BASE 0x7000FC00
240#define TEGRA_KFUSE_SIZE SZ_1K
241
242#define TEGRA_CSITE_BASE 0x70040000
243#define TEGRA_CSITE_SIZE SZ_256K
244
245#define TEGRA_USB_BASE 0xC5000000
246#define TEGRA_USB_SIZE SZ_16K
247
248#define TEGRA_USB2_BASE 0xC5004000
249#define TEGRA_USB2_SIZE SZ_16K
250
251#define TEGRA_USB3_BASE 0xC5008000
252#define TEGRA_USB3_SIZE SZ_16K
253
254#define TEGRA_SDMMC1_BASE 0xC8000000
255#define TEGRA_SDMMC1_SIZE SZ_512
256
257#define TEGRA_SDMMC2_BASE 0xC8000200
258#define TEGRA_SDMMC2_SIZE SZ_512
259
260#define TEGRA_SDMMC3_BASE 0xC8000400
261#define TEGRA_SDMMC3_SIZE SZ_512
262
263#define TEGRA_SDMMC4_BASE 0xC8000600
264#define TEGRA_SDMMC4_SIZE SZ_512
265
266#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
267# define TEGRA_DEBUG_UART_BASE 0
268#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
269# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
270#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
271# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
272#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
273# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
274#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
275# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
276#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
277# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
278#endif
279
280/* On TEGRA, many peripherals are very closely packed in
281 * two 256MB io windows (that actually only use about 64KB
282 * at the start of each).
283 *
284 * We will just map the first 1MB of each window (to minimize
285 * pt entries needed) and provide a macro to transform physical
286 * io addresses to an appropriate void __iomem *.
287 *
288 */
289
290#define IO_IRAM_PHYS 0x40000000
291#define IO_IRAM_VIRT IOMEM(0xFE400000)
292#define IO_IRAM_SIZE SZ_256K
293
294#define IO_CPU_PHYS 0x50040000
295#define IO_CPU_VIRT IOMEM(0xFE000000)
296#define IO_CPU_SIZE SZ_16K
297
298#define IO_PPSB_PHYS 0x60000000
299#define IO_PPSB_VIRT IOMEM(0xFE200000)
300#define IO_PPSB_SIZE SZ_1M
301
302#define IO_APB_PHYS 0x70000000
303#define IO_APB_VIRT IOMEM(0xFE300000)
304#define IO_APB_SIZE SZ_1M
305
306#define TEGRA_PCIE_BASE 0x80000000
307#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
308
309#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
310#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
311
312#define IO_TO_VIRT(n) ( \
313 IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \
314 IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \
315 IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \
316 IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \
317 IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \
318 IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \
319 IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \
320 IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \
321 NULL)
322
323#define IO_ADDRESS(n) (IO_TO_VIRT(n))
324
325#endif
diff --git a/arch/arm/mach-tegra/include/mach/irammap.h b/arch/arm/mach-tegra/include/mach/irammap.h
deleted file mode 100644
index 0cbe63261854..000000000000
--- a/arch/arm/mach-tegra/include/mach/irammap.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_IRAMMAP_H
18#define __MACH_TEGRA_IRAMMAP_H
19
20#include <asm/sizes.h>
21
22/* The first 1K of IRAM is permanently reserved for the CPU reset handler */
23#define TEGRA_IRAM_RESET_HANDLER_OFFSET 0
24#define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K
25
26/*
27 * These locations are written to by uncompress.h, and read by debug-macro.S.
28 * The first word holds the cookie value if the data is valid. The second
29 * word holds the UART physical address.
30 */
31#define TEGRA_IRAM_DEBUG_UART_OFFSET SZ_1K
32#define TEGRA_IRAM_DEBUG_UART_SIZE 8
33#define TEGRA_IRAM_DEBUG_UART_COOKIE 0x55415254
34
35#endif
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
deleted file mode 100644
index aad1a2c1d714..000000000000
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ /dev/null
@@ -1,182 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/irqs.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_IRQS_H
22#define __MACH_TEGRA_IRQS_H
23
24#define INT_GIC_BASE 0
25
26#define IRQ_LOCALTIMER 29
27
28/* Primary Interrupt Controller */
29#define INT_PRI_BASE (INT_GIC_BASE + 32)
30#define INT_TMR1 (INT_PRI_BASE + 0)
31#define INT_TMR2 (INT_PRI_BASE + 1)
32#define INT_RTC (INT_PRI_BASE + 2)
33#define INT_I2S2 (INT_PRI_BASE + 3)
34#define INT_SHR_SEM_INBOX_IBF (INT_PRI_BASE + 4)
35#define INT_SHR_SEM_INBOX_IBE (INT_PRI_BASE + 5)
36#define INT_SHR_SEM_OUTBOX_IBF (INT_PRI_BASE + 6)
37#define INT_SHR_SEM_OUTBOX_IBE (INT_PRI_BASE + 7)
38#define INT_VDE_UCQ_ERROR (INT_PRI_BASE + 8)
39#define INT_VDE_SYNC_TOKEN (INT_PRI_BASE + 9)
40#define INT_VDE_BSE_V (INT_PRI_BASE + 10)
41#define INT_VDE_BSE_A (INT_PRI_BASE + 11)
42#define INT_VDE_SXE (INT_PRI_BASE + 12)
43#define INT_I2S1 (INT_PRI_BASE + 13)
44#define INT_SDMMC1 (INT_PRI_BASE + 14)
45#define INT_SDMMC2 (INT_PRI_BASE + 15)
46#define INT_XIO (INT_PRI_BASE + 16)
47#define INT_VDE (INT_PRI_BASE + 17)
48#define INT_AVP_UCQ (INT_PRI_BASE + 18)
49#define INT_SDMMC3 (INT_PRI_BASE + 19)
50#define INT_USB (INT_PRI_BASE + 20)
51#define INT_USB2 (INT_PRI_BASE + 21)
52#define INT_PRI_RES_22 (INT_PRI_BASE + 22)
53#define INT_EIDE (INT_PRI_BASE + 23)
54#define INT_NANDFLASH (INT_PRI_BASE + 24)
55#define INT_VCP (INT_PRI_BASE + 25)
56#define INT_APB_DMA (INT_PRI_BASE + 26)
57#define INT_AHB_DMA (INT_PRI_BASE + 27)
58#define INT_GNT_0 (INT_PRI_BASE + 28)
59#define INT_GNT_1 (INT_PRI_BASE + 29)
60#define INT_OWR (INT_PRI_BASE + 30)
61#define INT_SDMMC4 (INT_PRI_BASE + 31)
62
63/* Secondary Interrupt Controller */
64#define INT_SEC_BASE (INT_PRI_BASE + 32)
65#define INT_GPIO1 (INT_SEC_BASE + 0)
66#define INT_GPIO2 (INT_SEC_BASE + 1)
67#define INT_GPIO3 (INT_SEC_BASE + 2)
68#define INT_GPIO4 (INT_SEC_BASE + 3)
69#define INT_UARTA (INT_SEC_BASE + 4)
70#define INT_UARTB (INT_SEC_BASE + 5)
71#define INT_I2C (INT_SEC_BASE + 6)
72#define INT_SPI (INT_SEC_BASE + 7)
73#define INT_TWC (INT_SEC_BASE + 8)
74#define INT_TMR3 (INT_SEC_BASE + 9)
75#define INT_TMR4 (INT_SEC_BASE + 10)
76#define INT_FLOW_RSM0 (INT_SEC_BASE + 11)
77#define INT_FLOW_RSM1 (INT_SEC_BASE + 12)
78#define INT_SPDIF (INT_SEC_BASE + 13)
79#define INT_UARTC (INT_SEC_BASE + 14)
80#define INT_MIPI (INT_SEC_BASE + 15)
81#define INT_EVENTA (INT_SEC_BASE + 16)
82#define INT_EVENTB (INT_SEC_BASE + 17)
83#define INT_EVENTC (INT_SEC_BASE + 18)
84#define INT_EVENTD (INT_SEC_BASE + 19)
85#define INT_VFIR (INT_SEC_BASE + 20)
86#define INT_DVC (INT_SEC_BASE + 21)
87#define INT_SYS_STATS_MON (INT_SEC_BASE + 22)
88#define INT_GPIO5 (INT_SEC_BASE + 23)
89#define INT_CPU0_PMU_INTR (INT_SEC_BASE + 24)
90#define INT_CPU1_PMU_INTR (INT_SEC_BASE + 25)
91#define INT_SEC_RES_26 (INT_SEC_BASE + 26)
92#define INT_S_LINK1 (INT_SEC_BASE + 27)
93#define INT_APB_DMA_COP (INT_SEC_BASE + 28)
94#define INT_AHB_DMA_COP (INT_SEC_BASE + 29)
95#define INT_DMA_TX (INT_SEC_BASE + 30)
96#define INT_DMA_RX (INT_SEC_BASE + 31)
97
98/* Tertiary Interrupt Controller */
99#define INT_TRI_BASE (INT_SEC_BASE + 32)
100#define INT_HOST1X_COP_SYNCPT (INT_TRI_BASE + 0)
101#define INT_HOST1X_MPCORE_SYNCPT (INT_TRI_BASE + 1)
102#define INT_HOST1X_COP_GENERAL (INT_TRI_BASE + 2)
103#define INT_HOST1X_MPCORE_GENERAL (INT_TRI_BASE + 3)
104#define INT_MPE_GENERAL (INT_TRI_BASE + 4)
105#define INT_VI_GENERAL (INT_TRI_BASE + 5)
106#define INT_EPP_GENERAL (INT_TRI_BASE + 6)
107#define INT_ISP_GENERAL (INT_TRI_BASE + 7)
108#define INT_2D_GENERAL (INT_TRI_BASE + 8)
109#define INT_DISPLAY_GENERAL (INT_TRI_BASE + 9)
110#define INT_DISPLAY_B_GENERAL (INT_TRI_BASE + 10)
111#define INT_HDMI (INT_TRI_BASE + 11)
112#define INT_TVO_GENERAL (INT_TRI_BASE + 12)
113#define INT_MC_GENERAL (INT_TRI_BASE + 13)
114#define INT_EMC_GENERAL (INT_TRI_BASE + 14)
115#define INT_TRI_RES_15 (INT_TRI_BASE + 15)
116#define INT_TRI_RES_16 (INT_TRI_BASE + 16)
117#define INT_AC97 (INT_TRI_BASE + 17)
118#define INT_SPI_2 (INT_TRI_BASE + 18)
119#define INT_SPI_3 (INT_TRI_BASE + 19)
120#define INT_I2C2 (INT_TRI_BASE + 20)
121#define INT_KBC (INT_TRI_BASE + 21)
122#define INT_EXTERNAL_PMU (INT_TRI_BASE + 22)
123#define INT_GPIO6 (INT_TRI_BASE + 23)
124#define INT_TVDAC (INT_TRI_BASE + 24)
125#define INT_GPIO7 (INT_TRI_BASE + 25)
126#define INT_UARTD (INT_TRI_BASE + 26)
127#define INT_UARTE (INT_TRI_BASE + 27)
128#define INT_I2C3 (INT_TRI_BASE + 28)
129#define INT_SPI_4 (INT_TRI_BASE + 29)
130#define INT_TRI_RES_30 (INT_TRI_BASE + 30)
131#define INT_SW_RESERVED (INT_TRI_BASE + 31)
132
133/* Quaternary Interrupt Controller */
134#define INT_QUAD_BASE (INT_TRI_BASE + 32)
135#define INT_SNOR (INT_QUAD_BASE + 0)
136#define INT_USB3 (INT_QUAD_BASE + 1)
137#define INT_PCIE_INTR (INT_QUAD_BASE + 2)
138#define INT_PCIE_MSI (INT_QUAD_BASE + 3)
139#define INT_QUAD_RES_4 (INT_QUAD_BASE + 4)
140#define INT_QUAD_RES_5 (INT_QUAD_BASE + 5)
141#define INT_QUAD_RES_6 (INT_QUAD_BASE + 6)
142#define INT_QUAD_RES_7 (INT_QUAD_BASE + 7)
143#define INT_APB_DMA_CH0 (INT_QUAD_BASE + 8)
144#define INT_APB_DMA_CH1 (INT_QUAD_BASE + 9)
145#define INT_APB_DMA_CH2 (INT_QUAD_BASE + 10)
146#define INT_APB_DMA_CH3 (INT_QUAD_BASE + 11)
147#define INT_APB_DMA_CH4 (INT_QUAD_BASE + 12)
148#define INT_APB_DMA_CH5 (INT_QUAD_BASE + 13)
149#define INT_APB_DMA_CH6 (INT_QUAD_BASE + 14)
150#define INT_APB_DMA_CH7 (INT_QUAD_BASE + 15)
151#define INT_APB_DMA_CH8 (INT_QUAD_BASE + 16)
152#define INT_APB_DMA_CH9 (INT_QUAD_BASE + 17)
153#define INT_APB_DMA_CH10 (INT_QUAD_BASE + 18)
154#define INT_APB_DMA_CH11 (INT_QUAD_BASE + 19)
155#define INT_APB_DMA_CH12 (INT_QUAD_BASE + 20)
156#define INT_APB_DMA_CH13 (INT_QUAD_BASE + 21)
157#define INT_APB_DMA_CH14 (INT_QUAD_BASE + 22)
158#define INT_APB_DMA_CH15 (INT_QUAD_BASE + 23)
159#define INT_QUAD_RES_24 (INT_QUAD_BASE + 24)
160#define INT_QUAD_RES_25 (INT_QUAD_BASE + 25)
161#define INT_QUAD_RES_26 (INT_QUAD_BASE + 26)
162#define INT_QUAD_RES_27 (INT_QUAD_BASE + 27)
163#define INT_QUAD_RES_28 (INT_QUAD_BASE + 28)
164#define INT_QUAD_RES_29 (INT_QUAD_BASE + 29)
165#define INT_QUAD_RES_30 (INT_QUAD_BASE + 30)
166#define INT_QUAD_RES_31 (INT_QUAD_BASE + 31)
167
168/* Tegra30 has 5 banks of 32 IRQs */
169#define INT_MAIN_NR (32 * 5)
170#define INT_GPIO_BASE (INT_PRI_BASE + INT_MAIN_NR)
171
172/* Tegra30 has 8 banks of 32 GPIOs */
173#define INT_GPIO_NR (32 * 8)
174
175#define TEGRA_NR_IRQS (INT_GPIO_BASE + INT_GPIO_NR)
176
177#define INT_BOARD_BASE TEGRA_NR_IRQS
178#define NR_BOARD_IRQS 32
179
180#define NR_IRQS (INT_BOARD_BASE + NR_BOARD_IRQS)
181
182#endif
diff --git a/arch/arm/mach-tegra/include/mach/powergate.h b/arch/arm/mach-tegra/include/mach/powergate.h
index 4752b1a68f35..06763fe7529d 100644
--- a/arch/arm/mach-tegra/include/mach/powergate.h
+++ b/arch/arm/mach-tegra/include/mach/powergate.h
@@ -20,6 +20,8 @@
20#ifndef _MACH_TEGRA_POWERGATE_H_ 20#ifndef _MACH_TEGRA_POWERGATE_H_
21#define _MACH_TEGRA_POWERGATE_H_ 21#define _MACH_TEGRA_POWERGATE_H_
22 22
23struct clk;
24
23#define TEGRA_POWERGATE_CPU 0 25#define TEGRA_POWERGATE_CPU 0
24#define TEGRA_POWERGATE_3D 1 26#define TEGRA_POWERGATE_3D 1
25#define TEGRA_POWERGATE_VENC 2 27#define TEGRA_POWERGATE_VENC 2
diff --git a/arch/arm/mach-tegra/include/mach/tegra-ahb.h b/arch/arm/mach-tegra/include/mach/tegra-ahb.h
deleted file mode 100644
index e0f8c84b1d8c..000000000000
--- a/arch/arm/mach-tegra/include/mach/tegra-ahb.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __MACH_TEGRA_AHB_H__
15#define __MACH_TEGRA_AHB_H__
16
17extern int tegra_ahb_enable_smmu(struct device_node *ahb);
18
19#endif /* __MACH_TEGRA_AHB_H__ */
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
index 937c4c50219e..485003f9b636 100644
--- a/arch/arm/mach-tegra/include/mach/uncompress.h
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -28,8 +28,7 @@
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/serial_reg.h> 29#include <linux/serial_reg.h>
30 30
31#include <mach/iomap.h> 31#include "../../iomap.h"
32#include <mach/irammap.h>
33 32
34#define BIT(x) (1 << (x)) 33#define BIT(x) (1 << (x))
35#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 34#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
@@ -52,17 +51,6 @@ static inline void flush(void)
52{ 51{
53} 52}
54 53
55static inline void save_uart_address(void)
56{
57 u32 *buf = (u32 *)(TEGRA_IRAM_BASE + TEGRA_IRAM_DEBUG_UART_OFFSET);
58
59 if (uart) {
60 buf[0] = TEGRA_IRAM_DEBUG_UART_COOKIE;
61 buf[1] = (u32)uart;
62 } else
63 buf[0] = 0;
64}
65
66static const struct { 54static const struct {
67 u32 base; 55 u32 base;
68 u32 reset_reg; 56 u32 reset_reg;
@@ -139,51 +127,19 @@ int auto_odmdata(void)
139} 127}
140#endif 128#endif
141 129
142#ifdef CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH
143int auto_scratch(void)
144{
145 int i;
146
147 /*
148 * Look for the first UART that:
149 * a) Is not in reset.
150 * b) Is clocked.
151 * c) Has a 'D' in the scratchpad register.
152 *
153 * Note that on Tegra30, the first two conditions are required, since
154 * if not true, accesses to the UART scratch register will hang.
155 * Tegra20 doesn't have this issue.
156 *
157 * The intent is that the bootloader will tell the kernel which UART
158 * to use by setting up those conditions. If nothing found, we'll fall
159 * back to what's specified in TEGRA_DEBUG_UART_BASE.
160 */
161 for (i = 0; i < ARRAY_SIZE(uarts); i++) {
162 if (!uart_clocked(i))
163 continue;
164
165 uart = (volatile u8 *)uarts[i].base;
166 if (uart[UART_SCR << DEBUG_UART_SHIFT] != 'D')
167 continue;
168
169 return i;
170 }
171
172 return -1;
173}
174#endif
175
176/* 130/*
177 * Setup before decompression. This is where we do UART selection for 131 * Setup before decompression. This is where we do UART selection for
178 * earlyprintk and init the uart_base register. 132 * earlyprintk and init the uart_base register.
179 */ 133 */
180static inline void arch_decomp_setup(void) 134static inline void arch_decomp_setup(void)
181{ 135{
182 int uart_id, auto_uart_id; 136 int uart_id;
183 volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; 137 volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE;
184 u32 chip, div; 138 u32 chip, div;
185 139
186#if defined(CONFIG_TEGRA_DEBUG_UARTA) 140#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
141 uart_id = auto_odmdata();
142#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
187 uart_id = 0; 143 uart_id = 0;
188#elif defined(CONFIG_TEGRA_DEBUG_UARTB) 144#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
189 uart_id = 1; 145 uart_id = 1;
@@ -193,19 +149,7 @@ static inline void arch_decomp_setup(void)
193 uart_id = 3; 149 uart_id = 3;
194#elif defined(CONFIG_TEGRA_DEBUG_UARTE) 150#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
195 uart_id = 4; 151 uart_id = 4;
196#else
197 uart_id = -1;
198#endif
199
200#if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA)
201 auto_uart_id = auto_odmdata();
202#elif defined(CONFIG_TEGRA_DEBUG_UART_AUTO_SCRATCH)
203 auto_uart_id = auto_scratch();
204#else
205 auto_uart_id = -1;
206#endif 152#endif
207 if (auto_uart_id != -1)
208 uart_id = auto_uart_id;
209 153
210 if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) || 154 if (uart_id < 0 || uart_id >= ARRAY_SIZE(uarts) ||
211 !uart_clocked(uart_id)) 155 !uart_clocked(uart_id))
@@ -213,7 +157,6 @@ static inline void arch_decomp_setup(void)
213 else 157 else
214 uart = (volatile u8 *)uarts[uart_id].base; 158 uart = (volatile u8 *)uarts[uart_id].base;
215 159
216 save_uart_address();
217 if (uart == NULL) 160 if (uart == NULL)
218 return; 161 return;
219 162
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 04:40:33 -0500