diff options
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/debug-macro.S')
-rw-r--r-- | arch/arm/mach-tegra/include/mach/debug-macro.S | 100 |
1 files changed, 0 insertions, 100 deletions
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S deleted file mode 100644 index 8ce0661b8a3d..000000000000 --- a/arch/arm/mach-tegra/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,100 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/include/mach/debug-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2010,2011 Google, Inc. | ||
5 | * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved. | ||
6 | * | ||
7 | * Author: | ||
8 | * Colin Cross <ccross@google.com> | ||
9 | * Erik Gilling <konkers@google.com> | ||
10 | * Doug Anderson <dianders@chromium.org> | ||
11 | * Stephen Warren <swarren@nvidia.com> | ||
12 | * | ||
13 | * Portions based on mach-omap2's debug-macro.S | ||
14 | * Copyright (C) 1994-1999 Russell King | ||
15 | * | ||
16 | * This software is licensed under the terms of the GNU General Public | ||
17 | * License version 2, as published by the Free Software Foundation, and | ||
18 | * may be copied, distributed, and modified under those terms. | ||
19 | * | ||
20 | * This program is distributed in the hope that it will be useful, | ||
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
23 | * GNU General Public License for more details. | ||
24 | * | ||
25 | */ | ||
26 | |||
27 | #include <linux/serial_reg.h> | ||
28 | |||
29 | #include <mach/iomap.h> | ||
30 | #include <mach/irammap.h> | ||
31 | |||
32 | .macro addruart, rp, rv, tmp | ||
33 | adr \rp, 99f @ actual addr of 99f | ||
34 | ldr \rv, [\rp] @ linked addr is stored there | ||
35 | sub \rv, \rv, \rp @ offset between the two | ||
36 | ldr \rp, [\rp, #4] @ linked tegra_uart_config | ||
37 | sub \tmp, \rp, \rv @ actual tegra_uart_config | ||
38 | ldr \rp, [\tmp] @ Load tegra_uart_config | ||
39 | cmp \rp, #1 @ needs intitialization? | ||
40 | bne 100f @ no; go load the addresses | ||
41 | mov \rv, #0 @ yes; record init is done | ||
42 | str \rv, [\tmp] | ||
43 | mov \rp, #TEGRA_IRAM_BASE @ See if cookie is in IRAM | ||
44 | ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET] | ||
45 | movw \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE & 0xffff | ||
46 | movt \rp, #TEGRA_IRAM_DEBUG_UART_COOKIE >> 16 | ||
47 | cmp \rv, \rp @ Cookie present? | ||
48 | bne 100f @ No, use default UART | ||
49 | mov \rp, #TEGRA_IRAM_BASE @ Load UART address from IRAM | ||
50 | ldr \rv, [\rp, #TEGRA_IRAM_DEBUG_UART_OFFSET + 4] | ||
51 | str \rv, [\tmp, #4] @ Store in tegra_uart_phys | ||
52 | sub \rv, \rv, #IO_APB_PHYS @ Calculate virt address | ||
53 | add \rv, \rv, #IO_APB_VIRT | ||
54 | str \rv, [\tmp, #8] @ Store in tegra_uart_virt | ||
55 | b 100f | ||
56 | |||
57 | .align | ||
58 | 99: .word . | ||
59 | .word tegra_uart_config | ||
60 | .ltorg | ||
61 | |||
62 | 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys | ||
63 | ldr \rv, [\tmp, #8] @ Load tegra_uart_virt | ||
64 | .endm | ||
65 | |||
66 | #define UART_SHIFT 2 | ||
67 | |||
68 | /* | ||
69 | * Code below is swiped from <asm/hardware/debug-8250.S>, but add an extra | ||
70 | * check to make sure that we aren't in the CONFIG_TEGRA_DEBUG_UART_NONE case. | ||
71 | * We use the fact that all 5 valid UART addresses all have something in the | ||
72 | * 2nd-to-lowest byte. | ||
73 | */ | ||
74 | |||
75 | .macro senduart, rd, rx | ||
76 | tst \rx, #0x0000ff00 | ||
77 | strneb \rd, [\rx, #UART_TX << UART_SHIFT] | ||
78 | 1001: | ||
79 | .endm | ||
80 | |||
81 | .macro busyuart, rd, rx | ||
82 | tst \rx, #0x0000ff00 | ||
83 | beq 1002f | ||
84 | 1001: ldrb \rd, [\rx, #UART_LSR << UART_SHIFT] | ||
85 | and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE | ||
86 | teq \rd, #UART_LSR_TEMT | UART_LSR_THRE | ||
87 | bne 1001b | ||
88 | 1002: | ||
89 | .endm | ||
90 | |||
91 | .macro waituart, rd, rx | ||
92 | #ifdef FLOW_CONTROL | ||
93 | tst \rx, #0x0000ff00 | ||
94 | beq 1002f | ||
95 | 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] | ||
96 | tst \rd, #UART_MSR_CTS | ||
97 | beq 1001b | ||
98 | 1002: | ||
99 | #endif | ||
100 | .endm | ||