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-rw-r--r--arch/arm/mach-tegra/devices.c701
1 files changed, 0 insertions, 701 deletions
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
deleted file mode 100644
index 63cc2800dcf8..000000000000
--- a/arch/arm/mach-tegra/devices.c
+++ /dev/null
@@ -1,701 +0,0 @@
1/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19
20#include <linux/resource.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/fsl_devices.h>
24#include <linux/serial_8250.h>
25#include <linux/i2c-tegra.h>
26#include <mach/irqs.h>
27#include <mach/iomap.h>
28#include <mach/dma.h>
29#include <linux/usb/tegra_usb_phy.h>
30
31#include "gpio-names.h"
32#include "devices.h"
33
34static struct resource gpio_resource[] = {
35 [0] = {
36 .start = TEGRA_GPIO_BASE,
37 .end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = INT_GPIO1,
42 .end = INT_GPIO1,
43 .flags = IORESOURCE_IRQ,
44 },
45 [2] = {
46 .start = INT_GPIO2,
47 .end = INT_GPIO2,
48 .flags = IORESOURCE_IRQ,
49 },
50 [3] = {
51 .start = INT_GPIO3,
52 .end = INT_GPIO3,
53 .flags = IORESOURCE_IRQ,
54 },
55 [4] = {
56 .start = INT_GPIO4,
57 .end = INT_GPIO4,
58 .flags = IORESOURCE_IRQ,
59 },
60 [5] = {
61 .start = INT_GPIO5,
62 .end = INT_GPIO5,
63 .flags = IORESOURCE_IRQ,
64 },
65 [6] = {
66 .start = INT_GPIO6,
67 .end = INT_GPIO6,
68 .flags = IORESOURCE_IRQ,
69 },
70 [7] = {
71 .start = INT_GPIO7,
72 .end = INT_GPIO7,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77struct platform_device tegra_gpio_device = {
78 .name = "tegra-gpio",
79 .id = -1,
80 .resource = gpio_resource,
81 .num_resources = ARRAY_SIZE(gpio_resource),
82};
83
84static struct resource pinmux_resource[] = {
85 [0] = {
86 /* Tri-state registers */
87 .start = TEGRA_APB_MISC_BASE + 0x14,
88 .end = TEGRA_APB_MISC_BASE + 0x20 + 3,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 /* Mux registers */
93 .start = TEGRA_APB_MISC_BASE + 0x80,
94 .end = TEGRA_APB_MISC_BASE + 0x9c + 3,
95 .flags = IORESOURCE_MEM,
96 },
97 [2] = {
98 /* Pull-up/down registers */
99 .start = TEGRA_APB_MISC_BASE + 0xa0,
100 .end = TEGRA_APB_MISC_BASE + 0xb0 + 3,
101 .flags = IORESOURCE_MEM,
102 },
103 [3] = {
104 /* Pad control registers */
105 .start = TEGRA_APB_MISC_BASE + 0x868,
106 .end = TEGRA_APB_MISC_BASE + 0x90c + 3,
107 .flags = IORESOURCE_MEM,
108 },
109};
110
111struct platform_device tegra_pinmux_device = {
112 .name = "tegra20-pinctrl",
113 .id = -1,
114 .resource = pinmux_resource,
115 .num_resources = ARRAY_SIZE(pinmux_resource),
116};
117
118static struct resource i2c_resource1[] = {
119 [0] = {
120 .start = INT_I2C,
121 .end = INT_I2C,
122 .flags = IORESOURCE_IRQ,
123 },
124 [1] = {
125 .start = TEGRA_I2C_BASE,
126 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
127 .flags = IORESOURCE_MEM,
128 },
129};
130
131static struct resource i2c_resource2[] = {
132 [0] = {
133 .start = INT_I2C2,
134 .end = INT_I2C2,
135 .flags = IORESOURCE_IRQ,
136 },
137 [1] = {
138 .start = TEGRA_I2C2_BASE,
139 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
140 .flags = IORESOURCE_MEM,
141 },
142};
143
144static struct resource i2c_resource3[] = {
145 [0] = {
146 .start = INT_I2C3,
147 .end = INT_I2C3,
148 .flags = IORESOURCE_IRQ,
149 },
150 [1] = {
151 .start = TEGRA_I2C3_BASE,
152 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
153 .flags = IORESOURCE_MEM,
154 },
155};
156
157static struct resource i2c_resource4[] = {
158 [0] = {
159 .start = INT_DVC,
160 .end = INT_DVC,
161 .flags = IORESOURCE_IRQ,
162 },
163 [1] = {
164 .start = TEGRA_DVC_BASE,
165 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
166 .flags = IORESOURCE_MEM,
167 },
168};
169
170static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
171 .bus_clk_rate = 400000,
172};
173
174static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
175 .bus_clk_rate = 400000,
176};
177
178static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
179 .bus_clk_rate = 400000,
180};
181
182static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
183 .bus_clk_rate = 400000,
184};
185
186struct platform_device tegra_i2c_device1 = {
187 .name = "tegra-i2c",
188 .id = 0,
189 .resource = i2c_resource1,
190 .num_resources = ARRAY_SIZE(i2c_resource1),
191 .dev = {
192 .platform_data = &tegra_i2c1_platform_data,
193 },
194};
195
196struct platform_device tegra_i2c_device2 = {
197 .name = "tegra-i2c",
198 .id = 1,
199 .resource = i2c_resource2,
200 .num_resources = ARRAY_SIZE(i2c_resource2),
201 .dev = {
202 .platform_data = &tegra_i2c2_platform_data,
203 },
204};
205
206struct platform_device tegra_i2c_device3 = {
207 .name = "tegra-i2c",
208 .id = 2,
209 .resource = i2c_resource3,
210 .num_resources = ARRAY_SIZE(i2c_resource3),
211 .dev = {
212 .platform_data = &tegra_i2c3_platform_data,
213 },
214};
215
216struct platform_device tegra_i2c_device4 = {
217 .name = "tegra-i2c",
218 .id = 3,
219 .resource = i2c_resource4,
220 .num_resources = ARRAY_SIZE(i2c_resource4),
221 .dev = {
222 .platform_data = &tegra_dvc_platform_data,
223 },
224};
225
226static struct resource spi_resource1[] = {
227 [0] = {
228 .start = INT_S_LINK1,
229 .end = INT_S_LINK1,
230 .flags = IORESOURCE_IRQ,
231 },
232 [1] = {
233 .start = TEGRA_SPI1_BASE,
234 .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
235 .flags = IORESOURCE_MEM,
236 },
237};
238
239static struct resource spi_resource2[] = {
240 [0] = {
241 .start = INT_SPI_2,
242 .end = INT_SPI_2,
243 .flags = IORESOURCE_IRQ,
244 },
245 [1] = {
246 .start = TEGRA_SPI2_BASE,
247 .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
248 .flags = IORESOURCE_MEM,
249 },
250};
251
252static struct resource spi_resource3[] = {
253 [0] = {
254 .start = INT_SPI_3,
255 .end = INT_SPI_3,
256 .flags = IORESOURCE_IRQ,
257 },
258 [1] = {
259 .start = TEGRA_SPI3_BASE,
260 .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
261 .flags = IORESOURCE_MEM,
262 },
263};
264
265static struct resource spi_resource4[] = {
266 [0] = {
267 .start = INT_SPI_4,
268 .end = INT_SPI_4,
269 .flags = IORESOURCE_IRQ,
270 },
271 [1] = {
272 .start = TEGRA_SPI4_BASE,
273 .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
274 .flags = IORESOURCE_MEM,
275 },
276};
277
278struct platform_device tegra_spi_device1 = {
279 .name = "spi_tegra",
280 .id = 0,
281 .resource = spi_resource1,
282 .num_resources = ARRAY_SIZE(spi_resource1),
283 .dev = {
284 .coherent_dma_mask = 0xffffffff,
285 },
286};
287
288struct platform_device tegra_spi_device2 = {
289 .name = "spi_tegra",
290 .id = 1,
291 .resource = spi_resource2,
292 .num_resources = ARRAY_SIZE(spi_resource2),
293 .dev = {
294 .coherent_dma_mask = 0xffffffff,
295 },
296};
297
298struct platform_device tegra_spi_device3 = {
299 .name = "spi_tegra",
300 .id = 2,
301 .resource = spi_resource3,
302 .num_resources = ARRAY_SIZE(spi_resource3),
303 .dev = {
304 .coherent_dma_mask = 0xffffffff,
305 },
306};
307
308struct platform_device tegra_spi_device4 = {
309 .name = "spi_tegra",
310 .id = 3,
311 .resource = spi_resource4,
312 .num_resources = ARRAY_SIZE(spi_resource4),
313 .dev = {
314 .coherent_dma_mask = 0xffffffff,
315 },
316};
317
318
319static struct resource sdhci_resource1[] = {
320 [0] = {
321 .start = INT_SDMMC1,
322 .end = INT_SDMMC1,
323 .flags = IORESOURCE_IRQ,
324 },
325 [1] = {
326 .start = TEGRA_SDMMC1_BASE,
327 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
328 .flags = IORESOURCE_MEM,
329 },
330};
331
332static struct resource sdhci_resource2[] = {
333 [0] = {
334 .start = INT_SDMMC2,
335 .end = INT_SDMMC2,
336 .flags = IORESOURCE_IRQ,
337 },
338 [1] = {
339 .start = TEGRA_SDMMC2_BASE,
340 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct resource sdhci_resource3[] = {
346 [0] = {
347 .start = INT_SDMMC3,
348 .end = INT_SDMMC3,
349 .flags = IORESOURCE_IRQ,
350 },
351 [1] = {
352 .start = TEGRA_SDMMC3_BASE,
353 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
354 .flags = IORESOURCE_MEM,
355 },
356};
357
358static struct resource sdhci_resource4[] = {
359 [0] = {
360 .start = INT_SDMMC4,
361 .end = INT_SDMMC4,
362 .flags = IORESOURCE_IRQ,
363 },
364 [1] = {
365 .start = TEGRA_SDMMC4_BASE,
366 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
367 .flags = IORESOURCE_MEM,
368 },
369};
370
371/* board files should fill in platform_data register the devices themselvs.
372 * See board-harmony.c for an example
373 */
374struct platform_device tegra_sdhci_device1 = {
375 .name = "sdhci-tegra",
376 .id = 0,
377 .resource = sdhci_resource1,
378 .num_resources = ARRAY_SIZE(sdhci_resource1),
379};
380
381struct platform_device tegra_sdhci_device2 = {
382 .name = "sdhci-tegra",
383 .id = 1,
384 .resource = sdhci_resource2,
385 .num_resources = ARRAY_SIZE(sdhci_resource2),
386};
387
388struct platform_device tegra_sdhci_device3 = {
389 .name = "sdhci-tegra",
390 .id = 2,
391 .resource = sdhci_resource3,
392 .num_resources = ARRAY_SIZE(sdhci_resource3),
393};
394
395struct platform_device tegra_sdhci_device4 = {
396 .name = "sdhci-tegra",
397 .id = 3,
398 .resource = sdhci_resource4,
399 .num_resources = ARRAY_SIZE(sdhci_resource4),
400};
401
402static struct resource tegra_usb1_resources[] = {
403 [0] = {
404 .start = TEGRA_USB_BASE,
405 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = INT_USB,
410 .end = INT_USB,
411 .flags = IORESOURCE_IRQ,
412 },
413};
414
415static struct resource tegra_usb2_resources[] = {
416 [0] = {
417 .start = TEGRA_USB2_BASE,
418 .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
419 .flags = IORESOURCE_MEM,
420 },
421 [1] = {
422 .start = INT_USB2,
423 .end = INT_USB2,
424 .flags = IORESOURCE_IRQ,
425 },
426};
427
428static struct resource tegra_usb3_resources[] = {
429 [0] = {
430 .start = TEGRA_USB3_BASE,
431 .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
432 .flags = IORESOURCE_MEM,
433 },
434 [1] = {
435 .start = INT_USB3,
436 .end = INT_USB3,
437 .flags = IORESOURCE_IRQ,
438 },
439};
440
441struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
442 .reset_gpio = -1,
443 .clk = "cdev2",
444};
445
446struct tegra_ehci_platform_data tegra_ehci1_pdata = {
447 .operating_mode = TEGRA_USB_OTG,
448 .power_down_on_bus_suspend = 1,
449 .vbus_gpio = -1,
450};
451
452struct tegra_ehci_platform_data tegra_ehci2_pdata = {
453 .phy_config = &tegra_ehci2_ulpi_phy_config,
454 .operating_mode = TEGRA_USB_HOST,
455 .power_down_on_bus_suspend = 1,
456 .vbus_gpio = -1,
457};
458
459struct tegra_ehci_platform_data tegra_ehci3_pdata = {
460 .operating_mode = TEGRA_USB_HOST,
461 .power_down_on_bus_suspend = 1,
462 .vbus_gpio = -1,
463};
464
465static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
466
467struct platform_device tegra_ehci1_device = {
468 .name = "tegra-ehci",
469 .id = 0,
470 .dev = {
471 .dma_mask = &tegra_ehci_dmamask,
472 .coherent_dma_mask = DMA_BIT_MASK(32),
473 .platform_data = &tegra_ehci1_pdata,
474 },
475 .resource = tegra_usb1_resources,
476 .num_resources = ARRAY_SIZE(tegra_usb1_resources),
477};
478
479struct platform_device tegra_ehci2_device = {
480 .name = "tegra-ehci",
481 .id = 1,
482 .dev = {
483 .dma_mask = &tegra_ehci_dmamask,
484 .coherent_dma_mask = DMA_BIT_MASK(32),
485 .platform_data = &tegra_ehci2_pdata,
486 },
487 .resource = tegra_usb2_resources,
488 .num_resources = ARRAY_SIZE(tegra_usb2_resources),
489};
490
491struct platform_device tegra_ehci3_device = {
492 .name = "tegra-ehci",
493 .id = 2,
494 .dev = {
495 .dma_mask = &tegra_ehci_dmamask,
496 .coherent_dma_mask = DMA_BIT_MASK(32),
497 .platform_data = &tegra_ehci3_pdata,
498 },
499 .resource = tegra_usb3_resources,
500 .num_resources = ARRAY_SIZE(tegra_usb3_resources),
501};
502
503static struct resource tegra_pmu_resources[] = {
504 [0] = {
505 .start = INT_CPU0_PMU_INTR,
506 .end = INT_CPU0_PMU_INTR,
507 .flags = IORESOURCE_IRQ,
508 },
509 [1] = {
510 .start = INT_CPU1_PMU_INTR,
511 .end = INT_CPU1_PMU_INTR,
512 .flags = IORESOURCE_IRQ,
513 },
514};
515
516struct platform_device tegra_pmu_device = {
517 .name = "arm-pmu",
518 .id = -1,
519 .num_resources = ARRAY_SIZE(tegra_pmu_resources),
520 .resource = tegra_pmu_resources,
521};
522
523static struct resource tegra_uarta_resources[] = {
524 [0] = {
525 .start = TEGRA_UARTA_BASE,
526 .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
527 .flags = IORESOURCE_MEM,
528 },
529 [1] = {
530 .start = INT_UARTA,
531 .end = INT_UARTA,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
536static struct resource tegra_uartb_resources[] = {
537 [0] = {
538 .start = TEGRA_UARTB_BASE,
539 .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
543 .start = INT_UARTB,
544 .end = INT_UARTB,
545 .flags = IORESOURCE_IRQ,
546 },
547};
548
549static struct resource tegra_uartc_resources[] = {
550 [0] = {
551 .start = TEGRA_UARTC_BASE,
552 .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
553 .flags = IORESOURCE_MEM,
554 },
555 [1] = {
556 .start = INT_UARTC,
557 .end = INT_UARTC,
558 .flags = IORESOURCE_IRQ,
559 },
560};
561
562static struct resource tegra_uartd_resources[] = {
563 [0] = {
564 .start = TEGRA_UARTD_BASE,
565 .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
569 .start = INT_UARTD,
570 .end = INT_UARTD,
571 .flags = IORESOURCE_IRQ,
572 },
573};
574
575static struct resource tegra_uarte_resources[] = {
576 [0] = {
577 .start = TEGRA_UARTE_BASE,
578 .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
579 .flags = IORESOURCE_MEM,
580 },
581 [1] = {
582 .start = INT_UARTE,
583 .end = INT_UARTE,
584 .flags = IORESOURCE_IRQ,
585 },
586};
587
588struct platform_device tegra_uarta_device = {
589 .name = "tegra_uart",
590 .id = 0,
591 .num_resources = ARRAY_SIZE(tegra_uarta_resources),
592 .resource = tegra_uarta_resources,
593 .dev = {
594 .coherent_dma_mask = DMA_BIT_MASK(32),
595 },
596};
597
598struct platform_device tegra_uartb_device = {
599 .name = "tegra_uart",
600 .id = 1,
601 .num_resources = ARRAY_SIZE(tegra_uartb_resources),
602 .resource = tegra_uartb_resources,
603 .dev = {
604 .coherent_dma_mask = DMA_BIT_MASK(32),
605 },
606};
607
608struct platform_device tegra_uartc_device = {
609 .name = "tegra_uart",
610 .id = 2,
611 .num_resources = ARRAY_SIZE(tegra_uartc_resources),
612 .resource = tegra_uartc_resources,
613 .dev = {
614 .coherent_dma_mask = DMA_BIT_MASK(32),
615 },
616};
617
618struct platform_device tegra_uartd_device = {
619 .name = "tegra_uart",
620 .id = 3,
621 .num_resources = ARRAY_SIZE(tegra_uartd_resources),
622 .resource = tegra_uartd_resources,
623 .dev = {
624 .coherent_dma_mask = DMA_BIT_MASK(32),
625 },
626};
627
628struct platform_device tegra_uarte_device = {
629 .name = "tegra_uart",
630 .id = 4,
631 .num_resources = ARRAY_SIZE(tegra_uarte_resources),
632 .resource = tegra_uarte_resources,
633 .dev = {
634 .coherent_dma_mask = DMA_BIT_MASK(32),
635 },
636};
637
638static struct resource i2s_resource1[] = {
639 [0] = {
640 .start = INT_I2S1,
641 .end = INT_I2S1,
642 .flags = IORESOURCE_IRQ
643 },
644 [1] = {
645 .start = TEGRA_DMA_REQ_SEL_I2S_1,
646 .end = TEGRA_DMA_REQ_SEL_I2S_1,
647 .flags = IORESOURCE_DMA
648 },
649 [2] = {
650 .start = TEGRA_I2S1_BASE,
651 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
652 .flags = IORESOURCE_MEM
653 }
654};
655
656static struct resource i2s_resource2[] = {
657 [0] = {
658 .start = INT_I2S2,
659 .end = INT_I2S2,
660 .flags = IORESOURCE_IRQ
661 },
662 [1] = {
663 .start = TEGRA_DMA_REQ_SEL_I2S2_1,
664 .end = TEGRA_DMA_REQ_SEL_I2S2_1,
665 .flags = IORESOURCE_DMA
666 },
667 [2] = {
668 .start = TEGRA_I2S2_BASE,
669 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
670 .flags = IORESOURCE_MEM
671 }
672};
673
674struct platform_device tegra_i2s_device1 = {
675 .name = "tegra20-i2s",
676 .id = 0,
677 .resource = i2s_resource1,
678 .num_resources = ARRAY_SIZE(i2s_resource1),
679};
680
681struct platform_device tegra_i2s_device2 = {
682 .name = "tegra20-i2s",
683 .id = 1,
684 .resource = i2s_resource2,
685 .num_resources = ARRAY_SIZE(i2s_resource2),
686};
687
688static struct resource tegra_das_resources[] = {
689 [0] = {
690 .start = TEGRA_APB_MISC_DAS_BASE,
691 .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
692 .flags = IORESOURCE_MEM,
693 },
694};
695
696struct platform_device tegra_das_device = {
697 .name = "tegra20-das",
698 .id = -1,
699 .num_resources = ARRAY_SIZE(tegra_das_resources),
700 .resource = tegra_das_resources,
701};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 05:03:02 -0500