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-rw-r--r--arch/arm/mach-tegra/common.c115
1 files changed, 0 insertions, 115 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
deleted file mode 100644
index 94a119a35af8..000000000000
--- a/arch/arm/mach-tegra/common.c
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@@ -1,115 +0,0 @@
1/*
2 * arch/arm/mach-tegra/common.c
3 *
4 * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5 * Copyright (C) 2010 Google, Inc.
6 *
7 * Author:
8 * Colin Cross <ccross@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/delay.h>
25#include <linux/reboot.h>
26#include <linux/irqchip.h>
27#include <linux/clk-provider.h>
28
29#include <asm/hardware/cache-l2x0.h>
30
31#include "board.h"
32#include "common.h"
33#include "cpuidle.h"
34#include "fuse.h"
35#include "iomap.h"
36#include "irq.h"
37#include "pmc.h"
38#include "apbio.h"
39#include "sleep.h"
40#include "pm.h"
41#include "reset.h"
42
43/*
44 * Storage for debug-macro.S's state.
45 *
46 * This must be in .data not .bss so that it gets initialized each time the
47 * kernel is loaded. The data is declared here rather than debug-macro.S so
48 * that multiple inclusions of debug-macro.S point at the same data.
49 */
50u32 tegra_uart_config[4] = {
51 /* Debug UART initialization required */
52 1,
53 /* Debug UART physical address */
54 0,
55 /* Debug UART virtual address */
56 0,
57 /* Scratch space for debug macro */
58 0,
59};
60
61#ifdef CONFIG_OF
62void __init tegra_dt_init_irq(void)
63{
64 of_clk_init(NULL);
65 tegra_pmc_init();
66 tegra_init_irq();
67 irqchip_init();
68 tegra_legacy_irq_syscore_init();
69}
70#endif
71
72void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
73{
74 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
75 u32 reg;
76
77 reg = readl_relaxed(reset);
78 reg |= 0x10;
79 writel_relaxed(reg, reset);
80}
81
82static void __init tegra_init_cache(void)
83{
84#ifdef CONFIG_CACHE_L2X0
85 int ret;
86 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
87 u32 aux_ctrl, cache_type;
88
89 cache_type = readl(p + L2X0_CACHE_TYPE);
90 aux_ctrl = (cache_type & 0x700) << (17-8);
91 aux_ctrl |= 0x7C400001;
92
93 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
94 if (!ret)
95 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
96#endif
97
98}
99
100void __init tegra_init_early(void)
101{
102 tegra_cpu_reset_handler_init();
103 tegra_apb_io_init();
104 tegra_init_fuse();
105 tegra_init_cache();
106 tegra_powergate_init();
107 tegra_hotplug_init();
108}
109
110void __init tegra_init_late(void)
111{
112 tegra_init_suspend();
113 tegra_cpuidle_init();
114 tegra_powergate_debugfs_init();
115}