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-rw-r--r--arch/arm/mach-tegra/common.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f688daa74978..11a74db51e5d 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -36,6 +36,7 @@
36#include "pmc.h" 36#include "pmc.h"
37#include "apbio.h" 37#include "apbio.h"
38#include "sleep.h" 38#include "sleep.h"
39#include "pm.h"
39 40
40/* 41/*
41 * Storage for debug-macro.S's state. 42 * Storage for debug-macro.S's state.
@@ -104,25 +105,30 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
104 { "clk_m", NULL, 0, true }, 105 { "clk_m", NULL, 0, true },
105 { "pll_p", "clk_m", 408000000, true }, 106 { "pll_p", "clk_m", 408000000, true },
106 { "pll_p_out1", "pll_p", 9600000, true }, 107 { "pll_p_out1", "pll_p", 9600000, true },
108 { "pll_p_out4", "pll_p", 102000000, true },
109 { "sclk", "pll_p_out4", 102000000, true },
110 { "hclk", "sclk", 102000000, true },
111 { "pclk", "hclk", 51000000, true },
112 { "csite", NULL, 0, true },
107 { NULL, NULL, 0, 0}, 113 { NULL, NULL, 0, 0},
108}; 114};
109#endif 115#endif
110 116
111 117
112static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) 118static void __init tegra_init_cache(void)
113{ 119{
114#ifdef CONFIG_CACHE_L2X0 120#ifdef CONFIG_CACHE_L2X0
121 int ret;
115 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; 122 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
116 u32 aux_ctrl, cache_type; 123 u32 aux_ctrl, cache_type;
117 124
118 writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
119 writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
120
121 cache_type = readl(p + L2X0_CACHE_TYPE); 125 cache_type = readl(p + L2X0_CACHE_TYPE);
122 aux_ctrl = (cache_type & 0x700) << (17-8); 126 aux_ctrl = (cache_type & 0x700) << (17-8);
123 aux_ctrl |= 0x6C000001; 127 aux_ctrl |= 0x7C400001;
124 128
125 l2x0_init(p, aux_ctrl, 0x8200c3fe); 129 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
130 if (!ret)
131 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
126#endif 132#endif
127 133
128} 134}
@@ -134,7 +140,7 @@ void __init tegra20_init_early(void)
134 tegra_init_fuse(); 140 tegra_init_fuse();
135 tegra2_init_clocks(); 141 tegra2_init_clocks();
136 tegra_clk_init_from_table(tegra20_clk_init_table); 142 tegra_clk_init_from_table(tegra20_clk_init_table);
137 tegra_init_cache(0x331, 0x441); 143 tegra_init_cache();
138 tegra_pmc_init(); 144 tegra_pmc_init();
139 tegra_powergate_init(); 145 tegra_powergate_init();
140 tegra20_hotplug_init(); 146 tegra20_hotplug_init();
@@ -147,7 +153,7 @@ void __init tegra30_init_early(void)
147 tegra_init_fuse(); 153 tegra_init_fuse();
148 tegra30_init_clocks(); 154 tegra30_init_clocks();
149 tegra_clk_init_from_table(tegra30_clk_init_table); 155 tegra_clk_init_from_table(tegra30_clk_init_table);
150 tegra_init_cache(0x441, 0x551); 156 tegra_init_cache();
151 tegra_pmc_init(); 157 tegra_pmc_init();
152 tegra_powergate_init(); 158 tegra_powergate_init();
153 tegra30_hotplug_init(); 159 tegra30_hotplug_init();