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-rw-r--r--arch/arm/mach-tegra/common.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 039a514b61ef..7c91e2b9d643 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -19,13 +19,17 @@
19 19
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/clk.h>
23#include <linux/delay.h>
22 24
23#include <asm/hardware/cache-l2x0.h> 25#include <asm/hardware/cache-l2x0.h>
24 26
25#include <mach/iomap.h> 27#include <mach/iomap.h>
28#include <mach/dma.h>
26 29
27#include "board.h" 30#include "board.h"
28#include "clock.h" 31#include "clock.h"
32#include "fuse.h"
29 33
30static __initdata struct tegra_clk_init_table common_clk_init_table[] = { 34static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
31 /* name parent rate enabled */ 35 /* name parent rate enabled */
@@ -35,8 +39,8 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
35 { "pll_p_out2", "pll_p", 48000000, true }, 39 { "pll_p_out2", "pll_p", 48000000, true },
36 { "pll_p_out3", "pll_p", 72000000, true }, 40 { "pll_p_out3", "pll_p", 72000000, true },
37 { "pll_p_out4", "pll_p", 108000000, true }, 41 { "pll_p_out4", "pll_p", 108000000, true },
38 { "sys", "pll_p_out4", 108000000, true }, 42 { "sclk", "pll_p_out4", 108000000, true },
39 { "hclk", "sys", 108000000, true }, 43 { "hclk", "sclk", 108000000, true },
40 { "pclk", "hclk", 54000000, true }, 44 { "pclk", "hclk", 54000000, true },
41 { NULL, NULL, 0, 0}, 45 { NULL, NULL, 0, 0},
42}; 46};
@@ -51,11 +55,16 @@ void __init tegra_init_cache(void)
51 55
52 l2x0_init(p, 0x6C080001, 0x8200c3fe); 56 l2x0_init(p, 0x6C080001, 0x8200c3fe);
53#endif 57#endif
58
54} 59}
55 60
56void __init tegra_common_init(void) 61void __init tegra_common_init(void)
57{ 62{
63 tegra_init_fuse();
58 tegra_init_clock(); 64 tegra_init_clock();
59 tegra_clk_init_from_table(common_clk_init_table); 65 tegra_clk_init_from_table(common_clk_init_table);
60 tegra_init_cache(); 66 tegra_init_cache();
67#ifdef CONFIG_TEGRA_SYSTEM_DMA
68 tegra_dma_init();
69#endif
61} 70}