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-rw-r--r--arch/arm/mach-tegra/common.c27
1 files changed, 22 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 690b888be506..0fafb60497a5 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/arm/mach-tegra/board-harmony.c 2 * arch/arm/mach-tegra/common.c
3 * 3 *
4 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2010 Google, Inc.
5 * 5 *
@@ -21,8 +21,10 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of_irq.h>
24 25
25#include <asm/hardware/cache-l2x0.h> 26#include <asm/hardware/cache-l2x0.h>
27#include <asm/hardware/gic.h>
26 28
27#include <mach/iomap.h> 29#include <mach/iomap.h>
28#include <mach/system.h> 30#include <mach/system.h>
@@ -33,6 +35,17 @@
33 35
34void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; 36void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
35 37
38static const struct of_device_id tegra_dt_irq_match[] __initconst = {
39 { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
40 { }
41};
42
43void __init tegra_dt_init_irq(void)
44{
45 tegra_init_irq();
46 of_irq_init(tegra_dt_irq_match);
47}
48
36void tegra_assert_system_reset(char mode, const char *cmd) 49void tegra_assert_system_reset(char mode, const char *cmd)
37{ 50{
38 void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); 51 void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
@@ -44,7 +57,8 @@ void tegra_assert_system_reset(char mode, const char *cmd)
44 writel_relaxed(reg, reset); 57 writel_relaxed(reg, reset);
45} 58}
46 59
47static __initdata struct tegra_clk_init_table common_clk_init_table[] = { 60#ifdef CONFIG_ARCH_TEGRA_2x_SOC
61static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
48 /* name parent rate enabled */ 62 /* name parent rate enabled */
49 { "clk_m", NULL, 0, true }, 63 { "clk_m", NULL, 0, true },
50 { "pll_p", "clk_m", 216000000, true }, 64 { "pll_p", "clk_m", 216000000, true },
@@ -60,6 +74,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
60 { "cpu", NULL, 0, true }, 74 { "cpu", NULL, 0, true },
61 { NULL, NULL, 0, 0}, 75 { NULL, NULL, 0, 0},
62}; 76};
77#endif
63 78
64static void __init tegra_init_cache(void) 79static void __init tegra_init_cache(void)
65{ 80{
@@ -74,10 +89,12 @@ static void __init tegra_init_cache(void)
74 89
75} 90}
76 91
77void __init tegra_init_early(void) 92#ifdef CONFIG_ARCH_TEGRA_2x_SOC
93void __init tegra20_init_early(void)
78{ 94{
79 tegra_init_fuse(); 95 tegra_init_fuse();
80 tegra_init_clock(); 96 tegra2_init_clocks();
81 tegra_clk_init_from_table(common_clk_init_table); 97 tegra_clk_init_from_table(tegra20_clk_init_table);
82 tegra_init_cache(); 98 tegra_init_cache();
83} 99}
100#endif