diff options
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r-- | arch/arm/mach-tegra/common.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 7c91e2b9d643..d5e3f89b05af 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
@@ -25,12 +25,25 @@ | |||
25 | #include <asm/hardware/cache-l2x0.h> | 25 | #include <asm/hardware/cache-l2x0.h> |
26 | 26 | ||
27 | #include <mach/iomap.h> | 27 | #include <mach/iomap.h> |
28 | #include <mach/dma.h> | 28 | #include <mach/system.h> |
29 | 29 | ||
30 | #include "board.h" | 30 | #include "board.h" |
31 | #include "clock.h" | 31 | #include "clock.h" |
32 | #include "fuse.h" | 32 | #include "fuse.h" |
33 | 33 | ||
34 | void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; | ||
35 | |||
36 | void tegra_assert_system_reset(char mode, const char *cmd) | ||
37 | { | ||
38 | void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); | ||
39 | u32 reg; | ||
40 | |||
41 | /* use *_related to avoid spinlock since caches are off */ | ||
42 | reg = readl_relaxed(reset); | ||
43 | reg |= 0x04; | ||
44 | writel_relaxed(reg, reset); | ||
45 | } | ||
46 | |||
34 | static __initdata struct tegra_clk_init_table common_clk_init_table[] = { | 47 | static __initdata struct tegra_clk_init_table common_clk_init_table[] = { |
35 | /* name parent rate enabled */ | 48 | /* name parent rate enabled */ |
36 | { "clk_m", NULL, 0, true }, | 49 | { "clk_m", NULL, 0, true }, |
@@ -42,6 +55,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { | |||
42 | { "sclk", "pll_p_out4", 108000000, true }, | 55 | { "sclk", "pll_p_out4", 108000000, true }, |
43 | { "hclk", "sclk", 108000000, true }, | 56 | { "hclk", "sclk", 108000000, true }, |
44 | { "pclk", "hclk", 54000000, true }, | 57 | { "pclk", "hclk", 54000000, true }, |
58 | { "csite", NULL, 0, true }, | ||
59 | { "emc", NULL, 0, true }, | ||
60 | { "cpu", NULL, 0, true }, | ||
45 | { NULL, NULL, 0, 0}, | 61 | { NULL, NULL, 0, 0}, |
46 | }; | 62 | }; |
47 | 63 | ||
@@ -50,21 +66,18 @@ void __init tegra_init_cache(void) | |||
50 | #ifdef CONFIG_CACHE_L2X0 | 66 | #ifdef CONFIG_CACHE_L2X0 |
51 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | 67 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; |
52 | 68 | ||
53 | writel(0x331, p + L2X0_TAG_LATENCY_CTRL); | 69 | writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); |
54 | writel(0x441, p + L2X0_DATA_LATENCY_CTRL); | 70 | writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); |
55 | 71 | ||
56 | l2x0_init(p, 0x6C080001, 0x8200c3fe); | 72 | l2x0_init(p, 0x6C080001, 0x8200c3fe); |
57 | #endif | 73 | #endif |
58 | 74 | ||
59 | } | 75 | } |
60 | 76 | ||
61 | void __init tegra_common_init(void) | 77 | void __init tegra_init_early(void) |
62 | { | 78 | { |
63 | tegra_init_fuse(); | 79 | tegra_init_fuse(); |
64 | tegra_init_clock(); | 80 | tegra_init_clock(); |
65 | tegra_clk_init_from_table(common_clk_init_table); | 81 | tegra_clk_init_from_table(common_clk_init_table); |
66 | tegra_init_cache(); | 82 | tegra_init_cache(); |
67 | #ifdef CONFIG_TEGRA_SYSTEM_DMA | ||
68 | tegra_dma_init(); | ||
69 | #endif | ||
70 | } | 83 | } |