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-rw-r--r--arch/arm/mach-tegra/clock.c25
1 files changed, 4 insertions, 21 deletions
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca9..8337068a4abe 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,35 +387,18 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
387 387
388void tegra_periph_reset_deassert(struct clk *c) 388void tegra_periph_reset_deassert(struct clk *c)
389{ 389{
390 tegra2_periph_reset_deassert(c); 390 BUG_ON(!c->ops->reset);
391 c->ops->reset(c, false);
391} 392}
392EXPORT_SYMBOL(tegra_periph_reset_deassert); 393EXPORT_SYMBOL(tegra_periph_reset_deassert);
393 394
394void tegra_periph_reset_assert(struct clk *c) 395void tegra_periph_reset_assert(struct clk *c)
395{ 396{
396 tegra2_periph_reset_assert(c); 397 BUG_ON(!c->ops->reset);
398 c->ops->reset(c, true);
397} 399}
398EXPORT_SYMBOL(tegra_periph_reset_assert); 400EXPORT_SYMBOL(tegra_periph_reset_assert);
399 401
400void __init tegra_init_clock(void)
401{
402 tegra2_init_clocks();
403}
404
405/*
406 * The SDMMC controllers have extra bits in the clock source register that
407 * adjust the delay between the clock and data to compenstate for delays
408 * on the PCB.
409 */
410void tegra_sdmmc_tap_delay(struct clk *c, int delay)
411{
412 unsigned long flags;
413
414 spin_lock_irqsave(&c->spinlock, flags);
415 tegra2_sdmmc_tap_delay(c, delay);
416 spin_unlock_irqrestore(&c->spinlock, flags);
417}
418
419#ifdef CONFIG_DEBUG_FS 402#ifdef CONFIG_DEBUG_FS
420 403
421static int __clk_lock_all_spinlocks(void) 404static int __clk_lock_all_spinlocks(void)