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Diffstat (limited to 'arch/arm/mach-tegra/board-dt-tegra20.c')
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra20.c76
1 files changed, 10 insertions, 66 deletions
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 734d9cc87f2e..a0edf2510280 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -15,6 +15,7 @@
15 * 15 *
16 */ 16 */
17 17
18#include <linux/clocksource.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -25,7 +26,6 @@
25#include <linux/of.h> 26#include <linux/of.h>
26#include <linux/of_address.h> 27#include <linux/of_address.h>
27#include <linux/of_fdt.h> 28#include <linux/of_fdt.h>
28#include <linux/of_irq.h>
29#include <linux/of_platform.h> 29#include <linux/of_platform.h>
30#include <linux/pda_power.h> 30#include <linux/pda_power.h>
31#include <linux/platform_data/tegra_usb.h> 31#include <linux/platform_data/tegra_usb.h>
@@ -34,106 +34,51 @@
34#include <linux/i2c-tegra.h> 34#include <linux/i2c-tegra.h>
35#include <linux/usb/tegra_usb_phy.h> 35#include <linux/usb/tegra_usb_phy.h>
36 36
37#include <asm/hardware/gic.h>
38#include <asm/mach-types.h> 37#include <asm/mach-types.h>
39#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 39#include <asm/mach/time.h>
41#include <asm/setup.h> 40#include <asm/setup.h>
42 41
43#include "board.h" 42#include "board.h"
44#include "clock.h"
45#include "common.h" 43#include "common.h"
46#include "iomap.h" 44#include "iomap.h"
47 45
48struct tegra_ehci_platform_data tegra_ehci1_pdata = { 46static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
49 .operating_mode = TEGRA_USB_OTG, 47 .operating_mode = TEGRA_USB_OTG,
50 .power_down_on_bus_suspend = 1, 48 .power_down_on_bus_suspend = 1,
51 .vbus_gpio = -1, 49 .vbus_gpio = -1,
52}; 50};
53 51
54struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = { 52static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
55 .reset_gpio = -1, 53 .reset_gpio = -1,
56 .clk = "cdev2", 54 .clk = "cdev2",
57}; 55};
58 56
59struct tegra_ehci_platform_data tegra_ehci2_pdata = { 57static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
60 .phy_config = &tegra_ehci2_ulpi_phy_config, 58 .phy_config = &tegra_ehci2_ulpi_phy_config,
61 .operating_mode = TEGRA_USB_HOST, 59 .operating_mode = TEGRA_USB_HOST,
62 .power_down_on_bus_suspend = 1, 60 .power_down_on_bus_suspend = 1,
63 .vbus_gpio = -1, 61 .vbus_gpio = -1,
64}; 62};
65 63
66struct tegra_ehci_platform_data tegra_ehci3_pdata = { 64static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
67 .operating_mode = TEGRA_USB_HOST, 65 .operating_mode = TEGRA_USB_HOST,
68 .power_down_on_bus_suspend = 1, 66 .power_down_on_bus_suspend = 1,
69 .vbus_gpio = -1, 67 .vbus_gpio = -1,
70}; 68};
71 69
72struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { 70static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
73 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), 71 OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0",
74 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
75 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
76 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
77 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
78 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
79 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
80 OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
81 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
82 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
83 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
84 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
85 &tegra_ehci1_pdata), 72 &tegra_ehci1_pdata),
86 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", 73 OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1",
87 &tegra_ehci2_pdata), 74 &tegra_ehci2_pdata),
88 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", 75 OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2",
89 &tegra_ehci3_pdata), 76 &tegra_ehci3_pdata),
90 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
91 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
92 OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
93 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
94 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
95 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
96 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
97 OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
98 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
99 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
100 OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
101 OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
102 OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
103 {} 77 {}
104}; 78};
105 79
106static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
107 /* name parent rate enabled */
108 { "uarta", "pll_p", 216000000, true },
109 { "uartd", "pll_p", 216000000, true },
110 { "usbd", "clk_m", 12000000, false },
111 { "usb2", "clk_m", 12000000, false },
112 { "usb3", "clk_m", 12000000, false },
113 { "pll_a", "pll_p_out1", 56448000, true },
114 { "pll_a_out0", "pll_a", 11289600, true },
115 { "cdev1", NULL, 0, true },
116 { "blink", "clk_32k", 32768, true },
117 { "i2s1", "pll_a_out0", 11289600, false},
118 { "i2s2", "pll_a_out0", 11289600, false},
119 { "sdmmc1", "pll_p", 48000000, false},
120 { "sdmmc3", "pll_p", 48000000, false},
121 { "sdmmc4", "pll_p", 48000000, false},
122 { "spi", "pll_p", 20000000, false },
123 { "sbc1", "pll_p", 100000000, false },
124 { "sbc2", "pll_p", 100000000, false },
125 { "sbc3", "pll_p", 100000000, false },
126 { "sbc4", "pll_p", 100000000, false },
127 { "host1x", "pll_c", 150000000, false },
128 { "disp1", "pll_p", 600000000, false },
129 { "disp2", "pll_p", 600000000, false },
130 { NULL, NULL, 0, 0},
131};
132
133static void __init tegra_dt_init(void) 80static void __init tegra_dt_init(void)
134{ 81{
135 tegra_clk_init_from_table(tegra_dt_clk_init_table);
136
137 /* 82 /*
138 * Finished with the static registrations now; fill in the missing 83 * Finished with the static registrations now; fill in the missing
139 * devices 84 * devices
@@ -202,8 +147,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
202 .smp = smp_ops(tegra_smp_ops), 147 .smp = smp_ops(tegra_smp_ops),
203 .init_early = tegra20_init_early, 148 .init_early = tegra20_init_early,
204 .init_irq = tegra_dt_init_irq, 149 .init_irq = tegra_dt_init_irq,
205 .handle_irq = gic_handle_irq, 150 .init_time = clocksource_of_init,
206 .timer = &tegra_sys_timer,
207 .init_machine = tegra_dt_init, 151 .init_machine = tegra_dt_init,
208 .init_late = tegra_dt_init_late, 152 .init_late = tegra_dt_init_late,
209 .restart = tegra_assert_system_reset, 153 .restart = tegra_assert_system_reset,
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 02:59:05 -0500