diff options
Diffstat (limited to 'arch/arm/mach-spear6xx')
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/debug-macro.S | 14 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/entry-macro.S | 55 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/generic.h | 45 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/gpio.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/hardware.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/io.h | 20 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/irqs.h | 96 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/memory.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/misc_regs.h | 173 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/spear.h | 173 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/spear600.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/system.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/timex.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/uncompress.h | 19 | ||||
-rw-r--r-- | arch/arm/mach-spear6xx/include/mach/vmalloc.h | 19 |
15 files changed, 732 insertions, 0 deletions
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S new file mode 100644 index 000000000000..0f3ea39edd96 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/debug-macro.S | |||
@@ -0,0 +1,14 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/debug-macro.S | ||
3 | * | ||
4 | * Debugging macro include header for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S new file mode 100644 index 000000000000..9eaecaeafcf0 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | #include <mach/spear.h> | ||
16 | #include <asm/hardware/vic.h> | ||
17 | |||
18 | .macro disable_fiq | ||
19 | .endm | ||
20 | |||
21 | .macro get_irqnr_preamble, base, tmp | ||
22 | .endm | ||
23 | |||
24 | .macro arch_ret_to_user, tmp1, tmp2 | ||
25 | .endm | ||
26 | |||
27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
28 | ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE | ||
29 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status | ||
30 | mov \irqnr, #0 | ||
31 | teq \irqstat, #0 | ||
32 | bne 1001f | ||
33 | ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE | ||
34 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status | ||
35 | teq \irqstat, #0 | ||
36 | beq 1002f @ this will set/reset | ||
37 | @ zero register | ||
38 | mov \irqnr, #32 | ||
39 | 1001: | ||
40 | /* | ||
41 | * Following code will find bit position of least significang | ||
42 | * bit set in irqstat, using following equation | ||
43 | * least significant bit set in n = (n & ~(n-1)) | ||
44 | */ | ||
45 | sub \tmp, \irqstat, #1 @ tmp = irqstat - 1 | ||
46 | mvn \tmp, \tmp @ tmp = ~tmp | ||
47 | and \irqstat, \irqstat, \tmp @ irqstat &= tmp | ||
48 | /* Now, irqstat is = bit no. of 1st bit set in vic irq status */ | ||
49 | clz \tmp, \irqstat @ tmp = leading zeros | ||
50 | |||
51 | rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1 | ||
52 | add \irqnr, \irqnr, \tmp | ||
53 | |||
54 | 1002: /* EQ will be set if no irqs pending */ | ||
55 | .endm | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h new file mode 100644 index 000000000000..16205a538756 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/generic.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/generic.h | ||
3 | * | ||
4 | * SPEAr6XX machine family specific generic header file | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_GENERIC_H | ||
15 | #define __MACH_GENERIC_H | ||
16 | |||
17 | #include <asm/mach/time.h> | ||
18 | #include <asm/mach/map.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/amba/bus.h> | ||
22 | |||
23 | /* | ||
24 | * Each GPT has 2 timer channels | ||
25 | * Following GPT channels will be used as clock source and clockevent | ||
26 | */ | ||
27 | #define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE | ||
28 | #define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 | ||
29 | #define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 | ||
30 | |||
31 | /* Add spear6xx family device structure declarations here */ | ||
32 | extern struct amba_device gpio_device[]; | ||
33 | extern struct amba_device uart_device[]; | ||
34 | extern struct sys_timer spear_sys_timer; | ||
35 | |||
36 | /* Add spear6xx family function declarations here */ | ||
37 | void __init spear6xx_map_io(void); | ||
38 | void __init spear6xx_init_irq(void); | ||
39 | void __init spear6xx_init(void); | ||
40 | void __init spear600_init(void); | ||
41 | void __init clk_init(void); | ||
42 | |||
43 | /* Add spear600 machine device structure declarations here */ | ||
44 | |||
45 | #endif /* __MACH_GENERIC_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h new file mode 100644 index 000000000000..3a789dbb69f7 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/gpio.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/gpio.h | ||
3 | * | ||
4 | * GPIO macros for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Viresh Kumar<viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_GPIO_H | ||
15 | #define __MACH_GPIO_H | ||
16 | |||
17 | #include <plat/gpio.h> | ||
18 | |||
19 | #endif /* __MACH_GPIO_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h new file mode 100644 index 000000000000..7545116deca9 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/hardware.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/hardware.h | ||
3 | * | ||
4 | * Hardware definitions for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_HARDWARE_H | ||
15 | #define __MACH_HARDWARE_H | ||
16 | |||
17 | /* Vitual to physical translation of statically mapped space */ | ||
18 | #define IO_ADDRESS(x) (x | 0xF0000000) | ||
19 | |||
20 | #endif /* __MACH_HARDWARE_H */ | ||
21 | |||
diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h new file mode 100644 index 000000000000..fb7c106cea94 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/io.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/io.h | ||
3 | * | ||
4 | * IO definitions for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_IO_H | ||
15 | #define __MACH_IO_H | ||
16 | |||
17 | #include <plat/io.h> | ||
18 | |||
19 | #endif /* __MACH_IO_H */ | ||
20 | |||
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h new file mode 100644 index 000000000000..08a3abced750 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/irqs.h | |||
@@ -0,0 +1,96 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/irqs.h | ||
3 | * | ||
4 | * IRQ helper macros for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_IRQS_H | ||
15 | #define __MACH_IRQS_H | ||
16 | |||
17 | /* IRQ definitions */ | ||
18 | /* VIC 1 */ | ||
19 | #define IRQ_INTRCOMM_SW_IRQ 0 | ||
20 | #define IRQ_INTRCOMM_CPU_1 1 | ||
21 | #define IRQ_INTRCOMM_CPU_2 2 | ||
22 | #define IRQ_INTRCOMM_RAS2A11_1 3 | ||
23 | #define IRQ_INTRCOMM_RAS2A11_2 4 | ||
24 | #define IRQ_INTRCOMM_RAS2A12_1 5 | ||
25 | #define IRQ_INTRCOMM_RAS2A12_2 6 | ||
26 | #define IRQ_GEN_RAS_0 7 | ||
27 | #define IRQ_GEN_RAS_1 8 | ||
28 | #define IRQ_GEN_RAS_2 9 | ||
29 | #define IRQ_GEN_RAS_3 10 | ||
30 | #define IRQ_GEN_RAS_4 11 | ||
31 | #define IRQ_GEN_RAS_5 12 | ||
32 | #define IRQ_GEN_RAS_6 13 | ||
33 | #define IRQ_GEN_RAS_7 14 | ||
34 | #define IRQ_GEN_RAS_8 15 | ||
35 | #define IRQ_CPU_GPT1_1 16 | ||
36 | #define IRQ_CPU_GPT1_2 17 | ||
37 | #define IRQ_LOCAL_GPIO 18 | ||
38 | #define IRQ_PLL_UNLOCK 19 | ||
39 | #define IRQ_JPEG 20 | ||
40 | #define IRQ_FSMC 21 | ||
41 | #define IRQ_IRDA 22 | ||
42 | #define IRQ_RESERVED 23 | ||
43 | #define IRQ_UART_0 24 | ||
44 | #define IRQ_UART_1 25 | ||
45 | #define IRQ_SSP_1 26 | ||
46 | #define IRQ_SSP_2 27 | ||
47 | #define IRQ_I2C 28 | ||
48 | #define IRQ_GEN_RAS_9 29 | ||
49 | #define IRQ_GEN_RAS_10 30 | ||
50 | #define IRQ_GEN_RAS_11 31 | ||
51 | |||
52 | /* VIC 2 */ | ||
53 | #define IRQ_APPL_GPT1_1 32 | ||
54 | #define IRQ_APPL_GPT1_2 33 | ||
55 | #define IRQ_APPL_GPT2_1 34 | ||
56 | #define IRQ_APPL_GPT2_2 35 | ||
57 | #define IRQ_APPL_GPIO 36 | ||
58 | #define IRQ_APPL_SSP 37 | ||
59 | #define IRQ_APPL_ADC 38 | ||
60 | #define IRQ_APPL_RESERVED 39 | ||
61 | #define IRQ_AHB_EXP_MASTER 40 | ||
62 | #define IRQ_DDR_CONTROLLER 41 | ||
63 | #define IRQ_BASIC_DMA 42 | ||
64 | #define IRQ_BASIC_RESERVED1 43 | ||
65 | #define IRQ_BASIC_SMI 44 | ||
66 | #define IRQ_BASIC_CLCD 45 | ||
67 | #define IRQ_EXP_AHB_1 46 | ||
68 | #define IRQ_EXP_AHB_2 47 | ||
69 | #define IRQ_BASIC_GPT1_1 48 | ||
70 | #define IRQ_BASIC_GPT1_2 49 | ||
71 | #define IRQ_BASIC_RTC 50 | ||
72 | #define IRQ_BASIC_GPIO 51 | ||
73 | #define IRQ_BASIC_WDT 52 | ||
74 | #define IRQ_BASIC_RESERVED 53 | ||
75 | #define IRQ_AHB_EXP_SLAVE 54 | ||
76 | #define IRQ_GMAC_1 55 | ||
77 | #define IRQ_GMAC_2 56 | ||
78 | #define IRQ_USB_DEV 57 | ||
79 | #define IRQ_USB_H_OHCI_0 58 | ||
80 | #define IRQ_USB_H_EHCI_0 59 | ||
81 | #define IRQ_USB_H_OHCI_1 60 | ||
82 | #define IRQ_USB_H_EHCI_1 61 | ||
83 | #define IRQ_EXP_AHB_3 62 | ||
84 | #define IRQ_EXP_AHB_4 63 | ||
85 | |||
86 | #define IRQ_VIC_END 64 | ||
87 | |||
88 | #define SPEAR_GPIO_INT_BASE IRQ_VIC_END | ||
89 | #define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE | ||
90 | #define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) | ||
91 | #define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) | ||
92 | #define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) | ||
93 | #define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) | ||
94 | #define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) | ||
95 | |||
96 | #endif /* __MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/memory.h b/arch/arm/mach-spear6xx/include/mach/memory.h new file mode 100644 index 000000000000..781f088fc228 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/memory.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/memory.h | ||
3 | * | ||
4 | * Memory map for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_MEMORY_H | ||
15 | #define __MACH_MEMORY_H | ||
16 | |||
17 | #include <plat/memory.h> | ||
18 | |||
19 | #endif /* __MACH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h new file mode 100644 index 000000000000..03908036b0d0 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/misc_regs.h | ||
3 | * | ||
4 | * Miscellaneous registers definitions for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Viresh Kumar<viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_MISC_REGS_H | ||
15 | #define __MACH_MISC_REGS_H | ||
16 | |||
17 | #include <mach/spear.h> | ||
18 | |||
19 | #define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE | ||
20 | |||
21 | #define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) | ||
22 | #define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) | ||
23 | #define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) | ||
24 | #define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) | ||
25 | #define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) | ||
26 | #define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) | ||
27 | /* PLL_CTR register masks */ | ||
28 | #define PLL_ENABLE 2 | ||
29 | #define PLL_MODE_SHIFT 4 | ||
30 | #define PLL_MODE_MASK 0x3 | ||
31 | #define PLL_MODE_NORMAL 0 | ||
32 | #define PLL_MODE_FRACTION 1 | ||
33 | #define PLL_MODE_DITH_DSB 2 | ||
34 | #define PLL_MODE_DITH_SSB 3 | ||
35 | |||
36 | #define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) | ||
37 | /* PLL FRQ register masks */ | ||
38 | #define PLL_DIV_N_SHIFT 0 | ||
39 | #define PLL_DIV_N_MASK 0xFF | ||
40 | #define PLL_DIV_P_SHIFT 8 | ||
41 | #define PLL_DIV_P_MASK 0x7 | ||
42 | #define PLL_NORM_FDBK_M_SHIFT 24 | ||
43 | #define PLL_NORM_FDBK_M_MASK 0xFF | ||
44 | #define PLL_DITH_FDBK_M_SHIFT 16 | ||
45 | #define PLL_DITH_FDBK_M_MASK 0xFFFF | ||
46 | |||
47 | #define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) | ||
48 | #define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) | ||
49 | #define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) | ||
50 | /* CORE CLK CFG register masks */ | ||
51 | #define PLL_HCLK_RATIO_SHIFT 10 | ||
52 | #define PLL_HCLK_RATIO_MASK 0x3 | ||
53 | #define HCLK_PCLK_RATIO_SHIFT 8 | ||
54 | #define HCLK_PCLK_RATIO_MASK 0x3 | ||
55 | |||
56 | #define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) | ||
57 | /* PERIP_CLK_CFG register masks */ | ||
58 | #define CLCD_CLK_SHIFT 2 | ||
59 | #define CLCD_CLK_MASK 0x3 | ||
60 | #define UART_CLK_SHIFT 4 | ||
61 | #define UART_CLK_MASK 0x1 | ||
62 | #define FIRDA_CLK_SHIFT 5 | ||
63 | #define FIRDA_CLK_MASK 0x3 | ||
64 | #define GPT0_CLK_SHIFT 8 | ||
65 | #define GPT1_CLK_SHIFT 10 | ||
66 | #define GPT2_CLK_SHIFT 11 | ||
67 | #define GPT3_CLK_SHIFT 12 | ||
68 | #define GPT_CLK_MASK 0x1 | ||
69 | #define AUX_CLK_PLL3_MASK 0 | ||
70 | #define AUX_CLK_PLL1_MASK 1 | ||
71 | |||
72 | #define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) | ||
73 | /* PERIP1_CLK_ENB register masks */ | ||
74 | #define UART0_CLK_ENB 3 | ||
75 | #define UART1_CLK_ENB 4 | ||
76 | #define SSP0_CLK_ENB 5 | ||
77 | #define SSP1_CLK_ENB 6 | ||
78 | #define I2C_CLK_ENB 7 | ||
79 | #define JPEG_CLK_ENB 8 | ||
80 | #define FSMC_CLK_ENB 9 | ||
81 | #define FIRDA_CLK_ENB 10 | ||
82 | #define GPT2_CLK_ENB 11 | ||
83 | #define GPT3_CLK_ENB 12 | ||
84 | #define GPIO2_CLK_ENB 13 | ||
85 | #define SSP2_CLK_ENB 14 | ||
86 | #define ADC_CLK_ENB 15 | ||
87 | #define GPT1_CLK_ENB 11 | ||
88 | #define RTC_CLK_ENB 17 | ||
89 | #define GPIO1_CLK_ENB 18 | ||
90 | #define DMA_CLK_ENB 19 | ||
91 | #define SMI_CLK_ENB 21 | ||
92 | #define CLCD_CLK_ENB 22 | ||
93 | #define GMAC_CLK_ENB 23 | ||
94 | #define USBD_CLK_ENB 24 | ||
95 | #define USBH0_CLK_ENB 25 | ||
96 | #define USBH1_CLK_ENB 26 | ||
97 | |||
98 | #define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) | ||
99 | #define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) | ||
100 | #define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) | ||
101 | /* PERIP1_SOF_RST register masks */ | ||
102 | #define JPEG_SOF_RST 8 | ||
103 | |||
104 | #define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) | ||
105 | #define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) | ||
106 | #define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) | ||
107 | #define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) | ||
108 | #define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) | ||
109 | /* gpt synthesizer register masks */ | ||
110 | #define GPT_MSCALE_SHIFT 0 | ||
111 | #define GPT_MSCALE_MASK 0xFFF | ||
112 | #define GPT_NSCALE_SHIFT 12 | ||
113 | #define GPT_NSCALE_MASK 0xF | ||
114 | |||
115 | #define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) | ||
116 | #define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) | ||
117 | #define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) | ||
118 | #define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) | ||
119 | #define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) | ||
120 | #define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) | ||
121 | #define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) | ||
122 | #define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) | ||
123 | #define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) | ||
124 | #define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) | ||
125 | /* aux clk synthesiser register masks for irda to ras4 */ | ||
126 | #define AUX_EQ_SEL_SHIFT 30 | ||
127 | #define AUX_EQ_SEL_MASK 1 | ||
128 | #define AUX_EQ1_SEL 0 | ||
129 | #define AUX_EQ2_SEL 1 | ||
130 | #define AUX_XSCALE_SHIFT 16 | ||
131 | #define AUX_XSCALE_MASK 0xFFF | ||
132 | #define AUX_YSCALE_SHIFT 0 | ||
133 | #define AUX_YSCALE_MASK 0xFFF | ||
134 | |||
135 | #define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) | ||
136 | #define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) | ||
137 | #define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) | ||
138 | #define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) | ||
139 | #define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) | ||
140 | #define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) | ||
141 | #define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) | ||
142 | #define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) | ||
143 | #define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) | ||
144 | #define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) | ||
145 | #define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) | ||
146 | #define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) | ||
147 | #define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) | ||
148 | #define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) | ||
149 | #define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) | ||
150 | #define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) | ||
151 | #define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) | ||
152 | #define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) | ||
153 | #define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) | ||
154 | #define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) | ||
155 | #define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) | ||
156 | #define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) | ||
157 | #define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) | ||
158 | #define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) | ||
159 | #define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) | ||
160 | #define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) | ||
161 | #define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) | ||
162 | #define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) | ||
163 | #define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) | ||
164 | #define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) | ||
165 | #define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) | ||
166 | #define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) | ||
167 | #define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) | ||
168 | #define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) | ||
169 | #define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) | ||
170 | #define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) | ||
171 | #define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) | ||
172 | |||
173 | #endif /* __MACH_MISC_REGS_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h new file mode 100644 index 000000000000..a835f5b6b182 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear.h | |||
@@ -0,0 +1,173 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/spear.h | ||
3 | * | ||
4 | * SPEAr6xx Machine family specific definition | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_SPEAR6XX_H | ||
15 | #define __MACH_SPEAR6XX_H | ||
16 | |||
17 | #include <mach/hardware.h> | ||
18 | #include <mach/spear600.h> | ||
19 | |||
20 | #define SPEAR6XX_ML_SDRAM_BASE 0x00000000 | ||
21 | #define SPEAR6XX_ML_SDRAM_SIZE 0x40000000 | ||
22 | |||
23 | /* ICM1 - Low speed connection */ | ||
24 | #define SPEAR6XX_ICM1_BASE 0xD0000000 | ||
25 | #define SPEAR6XX_ICM1_SIZE 0x08000000 | ||
26 | |||
27 | #define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 | ||
28 | #define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) | ||
29 | #define SPEAR6XX_ICM1_UART0_SIZE 0x00080000 | ||
30 | |||
31 | #define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 | ||
32 | #define SPEAR6XX_ICM1_UART1_SIZE 0x00080000 | ||
33 | |||
34 | #define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 | ||
35 | #define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000 | ||
36 | |||
37 | #define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 | ||
38 | #define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000 | ||
39 | |||
40 | #define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 | ||
41 | #define SPEAR6XX_ICM1_I2C_SIZE 0x00080000 | ||
42 | |||
43 | #define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 | ||
44 | #define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000 | ||
45 | |||
46 | #define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 | ||
47 | #define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000 | ||
48 | |||
49 | #define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 | ||
50 | #define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000 | ||
51 | |||
52 | #define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 | ||
53 | #define SPEAR6XX_ICM1_NAND_SIZE 0x00800000 | ||
54 | |||
55 | #define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 | ||
56 | #define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000 | ||
57 | |||
58 | /* ICM2 - Application Subsystem */ | ||
59 | #define SPEAR6XX_ICM2_BASE 0xD8000000 | ||
60 | #define SPEAR6XX_ICM2_SIZE 0x08000000 | ||
61 | |||
62 | #define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 | ||
63 | #define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000 | ||
64 | |||
65 | #define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 | ||
66 | #define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000 | ||
67 | |||
68 | #define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 | ||
69 | #define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000 | ||
70 | |||
71 | #define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 | ||
72 | #define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000 | ||
73 | |||
74 | #define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 | ||
75 | #define SPEAR6XX_ICM2_ADC_SIZE 0x00080000 | ||
76 | |||
77 | /* ML-1, 2 - Multi Layer CPU Subsystem */ | ||
78 | #define SPEAR6XX_ML_CPU_BASE 0xF0000000 | ||
79 | #define SPEAR6XX_ML_CPU_SIZE 0x08000000 | ||
80 | |||
81 | #define SPEAR6XX_CPU_TMR_BASE 0xF0000000 | ||
82 | #define SPEAR6XX_CPU_TMR_SIZE 0x00100000 | ||
83 | |||
84 | #define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 | ||
85 | #define SPEAR6XX_CPU_GPIO_SIZE 0x00100000 | ||
86 | |||
87 | #define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 | ||
88 | #define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) | ||
89 | #define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000 | ||
90 | |||
91 | #define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 | ||
92 | #define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) | ||
93 | #define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000 | ||
94 | |||
95 | /* ICM3 - Basic Subsystem */ | ||
96 | #define SPEAR6XX_ICM3_BASE 0xF8000000 | ||
97 | #define SPEAR6XX_ICM3_SIZE 0x08000000 | ||
98 | |||
99 | #define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 | ||
100 | #define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000 | ||
101 | |||
102 | #define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 | ||
103 | #define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000 | ||
104 | |||
105 | #define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 | ||
106 | #define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000 | ||
107 | |||
108 | #define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 | ||
109 | #define SPEAR6XX_ICM3_DMA_SIZE 0x00200000 | ||
110 | |||
111 | #define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 | ||
112 | #define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 | ||
113 | |||
114 | #define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 | ||
115 | #define SPEAR6XX_ICM3_TMR_SIZE 0x00080000 | ||
116 | |||
117 | #define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 | ||
118 | #define SPEAR6XX_ICM3_WDT_SIZE 0x00080000 | ||
119 | |||
120 | #define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 | ||
121 | #define SPEAR6XX_ICM3_RTC_SIZE 0x00080000 | ||
122 | |||
123 | #define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 | ||
124 | #define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000 | ||
125 | |||
126 | #define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 | ||
127 | #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) | ||
128 | #define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000 | ||
129 | |||
130 | #define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 | ||
131 | #define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) | ||
132 | #define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000 | ||
133 | |||
134 | /* ICM4 - High Speed Connection */ | ||
135 | #define SPEAR6XX_ICM4_BASE 0xE0000000 | ||
136 | #define SPEAR6XX_ICM4_SIZE 0x08000000 | ||
137 | |||
138 | #define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 | ||
139 | #define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000 | ||
140 | |||
141 | #define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 | ||
142 | #define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000 | ||
143 | |||
144 | #define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 | ||
145 | #define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000 | ||
146 | |||
147 | #define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 | ||
148 | #define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000 | ||
149 | |||
150 | #define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 | ||
151 | #define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000 | ||
152 | |||
153 | #define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 | ||
154 | #define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000 | ||
155 | |||
156 | #define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 | ||
157 | #define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000 | ||
158 | |||
159 | #define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 | ||
160 | #define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000 | ||
161 | |||
162 | #define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 | ||
163 | #define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000 | ||
164 | |||
165 | /* Debug uart for linux, will be used for debug and uncompress messages */ | ||
166 | #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE | ||
167 | #define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE | ||
168 | |||
169 | /* Sysctl base for spear platform */ | ||
170 | #define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE | ||
171 | #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE | ||
172 | |||
173 | #endif /* __MACH_SPEAR6XX_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h new file mode 100644 index 000000000000..c068cc50b0fb --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/spear600.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear66xx/include/mach/spear600.h | ||
3 | * | ||
4 | * SPEAr600 Machine specific definition | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Viresh Kumar<viresh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifdef CONFIG_MACH_SPEAR600 | ||
15 | |||
16 | #ifndef __MACH_SPEAR600_H | ||
17 | #define __MACH_SPEAR600_H | ||
18 | |||
19 | #endif /* __MACH_SPEAR600_H */ | ||
20 | |||
21 | #endif /* CONFIG_MACH_SPEAR600 */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h new file mode 100644 index 000000000000..0b1d2be81cfb --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/system.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/system.h | ||
3 | * | ||
4 | * SPEAr6xx Machine family specific architecture functions | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_SYSTEM_H | ||
15 | #define __MACH_SYSTEM_H | ||
16 | |||
17 | #include <plat/system.h> | ||
18 | |||
19 | #endif /* __MACH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h new file mode 100644 index 000000000000..ac1c5b005695 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/timex.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/timex.h | ||
3 | * | ||
4 | * SPEAr6XX machine family specific timex definitions | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_TIMEX_H | ||
15 | #define __MACH_TIMEX_H | ||
16 | |||
17 | #include <plat/timex.h> | ||
18 | |||
19 | #endif /* __MACH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h new file mode 100644 index 000000000000..77f0765e21e1 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/uncompress.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/uncompress.h | ||
3 | * | ||
4 | * Serial port stubs for kernel decompress status messages | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_UNCOMPRESS_H | ||
15 | #define __MACH_UNCOMPRESS_H | ||
16 | |||
17 | #include <plat/uncompress.h> | ||
18 | |||
19 | #endif /* __MACH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h new file mode 100644 index 000000000000..4a0b56cb2a91 --- /dev/null +++ b/arch/arm/mach-spear6xx/include/mach/vmalloc.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-spear6xx/include/mach/vmalloc.h | ||
3 | * | ||
4 | * Defining Vmalloc area for SPEAr6xx machine family | ||
5 | * | ||
6 | * Copyright (C) 2009 ST Microelectronics | ||
7 | * Rajeev Kumar<rajeev-dlh.kumar@st.com> | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public | ||
10 | * License version 2. This program is licensed "as is" without any | ||
11 | * warranty of any kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #ifndef __MACH_VMALLOC_H | ||
15 | #define __MACH_VMALLOC_H | ||
16 | |||
17 | #include <plat/vmalloc.h> | ||
18 | |||
19 | #endif /* __MACH_VMALLOC_H */ | ||