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-rw-r--r--arch/arm/mach-spear6xx/include/mach/entry-macro.S36
1 files changed, 0 insertions, 36 deletions
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
index 8a0b0ed7b203..d490a910d925 100644
--- a/arch/arm/mach-spear6xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
@@ -11,44 +11,8 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <asm/hardware/vic.h>
15#include <mach/hardware.h>
16
17 .macro disable_fiq 14 .macro disable_fiq
18 .endm 15 .endm
19 16
20 .macro get_irqnr_preamble, base, tmp
21 .endm
22
23 .macro arch_ret_to_user, tmp1, tmp2 17 .macro arch_ret_to_user, tmp1, tmp2
24 .endm 18 .endm
25
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
28 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
29 mov \irqnr, #0
30 teq \irqstat, #0
31 bne 1001f
32 ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
33 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
34 teq \irqstat, #0
35 beq 1002f @ this will set/reset
36 @ zero register
37 mov \irqnr, #32
381001:
39 /*
40 * Following code will find bit position of least significang
41 * bit set in irqstat, using following equation
42 * least significant bit set in n = (n & ~(n-1))
43 */
44 sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
45 mvn \tmp, \tmp @ tmp = ~tmp
46 and \irqstat, \irqstat, \tmp @ irqstat &= tmp
47 /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
48 clz \tmp, \irqstat @ tmp = leading zeros
49
50 rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1
51 add \irqnr, \irqnr, \tmp
52
531002: /* EQ will be set if no irqs pending */
54 .endm