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-rw-r--r--arch/arm/mach-spear3xx/Kconfig30
-rw-r--r--arch/arm/mach-spear3xx/Kconfig30017
-rw-r--r--arch/arm/mach-spear3xx/Kconfig31017
-rw-r--r--arch/arm/mach-spear3xx/Kconfig32017
-rw-r--r--arch/arm/mach-spear3xx/clock.c74
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h205
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h206
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h26
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h44
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h48
-rw-r--r--arch/arm/mach-spear3xx/spear300.c163
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c32
-rw-r--r--arch/arm/mach-spear3xx/spear310.c149
-rw-r--r--arch/arm/mach-spear3xx/spear310_evb.c45
-rw-r--r--arch/arm/mach-spear3xx/spear320.c251
-rw-r--r--arch/arm/mach-spear3xx/spear320_evb.c40
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c132
17 files changed, 738 insertions, 758 deletions
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317cc486..2cee6b0de371 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
4 4
5if ARCH_SPEAR3XX 5if ARCH_SPEAR3XX
6 6
7choice 7menu "SPEAr3xx Implementations"
8 prompt "SPEAr3XX Family" 8config BOARD_SPEAR300_EVB
9 default MACH_SPEAR300 9 bool "SPEAr300 Evaluation Board"
10 select MACH_SPEAR300
11 help
12 Supports ST SPEAr300 Evaluation Board
13
14config BOARD_SPEAR310_EVB
15 bool "SPEAr310 Evaluation Board"
16 select MACH_SPEAR310
17 help
18 Supports ST SPEAr310 Evaluation Board
19
20config BOARD_SPEAR320_EVB
21 bool "SPEAr320 Evaluation Board"
22 select MACH_SPEAR320
23 help
24 Supports ST SPEAr320 Evaluation Board
25
26endmenu
10 27
11config MACH_SPEAR300 28config MACH_SPEAR300
12 bool "SPEAr300" 29 bool "SPEAr300"
@@ -23,11 +40,4 @@ config MACH_SPEAR320
23 help 40 help
24 Supports ST SPEAr320 Machine 41 Supports ST SPEAr320 Machine
25 42
26endchoice
27
28# Adding SPEAr3XX machine specific configuration files
29source "arch/arm/mach-spear3xx/Kconfig300"
30source "arch/arm/mach-spear3xx/Kconfig310"
31source "arch/arm/mach-spear3xx/Kconfig320"
32
33endif #ARCH_SPEAR3XX 43endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05b4ab4..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr300 machine configuration file
3#
4
5if MACH_SPEAR300
6
7choice
8 prompt "SPEAr300 Boards"
9 default BOARD_SPEAR300_EVB
10
11config BOARD_SPEAR300_EVB
12 bool "SPEAr300 Evaluation Board"
13 help
14 Supports ST SPEAr300 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442d75bd..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr310 machine configuration file
3#
4
5if MACH_SPEAR310
6
7choice
8 prompt "SPEAr310 Boards"
9 default BOARD_SPEAR310_EVB
10
11config BOARD_SPEAR310_EVB
12 bool "SPEAr310 Evaluation Board"
13 help
14 Supports ST SPEAr310 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438399b8..000000000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
1#
2# SPEAr320 machine configuration file
3#
4
5if MACH_SPEAR320
6
7choice
8 prompt "SPEAr320 Boards"
9 default BOARD_SPEAR320_EVB
10
11config BOARD_SPEAR320_EVB
12 bool "SPEAr320 Evaluation Board"
13 help
14 Supports ST SPEAr320 Evaluation Board
15endchoice
16
17endif #MACH_SPEAR320
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 98bc7edc95a6..f67860cd649f 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <asm/mach-types.h>
16#include <plat/clock.h> 17#include <plat/clock.h>
17#include <mach/misc_regs.h> 18#include <mach/misc_regs.h>
18 19
@@ -688,56 +689,71 @@ static struct clk_lookup spear_clk_lookups[] = {
688 { .dev_id = "adc", .clk = &adc_clk}, 689 { .dev_id = "adc", .clk = &adc_clk},
689 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk}, 690 { .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
690 { .dev_id = "gpio", .clk = &gpio_clk}, 691 { .dev_id = "gpio", .clk = &gpio_clk},
691#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 692};
692 { .dev_id = "physmap-flash", .clk = &emi_clk},
693#endif
694#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
695 defined(CONFIG_MACH_SPEAR320)
696 { .con_id = "fsmc", .clk = &fsmc_clk},
697#endif
698
699/* common clocks to spear310 and spear320 */
700#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
701 { .dev_id = "uart1", .clk = &uart1_clk},
702 { .dev_id = "uart2", .clk = &uart2_clk},
703#endif
704
705 /* common clock to spear300 and spear320 */
706#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
707 { .dev_id = "clcd", .clk = &clcd_clk},
708 { .dev_id = "sdhci", .clk = &sdhci_clk},
709#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
710 693
711 /* spear300 machine specific clock structures */ 694/* array of all spear 300 clock lookups */
712#ifdef CONFIG_MACH_SPEAR300 695#ifdef CONFIG_MACH_SPEAR300
696static struct clk_lookup spear300_clk_lookups[] = {
697 { .dev_id = "clcd", .clk = &clcd_clk},
698 { .con_id = "fsmc", .clk = &fsmc_clk},
713 { .dev_id = "gpio1", .clk = &gpio1_clk}, 699 { .dev_id = "gpio1", .clk = &gpio1_clk},
714 { .dev_id = "keyboard", .clk = &kbd_clk}, 700 { .dev_id = "keyboard", .clk = &kbd_clk},
701 { .dev_id = "sdhci", .clk = &sdhci_clk},
702};
715#endif 703#endif
716 704
717 /* spear310 machine specific clock structures */ 705/* array of all spear 310 clock lookups */
718#ifdef CONFIG_MACH_SPEAR310 706#ifdef CONFIG_MACH_SPEAR310
707static struct clk_lookup spear310_clk_lookups[] = {
708 { .con_id = "fsmc", .clk = &fsmc_clk},
709 { .con_id = "emi", .clk = &emi_clk},
710 { .dev_id = "uart1", .clk = &uart1_clk},
711 { .dev_id = "uart2", .clk = &uart2_clk},
719 { .dev_id = "uart3", .clk = &uart3_clk}, 712 { .dev_id = "uart3", .clk = &uart3_clk},
720 { .dev_id = "uart4", .clk = &uart4_clk}, 713 { .dev_id = "uart4", .clk = &uart4_clk},
721 { .dev_id = "uart5", .clk = &uart5_clk}, 714 { .dev_id = "uart5", .clk = &uart5_clk},
722 715};
723#endif 716#endif
724 /* spear320 machine specific clock structures */ 717
718/* array of all spear 320 clock lookups */
725#ifdef CONFIG_MACH_SPEAR320 719#ifdef CONFIG_MACH_SPEAR320
720static struct clk_lookup spear320_clk_lookups[] = {
721 { .dev_id = "clcd", .clk = &clcd_clk},
722 { .con_id = "fsmc", .clk = &fsmc_clk},
723 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
724 { .con_id = "emi", .clk = &emi_clk},
725 { .dev_id = "pwm", .clk = &pwm_clk},
726 { .dev_id = "sdhci", .clk = &sdhci_clk},
726 { .dev_id = "c_can_platform.0", .clk = &can0_clk}, 727 { .dev_id = "c_can_platform.0", .clk = &can0_clk},
727 { .dev_id = "c_can_platform.1", .clk = &can1_clk}, 728 { .dev_id = "c_can_platform.1", .clk = &can1_clk},
728 { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
729 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk}, 729 { .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
730 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk}, 730 { .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
731 { .dev_id = "pwm", .clk = &pwm_clk}, 731 { .dev_id = "uart1", .clk = &uart1_clk},
732#endif 732 { .dev_id = "uart2", .clk = &uart2_clk},
733}; 733};
734#endif
734 735
735void __init clk_init(void) 736void __init spear3xx_clk_init(void)
736{ 737{
737 int i; 738 int i, cnt;
739 struct clk_lookup *lookups;
740
741 if (machine_is_spear300()) {
742 cnt = ARRAY_SIZE(spear300_clk_lookups);
743 lookups = spear300_clk_lookups;
744 } else if (machine_is_spear310()) {
745 cnt = ARRAY_SIZE(spear310_clk_lookups);
746 lookups = spear310_clk_lookups;
747 } else {
748 cnt = ARRAY_SIZE(spear320_clk_lookups);
749 lookups = spear320_clk_lookups;
750 }
738 751
739 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) 752 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
740 clk_register(&spear_clk_lookups[i]); 753 clk_register(&spear_clk_lookups[i]);
741 754
742 recalc_root_clocks(); 755 for (i = 0; i < cnt; i++)
756 clk_register(&lookups[i]);
757
758 clk_init();
743} 759}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 8e30636909ef..b8f31c3935f7 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,16 +27,16 @@
27 * Following GPT channels will be used as clock source and clockevent 27 * Following GPT channels will be used as clock source and clockevent
28 */ 28 */
29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE 29#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
30#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 30#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
31#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 31#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
32 32
33/* Add spear3xx family device structure declarations here */ 33/* Add spear3xx family device structure declarations here */
34extern struct amba_device gpio_device; 34extern struct amba_device spear3xx_gpio_device;
35extern struct amba_device uart_device; 35extern struct amba_device spear3xx_uart_device;
36extern struct sys_timer spear3xx_timer; 36extern struct sys_timer spear3xx_timer;
37 37
38/* Add spear3xx family function declarations here */ 38/* Add spear3xx family function declarations here */
39void __init clk_init(void); 39void __init spear3xx_clk_init(void);
40void __init spear_setup_timer(void); 40void __init spear_setup_timer(void);
41void __init spear3xx_map_io(void); 41void __init spear3xx_map_io(void);
42void __init spear3xx_init_irq(void); 42void __init spear3xx_init_irq(void);
@@ -60,81 +60,80 @@ void __init spear3xx_init(void);
60#define PMX_TIMER_1_2_MASK (1 << 0) 60#define PMX_TIMER_1_2_MASK (1 << 0)
61 61
62/* pad mux devices */ 62/* pad mux devices */
63extern struct pmx_dev pmx_firda; 63extern struct pmx_dev spear3xx_pmx_firda;
64extern struct pmx_dev pmx_i2c; 64extern struct pmx_dev spear3xx_pmx_i2c;
65extern struct pmx_dev pmx_ssp_cs; 65extern struct pmx_dev spear3xx_pmx_ssp_cs;
66extern struct pmx_dev pmx_ssp; 66extern struct pmx_dev spear3xx_pmx_ssp;
67extern struct pmx_dev pmx_mii; 67extern struct pmx_dev spear3xx_pmx_mii;
68extern struct pmx_dev pmx_gpio_pin0; 68extern struct pmx_dev spear3xx_pmx_gpio_pin0;
69extern struct pmx_dev pmx_gpio_pin1; 69extern struct pmx_dev spear3xx_pmx_gpio_pin1;
70extern struct pmx_dev pmx_gpio_pin2; 70extern struct pmx_dev spear3xx_pmx_gpio_pin2;
71extern struct pmx_dev pmx_gpio_pin3; 71extern struct pmx_dev spear3xx_pmx_gpio_pin3;
72extern struct pmx_dev pmx_gpio_pin4; 72extern struct pmx_dev spear3xx_pmx_gpio_pin4;
73extern struct pmx_dev pmx_gpio_pin5; 73extern struct pmx_dev spear3xx_pmx_gpio_pin5;
74extern struct pmx_dev pmx_uart0_modem; 74extern struct pmx_dev spear3xx_pmx_uart0_modem;
75extern struct pmx_dev pmx_uart0; 75extern struct pmx_dev spear3xx_pmx_uart0;
76extern struct pmx_dev pmx_timer_3_4; 76extern struct pmx_dev spear3xx_pmx_timer_3_4;
77extern struct pmx_dev pmx_timer_1_2; 77extern struct pmx_dev spear3xx_pmx_timer_1_2;
78 78
79#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 79#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
80/* padmux plgpio devices */ 80/* padmux plgpio devices */
81extern struct pmx_dev pmx_plgpio_0_1; 81extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
82extern struct pmx_dev pmx_plgpio_2_3; 82extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
83extern struct pmx_dev pmx_plgpio_4_5; 83extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
84extern struct pmx_dev pmx_plgpio_6_9; 84extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
85extern struct pmx_dev pmx_plgpio_10_27; 85extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
86extern struct pmx_dev pmx_plgpio_28; 86extern struct pmx_dev spear3xx_pmx_plgpio_28;
87extern struct pmx_dev pmx_plgpio_29; 87extern struct pmx_dev spear3xx_pmx_plgpio_29;
88extern struct pmx_dev pmx_plgpio_30; 88extern struct pmx_dev spear3xx_pmx_plgpio_30;
89extern struct pmx_dev pmx_plgpio_31; 89extern struct pmx_dev spear3xx_pmx_plgpio_31;
90extern struct pmx_dev pmx_plgpio_32; 90extern struct pmx_dev spear3xx_pmx_plgpio_32;
91extern struct pmx_dev pmx_plgpio_33; 91extern struct pmx_dev spear3xx_pmx_plgpio_33;
92extern struct pmx_dev pmx_plgpio_34_36; 92extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
93extern struct pmx_dev pmx_plgpio_37_42; 93extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
94extern struct pmx_dev pmx_plgpio_43_44_47_48; 94extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
95extern struct pmx_dev pmx_plgpio_45_46_49_50; 95extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
96#endif 96#endif
97 97
98extern struct pmx_driver pmx_driver;
99
100/* spear300 declarations */ 98/* spear300 declarations */
101#ifdef CONFIG_MACH_SPEAR300 99#ifdef CONFIG_MACH_SPEAR300
102/* Add spear300 machine device structure declarations here */ 100/* Add spear300 machine device structure declarations here */
103extern struct amba_device gpio1_device; 101extern struct amba_device spear300_gpio1_device;
104 102
105/* pad mux modes */ 103/* pad mux modes */
106extern struct pmx_mode nand_mode; 104extern struct pmx_mode spear300_nand_mode;
107extern struct pmx_mode nor_mode; 105extern struct pmx_mode spear300_nor_mode;
108extern struct pmx_mode photo_frame_mode; 106extern struct pmx_mode spear300_photo_frame_mode;
109extern struct pmx_mode lend_ip_phone_mode; 107extern struct pmx_mode spear300_lend_ip_phone_mode;
110extern struct pmx_mode hend_ip_phone_mode; 108extern struct pmx_mode spear300_hend_ip_phone_mode;
111extern struct pmx_mode lend_wifi_phone_mode; 109extern struct pmx_mode spear300_lend_wifi_phone_mode;
112extern struct pmx_mode hend_wifi_phone_mode; 110extern struct pmx_mode spear300_hend_wifi_phone_mode;
113extern struct pmx_mode ata_pabx_wi2s_mode; 111extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
114extern struct pmx_mode ata_pabx_i2s_mode; 112extern struct pmx_mode spear300_ata_pabx_i2s_mode;
115extern struct pmx_mode caml_lcdw_mode; 113extern struct pmx_mode spear300_caml_lcdw_mode;
116extern struct pmx_mode camu_lcd_mode; 114extern struct pmx_mode spear300_camu_lcd_mode;
117extern struct pmx_mode camu_wlcd_mode; 115extern struct pmx_mode spear300_camu_wlcd_mode;
118extern struct pmx_mode caml_lcd_mode; 116extern struct pmx_mode spear300_caml_lcd_mode;
119 117
120/* pad mux devices */ 118/* pad mux devices */
121extern struct pmx_dev pmx_fsmc_2_chips; 119extern struct pmx_dev spear300_pmx_fsmc_2_chips;
122extern struct pmx_dev pmx_fsmc_4_chips; 120extern struct pmx_dev spear300_pmx_fsmc_4_chips;
123extern struct pmx_dev pmx_keyboard; 121extern struct pmx_dev spear300_pmx_keyboard;
124extern struct pmx_dev pmx_clcd; 122extern struct pmx_dev spear300_pmx_clcd;
125extern struct pmx_dev pmx_telecom_gpio; 123extern struct pmx_dev spear300_pmx_telecom_gpio;
126extern struct pmx_dev pmx_telecom_tdm; 124extern struct pmx_dev spear300_pmx_telecom_tdm;
127extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk; 125extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
128extern struct pmx_dev pmx_telecom_camera; 126extern struct pmx_dev spear300_pmx_telecom_camera;
129extern struct pmx_dev pmx_telecom_dac; 127extern struct pmx_dev spear300_pmx_telecom_dac;
130extern struct pmx_dev pmx_telecom_i2s; 128extern struct pmx_dev spear300_pmx_telecom_i2s;
131extern struct pmx_dev pmx_telecom_boot_pins; 129extern struct pmx_dev spear300_pmx_telecom_boot_pins;
132extern struct pmx_dev pmx_telecom_sdhci_4bit; 130extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
133extern struct pmx_dev pmx_telecom_sdhci_8bit; 131extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
134extern struct pmx_dev pmx_gpio1; 132extern struct pmx_dev spear300_pmx_gpio1;
135 133
136/* Add spear300 machine function declarations here */ 134/* Add spear300 machine function declarations here */
137void __init spear300_init(void); 135void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
136 u8 pmx_dev_count);
138 137
139#endif /* CONFIG_MACH_SPEAR300 */ 138#endif /* CONFIG_MACH_SPEAR300 */
140 139
@@ -143,17 +142,18 @@ void __init spear300_init(void);
143/* Add spear310 machine device structure declarations here */ 142/* Add spear310 machine device structure declarations here */
144 143
145/* pad mux devices */ 144/* pad mux devices */
146extern struct pmx_dev pmx_emi_cs_0_1_4_5; 145extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
147extern struct pmx_dev pmx_emi_cs_2_3; 146extern struct pmx_dev spear310_pmx_emi_cs_2_3;
148extern struct pmx_dev pmx_uart1; 147extern struct pmx_dev spear310_pmx_uart1;
149extern struct pmx_dev pmx_uart2; 148extern struct pmx_dev spear310_pmx_uart2;
150extern struct pmx_dev pmx_uart3_4_5; 149extern struct pmx_dev spear310_pmx_uart3_4_5;
151extern struct pmx_dev pmx_fsmc; 150extern struct pmx_dev spear310_pmx_fsmc;
152extern struct pmx_dev pmx_rs485_0_1; 151extern struct pmx_dev spear310_pmx_rs485_0_1;
153extern struct pmx_dev pmx_tdm0; 152extern struct pmx_dev spear310_pmx_tdm0;
154 153
155/* Add spear310 machine function declarations here */ 154/* Add spear310 machine function declarations here */
156void __init spear310_init(void); 155void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
156 u8 pmx_dev_count);
157 157
158#endif /* CONFIG_MACH_SPEAR310 */ 158#endif /* CONFIG_MACH_SPEAR310 */
159 159
@@ -162,37 +162,38 @@ void __init spear310_init(void);
162/* Add spear320 machine device structure declarations here */ 162/* Add spear320 machine device structure declarations here */
163 163
164/* pad mux modes */ 164/* pad mux modes */
165extern struct pmx_mode auto_net_smii_mode; 165extern struct pmx_mode spear320_auto_net_smii_mode;
166extern struct pmx_mode auto_net_mii_mode; 166extern struct pmx_mode spear320_auto_net_mii_mode;
167extern struct pmx_mode auto_exp_mode; 167extern struct pmx_mode spear320_auto_exp_mode;
168extern struct pmx_mode small_printers_mode; 168extern struct pmx_mode spear320_small_printers_mode;
169 169
170/* pad mux devices */ 170/* pad mux devices */
171extern struct pmx_dev pmx_clcd; 171extern struct pmx_dev spear320_pmx_clcd;
172extern struct pmx_dev pmx_emi; 172extern struct pmx_dev spear320_pmx_emi;
173extern struct pmx_dev pmx_fsmc; 173extern struct pmx_dev spear320_pmx_fsmc;
174extern struct pmx_dev pmx_spp; 174extern struct pmx_dev spear320_pmx_spp;
175extern struct pmx_dev pmx_sdhci; 175extern struct pmx_dev spear320_pmx_sdhci;
176extern struct pmx_dev pmx_i2s; 176extern struct pmx_dev spear320_pmx_i2s;
177extern struct pmx_dev pmx_uart1; 177extern struct pmx_dev spear320_pmx_uart1;
178extern struct pmx_dev pmx_uart1_modem; 178extern struct pmx_dev spear320_pmx_uart1_modem;
179extern struct pmx_dev pmx_uart2; 179extern struct pmx_dev spear320_pmx_uart2;
180extern struct pmx_dev pmx_touchscreen; 180extern struct pmx_dev spear320_pmx_touchscreen;
181extern struct pmx_dev pmx_can; 181extern struct pmx_dev spear320_pmx_can;
182extern struct pmx_dev pmx_sdhci_led; 182extern struct pmx_dev spear320_pmx_sdhci_led;
183extern struct pmx_dev pmx_pwm0; 183extern struct pmx_dev spear320_pmx_pwm0;
184extern struct pmx_dev pmx_pwm1; 184extern struct pmx_dev spear320_pmx_pwm1;
185extern struct pmx_dev pmx_pwm2; 185extern struct pmx_dev spear320_pmx_pwm2;
186extern struct pmx_dev pmx_pwm3; 186extern struct pmx_dev spear320_pmx_pwm3;
187extern struct pmx_dev pmx_ssp1; 187extern struct pmx_dev spear320_pmx_ssp1;
188extern struct pmx_dev pmx_ssp2; 188extern struct pmx_dev spear320_pmx_ssp2;
189extern struct pmx_dev pmx_mii1; 189extern struct pmx_dev spear320_pmx_mii1;
190extern struct pmx_dev pmx_smii0; 190extern struct pmx_dev spear320_pmx_smii0;
191extern struct pmx_dev pmx_smii1; 191extern struct pmx_dev spear320_pmx_smii1;
192extern struct pmx_dev pmx_i2c1; 192extern struct pmx_dev spear320_pmx_i2c1;
193 193
194/* Add spear320 machine function declarations here */ 194/* Add spear320 machine function declarations here */
195void __init spear320_init(void); 195void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
196 u8 pmx_dev_count);
196 197
197#endif /* CONFIG_MACH_SPEAR320 */ 198#endif /* CONFIG_MACH_SPEAR320 */
198 199
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index a1a7f481866d..6e265442808e 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,140 @@
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* SPEAr3xx IRQ definitions */
18#define IRQ_HW_ACCEL_MOD_0 0 18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define IRQ_INTRCOMM_RAS_ARM 1 19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define IRQ_CPU_GPT1_1 2 20#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define IRQ_CPU_GPT1_2 3 21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define IRQ_BASIC_GPT1_1 4 22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define IRQ_BASIC_GPT1_2 5 23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define IRQ_BASIC_GPT2_1 6 24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define IRQ_BASIC_GPT2_2 7 25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define IRQ_BASIC_DMA 8 26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define IRQ_BASIC_SMI 9 27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define IRQ_BASIC_RTC 10 28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define IRQ_BASIC_GPIO 11 29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define IRQ_BASIC_WDT 12 30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define IRQ_DDR_CONTROLLER 13 31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define IRQ_SYS_ERROR 14 32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define IRQ_WAKEUP_RCV 15 33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define IRQ_JPEG 16 34#define SPEAR3XX_IRQ_JPEG 16
35#define IRQ_IRDA 17 35#define SPEAR3XX_IRQ_IRDA 17
36#define IRQ_ADC 18 36#define SPEAR3XX_IRQ_ADC 18
37#define IRQ_UART 19 37#define SPEAR3XX_IRQ_UART 19
38#define IRQ_SSP 20 38#define SPEAR3XX_IRQ_SSP 20
39#define IRQ_I2C 21 39#define SPEAR3XX_IRQ_I2C 21
40#define IRQ_MAC_1 22 40#define SPEAR3XX_IRQ_MAC_1 22
41#define IRQ_MAC_2 23 41#define SPEAR3XX_IRQ_MAC_2 23
42#define IRQ_USB_DEV 24 42#define SPEAR3XX_IRQ_USB_DEV 24
43#define IRQ_USB_H_OHCI_0 25 43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define IRQ_USB_H_EHCI_0 26 44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0 45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define IRQ_USB_H_OHCI_1 27 46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define IRQ_GEN_RAS_1 28 47#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define IRQ_GEN_RAS_2 29 48#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define IRQ_GEN_RAS_3 30 49#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define IRQ_HW_ACCEL_MOD_1 31 50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define IRQ_VIC_END 32 51#define SPEAR3XX_IRQ_VIC_END 32
52 52
53#define VIRQ_START IRQ_VIC_END 53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 54
55/* SPEAr300 Virtual irq definitions */ 55/* SPEAr300 Virtual irq definitions */
56#ifdef CONFIG_MACH_SPEAR300
57/* IRQs sharing IRQ_GEN_RAS_1 */ 56/* IRQs sharing IRQ_GEN_RAS_1 */
58#define VIRQ_IT_PERS_S (VIRQ_START + 0) 57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
59#define VIRQ_IT_CHANGE_S (VIRQ_START + 1) 58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
60#define VIRQ_I2S (VIRQ_START + 2) 59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
61#define VIRQ_TDM (VIRQ_START + 3) 60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
62#define VIRQ_CAMERA_L (VIRQ_START + 4) 61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
63#define VIRQ_CAMERA_F (VIRQ_START + 5) 62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
64#define VIRQ_CAMERA_V (VIRQ_START + 6) 63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
65#define VIRQ_KEYBOARD (VIRQ_START + 7) 64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
66#define VIRQ_GPIO1 (VIRQ_START + 8) 65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
67 66
68/* IRQs sharing IRQ_GEN_RAS_3 */ 67/* IRQs sharing IRQ_GEN_RAS_3 */
69#define IRQ_CLCD IRQ_GEN_RAS_3 68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
70 69
71/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
72#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM 71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
73
74/* GPIO pins virtual irqs */
75#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
76#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
77#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
78 72
79/* SPEAr310 Virtual irq definitions */ 73/* SPEAr310 Virtual irq definitions */
80#elif defined(CONFIG_MACH_SPEAR310)
81/* IRQs sharing IRQ_GEN_RAS_1 */ 74/* IRQs sharing IRQ_GEN_RAS_1 */
82#define VIRQ_SMII0 (VIRQ_START + 0) 75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
83#define VIRQ_SMII1 (VIRQ_START + 1) 76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
84#define VIRQ_SMII2 (VIRQ_START + 2) 77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
85#define VIRQ_SMII3 (VIRQ_START + 3) 78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
86#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4) 79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
87#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5) 80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
88#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6) 81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
89#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7) 82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
90 83
91/* IRQs sharing IRQ_GEN_RAS_2 */ 84/* IRQs sharing IRQ_GEN_RAS_2 */
92#define VIRQ_UART1 (VIRQ_START + 8) 85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
93#define VIRQ_UART2 (VIRQ_START + 9) 86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
94#define VIRQ_UART3 (VIRQ_START + 10) 87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
95#define VIRQ_UART4 (VIRQ_START + 11) 88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
96#define VIRQ_UART5 (VIRQ_START + 12) 89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
97 90
98/* IRQs sharing IRQ_GEN_RAS_3 */ 91/* IRQs sharing IRQ_GEN_RAS_3 */
99#define VIRQ_EMI (VIRQ_START + 13) 92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
100#define VIRQ_PLGPIO (VIRQ_START + 14) 93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
101 94
102/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
103#define VIRQ_TDM_HDLC (VIRQ_START + 15) 96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
104#define VIRQ_RS485_0 (VIRQ_START + 16) 97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
105#define VIRQ_RS485_1 (VIRQ_START + 17) 98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
106
107/* GPIO pins virtual irqs */
108#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
109 99
110/* SPEAr320 Virtual irq definitions */ 100/* SPEAr320 Virtual irq definitions */
111#else
112/* IRQs sharing IRQ_GEN_RAS_1 */ 101/* IRQs sharing IRQ_GEN_RAS_1 */
113#define VIRQ_EMI (VIRQ_START + 0) 102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
114#define VIRQ_CLCD (VIRQ_START + 1) 103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
115#define VIRQ_SPP (VIRQ_START + 2) 104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
116 105
117/* IRQs sharing IRQ_GEN_RAS_2 */ 106/* IRQs sharing IRQ_GEN_RAS_2 */
118#define IRQ_SDHCI IRQ_GEN_RAS_2 107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
119 108
120/* IRQs sharing IRQ_GEN_RAS_3 */ 109/* IRQs sharing IRQ_GEN_RAS_3 */
121#define VIRQ_PLGPIO (VIRQ_START + 3) 110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
122#define VIRQ_I2S_PLAY (VIRQ_START + 4) 111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
123#define VIRQ_I2S_REC (VIRQ_START + 5) 112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
124 113
125/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
126#define VIRQ_CANU (VIRQ_START + 6) 115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
127#define VIRQ_CANL (VIRQ_START + 7) 116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
128#define VIRQ_UART1 (VIRQ_START + 8) 117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
129#define VIRQ_UART2 (VIRQ_START + 9) 118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
130#define VIRQ_SSP1 (VIRQ_START + 10) 119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
131#define VIRQ_SSP2 (VIRQ_START + 11) 120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
132#define VIRQ_SMII0 (VIRQ_START + 12) 121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
133#define VIRQ_MII1_SMII1 (VIRQ_START + 13) 122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
134#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14) 123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
135#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15) 124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
136#define VIRQ_I2C (VIRQ_START + 16) 125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
137
138/* GPIO pins virtual irqs */
139#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
140 126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
141#endif 138#endif
142 139
143/* PLGPIO Virtual IRQs */ 140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
144#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
145#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8) 144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
146#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102) 145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
147#endif 149#endif
148 150
149#define VIRQ_END SPEAR_GPIO_INT_END 151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
150#define NR_IRQS VIRQ_END 152#define NR_IRQS SPEAR3XX_VIRQ_END
151 153
152#endif /* __MACH_IRQS_H */ 154#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index c723515f8853..3b6ea0729040 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
20#define SPEAR300_TELECOM_BASE UL(0x50000000) 20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21 21
22/* Interrupt registers offsets and masks */ 22/* Interrupt registers offsets and masks */
23#define INT_ENB_MASK_REG 0x54 23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define INT_STS_MASK_REG 0x58 24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define IT_PERS_S_IRQ_MASK (1 << 0) 25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define IT_CHANGE_S_IRQ_MASK (1 << 1) 26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define I2S_IRQ_MASK (1 << 2) 27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define TDM_IRQ_MASK (1 << 3) 28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define CAMERA_L_IRQ_MASK (1 << 4) 29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define CAMERA_F_IRQ_MASK (1 << 5) 30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define CAMERA_V_IRQ_MASK (1 << 6) 31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define KEYBOARD_IRQ_MASK (1 << 7) 32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define GPIO1_IRQ_MASK (1 << 8) 33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34 34
35#define SHIRQ_RAS1_MASK 0x1FF 35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36 36
37#define SPEAR300_CLCD_BASE UL(0x60000000) 37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000) 38#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e853479b8cd..1567d0da725f 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -29,29 +29,29 @@
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) 29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30 30
31/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
32#define INT_STS_MASK_REG 0x04 32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SMII0_IRQ_MASK (1 << 0) 33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SMII1_IRQ_MASK (1 << 1) 34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SMII2_IRQ_MASK (1 << 2) 35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SMII3_IRQ_MASK (1 << 3) 36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define WAKEUP_SMII0_IRQ_MASK (1 << 4) 37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define WAKEUP_SMII1_IRQ_MASK (1 << 5) 38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define WAKEUP_SMII2_IRQ_MASK (1 << 6) 39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define WAKEUP_SMII3_IRQ_MASK (1 << 7) 40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define UART1_IRQ_MASK (1 << 8) 41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define UART2_IRQ_MASK (1 << 9) 42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define UART3_IRQ_MASK (1 << 10) 43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define UART4_IRQ_MASK (1 << 11) 44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define UART5_IRQ_MASK (1 << 12) 45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define EMI_IRQ_MASK (1 << 13) 46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define TDM_HDLC_IRQ_MASK (1 << 14) 47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define RS485_0_IRQ_MASK (1 << 15) 48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define RS485_1_IRQ_MASK (1 << 16) 49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50 50
51#define SHIRQ_RAS1_MASK 0x000FF 51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SHIRQ_RAS2_MASK 0x01F00 52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SHIRQ_RAS3_MASK 0x02000 53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55 55
56#endif /* __MACH_SPEAR310_H */ 56#endif /* __MACH_SPEAR310_H */
57 57
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d85d959..8cfa83fa1296 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) 36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37 37
38/* Interrupt registers offsets and masks */ 38/* Interrupt registers offsets and masks */
39#define INT_STS_MASK_REG 0x04 39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define INT_CLR_MASK_REG 0x04 40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define INT_ENB_MASK_REG 0x08 41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define GPIO_IRQ_MASK (1 << 0) 42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define I2S_PLAY_IRQ_MASK (1 << 1) 43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define I2S_REC_IRQ_MASK (1 << 2) 44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define EMI_IRQ_MASK (1 << 7) 45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define CLCD_IRQ_MASK (1 << 8) 46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPP_IRQ_MASK (1 << 9) 47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SDHCI_IRQ_MASK (1 << 10) 48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define CAN_U_IRQ_MASK (1 << 11) 49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define CAN_L_IRQ_MASK (1 << 12) 50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define UART1_IRQ_MASK (1 << 13) 51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define UART2_IRQ_MASK (1 << 14) 52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SSP1_IRQ_MASK (1 << 15) 53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SSP2_IRQ_MASK (1 << 16) 54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SMII0_IRQ_MASK (1 << 17) 55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define MII1_SMII1_IRQ_MASK (1 << 18) 56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define WAKEUP_SMII0_IRQ_MASK (1 << 19) 57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) 58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define I2C1_IRQ_MASK (1 << 21) 59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60 60
61#define SHIRQ_RAS1_MASK 0x000380 61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SHIRQ_RAS3_MASK 0x000007 62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64 64
65#endif /* __MACH_SPEAR320_H */ 65#endif /* __MACH_SPEAR320_H */
66 66
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2697e65adf86..a5e46b4ade20 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -40,86 +40,86 @@
40#define CAML_LCD_MODE (1 << 12) 40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF 41#define ALL_MODES 0x1FFF
42 42
43struct pmx_mode nand_mode = { 43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE, 44 .id = NAND_MODE,
45 .name = "nand mode", 45 .name = "nand mode",
46 .mask = 0x00, 46 .mask = 0x00,
47}; 47};
48 48
49struct pmx_mode nor_mode = { 49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE, 50 .id = NOR_MODE,
51 .name = "nor mode", 51 .name = "nor mode",
52 .mask = 0x01, 52 .mask = 0x01,
53}; 53};
54 54
55struct pmx_mode photo_frame_mode = { 55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE, 56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode", 57 .name = "photo frame mode",
58 .mask = 0x02, 58 .mask = 0x02,
59}; 59};
60 60
61struct pmx_mode lend_ip_phone_mode = { 61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE, 62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode", 63 .name = "lend ip phone mode",
64 .mask = 0x03, 64 .mask = 0x03,
65}; 65};
66 66
67struct pmx_mode hend_ip_phone_mode = { 67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE, 68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode", 69 .name = "hend ip phone mode",
70 .mask = 0x04, 70 .mask = 0x04,
71}; 71};
72 72
73struct pmx_mode lend_wifi_phone_mode = { 73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE, 74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode", 75 .name = "lend wifi phone mode",
76 .mask = 0x05, 76 .mask = 0x05,
77}; 77};
78 78
79struct pmx_mode hend_wifi_phone_mode = { 79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE, 80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode", 81 .name = "hend wifi phone mode",
82 .mask = 0x06, 82 .mask = 0x06,
83}; 83};
84 84
85struct pmx_mode ata_pabx_wi2s_mode = { 85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE, 86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode", 87 .name = "ata pabx wi2s mode",
88 .mask = 0x07, 88 .mask = 0x07,
89}; 89};
90 90
91struct pmx_mode ata_pabx_i2s_mode = { 91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE, 92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode", 93 .name = "ata pabx i2s mode",
94 .mask = 0x08, 94 .mask = 0x08,
95}; 95};
96 96
97struct pmx_mode caml_lcdw_mode = { 97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE, 98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode", 99 .name = "caml lcdw mode",
100 .mask = 0x0C, 100 .mask = 0x0C,
101}; 101};
102 102
103struct pmx_mode camu_lcd_mode = { 103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE, 104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode", 105 .name = "camu lcd mode",
106 .mask = 0x0D, 106 .mask = 0x0D,
107}; 107};
108 108
109struct pmx_mode camu_wlcd_mode = { 109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE, 110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode", 111 .name = "camu wlcd mode",
112 .mask = 0x0E, 112 .mask = 0x0E,
113}; 113};
114 114
115struct pmx_mode caml_lcd_mode = { 115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE, 116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode", 117 .name = "caml lcd mode",
118 .mask = 0x0F, 118 .mask = 0x0F,
119}; 119};
120 120
121/* devices */ 121/* devices */
122struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { 122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 { 123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -127,14 +127,14 @@ struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
127 }, 127 },
128}; 128};
129 129
130struct pmx_dev pmx_fsmc_2_chips = { 130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips", 131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes, 132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), 133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1, 134 .enb_on_reset = 1,
135}; 135};
136 136
137struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { 137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 { 138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | 139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, 140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -142,14 +142,14 @@ struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
142 }, 142 },
143}; 143};
144 144
145struct pmx_dev pmx_fsmc_4_chips = { 145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips", 146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes, 147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), 148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1, 149 .enb_on_reset = 1,
150}; 150};
151 151
152struct pmx_dev_mode pmx_keyboard_modes[] = { 152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 { 153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -159,14 +159,14 @@ struct pmx_dev_mode pmx_keyboard_modes[] = {
159 }, 159 },
160}; 160};
161 161
162struct pmx_dev pmx_keyboard = { 162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard", 163 .name = "keyboard",
164 .modes = pmx_keyboard_modes, 164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes), 165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1, 166 .enb_on_reset = 1,
167}; 167};
168 168
169struct pmx_dev_mode pmx_clcd_modes[] = { 169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 { 170 {
171 .ids = PHOTO_FRAME_MODE, 171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , 172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
@@ -177,14 +177,14 @@ struct pmx_dev_mode pmx_clcd_modes[] = {
177 }, 177 },
178}; 178};
179 179
180struct pmx_dev pmx_clcd = { 180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd", 181 .name = "clcd",
182 .modes = pmx_clcd_modes, 182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1, 184 .enb_on_reset = 1,
185}; 185};
186 186
187struct pmx_dev_mode pmx_telecom_gpio_modes[] = { 187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 { 188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, 189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK, 190 .mask = PMX_MII_MASK,
@@ -204,14 +204,14 @@ struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
204 }, 204 },
205}; 205};
206 206
207struct pmx_dev pmx_telecom_gpio = { 207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio", 208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes, 209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), 210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1, 211 .enb_on_reset = 1,
212}; 212};
213 213
214struct pmx_dev_mode pmx_telecom_tdm_modes[] = { 214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 { 215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE 217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
@@ -222,14 +222,14 @@ struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
222 }, 222 },
223}; 223};
224 224
225struct pmx_dev pmx_telecom_tdm = { 225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm", 226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes, 227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), 228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1, 229 .enb_on_reset = 1,
230}; 230};
231 231
232struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { 232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 { 233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | 234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE 235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
@@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
239 }, 239 },
240}; 240};
241 241
242struct pmx_dev pmx_telecom_spi_cs_i2c_clk = { 242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk", 243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes, 244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), 245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1, 246 .enb_on_reset = 1,
247}; 247};
248 248
249struct pmx_dev_mode pmx_telecom_camera_modes[] = { 249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 { 250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE, 251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK, 252 .mask = PMX_MII_MASK,
@@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_telecom_camera_modes[] = {
256 }, 256 },
257}; 257};
258 258
259struct pmx_dev pmx_telecom_camera = { 259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera", 260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes, 261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), 262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1, 263 .enb_on_reset = 1,
264}; 264};
265 265
266struct pmx_dev_mode pmx_telecom_dac_modes[] = { 266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 { 267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE 268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE, 269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
@@ -271,14 +271,14 @@ struct pmx_dev_mode pmx_telecom_dac_modes[] = {
271 }, 271 },
272}; 272};
273 273
274struct pmx_dev pmx_telecom_dac = { 274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac", 275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes, 276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), 277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1, 278 .enb_on_reset = 1,
279}; 279};
280 280
281struct pmx_dev_mode pmx_telecom_i2s_modes[] = { 281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 { 282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE 283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | 284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -288,14 +288,14 @@ struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
288 }, 288 },
289}; 289};
290 290
291struct pmx_dev pmx_telecom_i2s = { 291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s", 292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes, 293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), 294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1, 295 .enb_on_reset = 1,
296}; 296};
297 297
298struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { 298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 { 299 {
300 .ids = NAND_MODE | NOR_MODE, 300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | 301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -303,14 +303,14 @@ struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
303 }, 303 },
304}; 304};
305 305
306struct pmx_dev pmx_telecom_boot_pins = { 306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins", 307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes, 308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), 309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1, 310 .enb_on_reset = 1,
311}; 311};
312 312
313struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { 313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 { 314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
323 }, 323 },
324}; 324};
325 325
326struct pmx_dev pmx_telecom_sdhci_4bit = { 326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit", 327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes, 328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), 329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1, 330 .enb_on_reset = 1,
331}; 331};
332 332
333struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { 333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 { 334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | 335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | 336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -342,14 +342,14 @@ struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
342 }, 342 },
343}; 343};
344 344
345struct pmx_dev pmx_telecom_sdhci_8bit = { 345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit", 346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes, 347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), 348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1, 349 .enb_on_reset = 1,
350}; 350};
351 351
352struct pmx_dev_mode pmx_gpio1_modes[] = { 352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 { 353 {
354 .ids = PHOTO_FRAME_MODE, 354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | 355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -357,7 +357,7 @@ struct pmx_dev_mode pmx_gpio1_modes[] = {
357 }, 357 },
358}; 358};
359 359
360struct pmx_dev pmx_gpio1 = { 360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1", 361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes, 362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes), 363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
@@ -365,60 +365,60 @@ struct pmx_dev pmx_gpio1 = {
365}; 365};
366 366
367/* pmx driver structure */ 367/* pmx driver structure */
368struct pmx_driver pmx_driver = { 368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, 369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371}; 371};
372 372
373/* spear3xx shared irq */ 373/* spear3xx shared irq */
374struct shirq_dev_config shirq_ras1_config[] = { 374static struct shirq_dev_config shirq_ras1_config[] = {
375 { 375 {
376 .virq = VIRQ_IT_PERS_S, 376 .virq = SPEAR300_VIRQ_IT_PERS_S,
377 .enb_mask = IT_PERS_S_IRQ_MASK, 377 .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
378 .status_mask = IT_PERS_S_IRQ_MASK, 378 .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
379 }, { 379 }, {
380 .virq = VIRQ_IT_CHANGE_S, 380 .virq = SPEAR300_VIRQ_IT_CHANGE_S,
381 .enb_mask = IT_CHANGE_S_IRQ_MASK, 381 .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
382 .status_mask = IT_CHANGE_S_IRQ_MASK, 382 .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
383 }, { 383 }, {
384 .virq = VIRQ_I2S, 384 .virq = SPEAR300_VIRQ_I2S,
385 .enb_mask = I2S_IRQ_MASK, 385 .enb_mask = SPEAR300_I2S_IRQ_MASK,
386 .status_mask = I2S_IRQ_MASK, 386 .status_mask = SPEAR300_I2S_IRQ_MASK,
387 }, { 387 }, {
388 .virq = VIRQ_TDM, 388 .virq = SPEAR300_VIRQ_TDM,
389 .enb_mask = TDM_IRQ_MASK, 389 .enb_mask = SPEAR300_TDM_IRQ_MASK,
390 .status_mask = TDM_IRQ_MASK, 390 .status_mask = SPEAR300_TDM_IRQ_MASK,
391 }, { 391 }, {
392 .virq = VIRQ_CAMERA_L, 392 .virq = SPEAR300_VIRQ_CAMERA_L,
393 .enb_mask = CAMERA_L_IRQ_MASK, 393 .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
394 .status_mask = CAMERA_L_IRQ_MASK, 394 .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
395 }, { 395 }, {
396 .virq = VIRQ_CAMERA_F, 396 .virq = SPEAR300_VIRQ_CAMERA_F,
397 .enb_mask = CAMERA_F_IRQ_MASK, 397 .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
398 .status_mask = CAMERA_F_IRQ_MASK, 398 .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
399 }, { 399 }, {
400 .virq = VIRQ_CAMERA_V, 400 .virq = SPEAR300_VIRQ_CAMERA_V,
401 .enb_mask = CAMERA_V_IRQ_MASK, 401 .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
402 .status_mask = CAMERA_V_IRQ_MASK, 402 .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
403 }, { 403 }, {
404 .virq = VIRQ_KEYBOARD, 404 .virq = SPEAR300_VIRQ_KEYBOARD,
405 .enb_mask = KEYBOARD_IRQ_MASK, 405 .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
406 .status_mask = KEYBOARD_IRQ_MASK, 406 .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
407 }, { 407 }, {
408 .virq = VIRQ_GPIO1, 408 .virq = SPEAR300_VIRQ_GPIO1,
409 .enb_mask = GPIO1_IRQ_MASK, 409 .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
410 .status_mask = GPIO1_IRQ_MASK, 410 .status_mask = SPEAR300_GPIO1_IRQ_MASK,
411 }, 411 },
412}; 412};
413 413
414struct spear_shirq shirq_ras1 = { 414static struct spear_shirq shirq_ras1 = {
415 .irq = IRQ_GEN_RAS_1, 415 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
416 .dev_config = shirq_ras1_config, 416 .dev_config = shirq_ras1_config,
417 .dev_count = ARRAY_SIZE(shirq_ras1_config), 417 .dev_count = ARRAY_SIZE(shirq_ras1_config),
418 .regs = { 418 .regs = {
419 .enb_reg = INT_ENB_MASK_REG, 419 .enb_reg = SPEAR300_INT_ENB_MASK_REG,
420 .status_reg = INT_STS_MASK_REG, 420 .status_reg = SPEAR300_INT_STS_MASK_REG,
421 .status_reg_mask = SHIRQ_RAS1_MASK, 421 .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
422 .clear_reg = -1, 422 .clear_reg = -1,
423 }, 423 },
424}; 424};
@@ -427,10 +427,10 @@ struct spear_shirq shirq_ras1 = {
427/* arm gpio1 device registration */ 427/* arm gpio1 device registration */
428static struct pl061_platform_data gpio1_plat_data = { 428static struct pl061_platform_data gpio1_plat_data = {
429 .gpio_base = 8, 429 .gpio_base = 8,
430 .irq_base = SPEAR_GPIO1_INT_BASE, 430 .irq_base = SPEAR300_GPIO1_INT_BASE,
431}; 431};
432 432
433struct amba_device gpio1_device = { 433struct amba_device spear300_gpio1_device = {
434 .dev = { 434 .dev = {
435 .init_name = "gpio1", 435 .init_name = "gpio1",
436 .platform_data = &gpio1_plat_data, 436 .platform_data = &gpio1_plat_data,
@@ -440,11 +440,12 @@ struct amba_device gpio1_device = {
440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1, 440 .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
442 }, 442 },
443 .irq = {VIRQ_GPIO1, NO_IRQ}, 443 .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
444}; 444};
445 445
446/* spear300 routines */ 446/* spear300 routines */
447void __init spear300_init(void) 447void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
448 u8 pmx_dev_count)
448{ 449{
449 int ret = 0; 450 int ret = 0;
450 451
@@ -460,6 +461,10 @@ void __init spear300_init(void)
460 } 461 }
461 462
462 /* pmx initialization */ 463 /* pmx initialization */
464 pmx_driver.mode = pmx_mode;
465 pmx_driver.devs = pmx_devs;
466 pmx_driver.devs_count = pmx_dev_count;
467
463 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 468 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
464 if (pmx_driver.base) { 469 if (pmx_driver.base) {
465 ret = pmx_register(&pmx_driver); 470 ret = pmx_register(&pmx_driver);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 42d2253ef540..69006f694220 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -19,26 +19,26 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp_cs, 23 &spear3xx_pmx_ssp_cs,
24 &pmx_ssp, 24 &spear3xx_pmx_ssp,
25 &pmx_mii, 25 &spear3xx_pmx_mii,
26 &pmx_uart0, 26 &spear3xx_pmx_uart0,
27 27
28 /* spear300 specific devices */ 28 /* spear300 specific devices */
29 &pmx_fsmc_2_chips, 29 &spear300_pmx_fsmc_2_chips,
30 &pmx_clcd, 30 &spear300_pmx_clcd,
31 &pmx_telecom_sdhci_4bit, 31 &spear300_pmx_telecom_sdhci_4bit,
32 &pmx_gpio1, 32 &spear300_pmx_gpio1,
33}; 33};
34 34
35static struct amba_device *amba_devs[] __initdata = { 35static struct amba_device *amba_devs[] __initdata = {
36 /* spear3xx specific devices */ 36 /* spear3xx specific devices */
37 &gpio_device, 37 &spear3xx_gpio_device,
38 &uart_device, 38 &spear3xx_uart_device,
39 39
40 /* spear300 specific devices */ 40 /* spear300 specific devices */
41 &gpio1_device, 41 &spear300_gpio1_device,
42}; 42};
43 43
44static struct platform_device *plat_devs[] __initdata = { 44static struct platform_device *plat_devs[] __initdata = {
@@ -51,13 +51,9 @@ static void __init spear300_evb_init(void)
51{ 51{
52 unsigned int i; 52 unsigned int i;
53 53
54 /* padmux initialization, must be done before spear300_init */
55 pmx_driver.mode = &photo_frame_mode;
56 pmx_driver.devs = pmx_devs;
57 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
58
59 /* call spear300 machine init function */ 54 /* call spear300 machine init function */
60 spear300_init(); 55 spear300_init(&spear300_photo_frame_mode, pmx_devs,
56 ARRAY_SIZE(pmx_devs));
61 57
62 /* Add Platform Devices */ 58 /* Add Platform Devices */
63 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 59 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 5c0a67b60c2a..9004cf9f01bf 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -22,112 +22,112 @@
22#define PAD_MUX_CONFIG_REG 0x08 22#define PAD_MUX_CONFIG_REG 0x08
23 23
24/* devices */ 24/* devices */
25struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { 25static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
26 { 26 {
27 .ids = 0x00, 27 .ids = 0x00,
28 .mask = PMX_TIMER_3_4_MASK, 28 .mask = PMX_TIMER_3_4_MASK,
29 }, 29 },
30}; 30};
31 31
32struct pmx_dev pmx_emi_cs_0_1_4_5 = { 32struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
33 .name = "emi_cs_0_1_4_5", 33 .name = "emi_cs_0_1_4_5",
34 .modes = pmx_emi_cs_0_1_4_5_modes, 34 .modes = pmx_emi_cs_0_1_4_5_modes,
35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), 35 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
36 .enb_on_reset = 1, 36 .enb_on_reset = 1,
37}; 37};
38 38
39struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { 39static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
40 { 40 {
41 .ids = 0x00, 41 .ids = 0x00,
42 .mask = PMX_TIMER_1_2_MASK, 42 .mask = PMX_TIMER_1_2_MASK,
43 }, 43 },
44}; 44};
45 45
46struct pmx_dev pmx_emi_cs_2_3 = { 46struct pmx_dev spear310_pmx_emi_cs_2_3 = {
47 .name = "emi_cs_2_3", 47 .name = "emi_cs_2_3",
48 .modes = pmx_emi_cs_2_3_modes, 48 .modes = pmx_emi_cs_2_3_modes,
49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), 49 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
50 .enb_on_reset = 1, 50 .enb_on_reset = 1,
51}; 51};
52 52
53struct pmx_dev_mode pmx_uart1_modes[] = { 53static struct pmx_dev_mode pmx_uart1_modes[] = {
54 { 54 {
55 .ids = 0x00, 55 .ids = 0x00,
56 .mask = PMX_FIRDA_MASK, 56 .mask = PMX_FIRDA_MASK,
57 }, 57 },
58}; 58};
59 59
60struct pmx_dev pmx_uart1 = { 60struct pmx_dev spear310_pmx_uart1 = {
61 .name = "uart1", 61 .name = "uart1",
62 .modes = pmx_uart1_modes, 62 .modes = pmx_uart1_modes,
63 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 63 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
64 .enb_on_reset = 1, 64 .enb_on_reset = 1,
65}; 65};
66 66
67struct pmx_dev_mode pmx_uart2_modes[] = { 67static struct pmx_dev_mode pmx_uart2_modes[] = {
68 { 68 {
69 .ids = 0x00, 69 .ids = 0x00,
70 .mask = PMX_TIMER_1_2_MASK, 70 .mask = PMX_TIMER_1_2_MASK,
71 }, 71 },
72}; 72};
73 73
74struct pmx_dev pmx_uart2 = { 74struct pmx_dev spear310_pmx_uart2 = {
75 .name = "uart2", 75 .name = "uart2",
76 .modes = pmx_uart2_modes, 76 .modes = pmx_uart2_modes,
77 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 77 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
78 .enb_on_reset = 1, 78 .enb_on_reset = 1,
79}; 79};
80 80
81struct pmx_dev_mode pmx_uart3_4_5_modes[] = { 81static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
82 { 82 {
83 .ids = 0x00, 83 .ids = 0x00,
84 .mask = PMX_UART0_MODEM_MASK, 84 .mask = PMX_UART0_MODEM_MASK,
85 }, 85 },
86}; 86};
87 87
88struct pmx_dev pmx_uart3_4_5 = { 88struct pmx_dev spear310_pmx_uart3_4_5 = {
89 .name = "uart3_4_5", 89 .name = "uart3_4_5",
90 .modes = pmx_uart3_4_5_modes, 90 .modes = pmx_uart3_4_5_modes,
91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), 91 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92 .enb_on_reset = 1, 92 .enb_on_reset = 1,
93}; 93};
94 94
95struct pmx_dev_mode pmx_fsmc_modes[] = { 95static struct pmx_dev_mode pmx_fsmc_modes[] = {
96 { 96 {
97 .ids = 0x00, 97 .ids = 0x00,
98 .mask = PMX_SSP_CS_MASK, 98 .mask = PMX_SSP_CS_MASK,
99 }, 99 },
100}; 100};
101 101
102struct pmx_dev pmx_fsmc = { 102struct pmx_dev spear310_pmx_fsmc = {
103 .name = "fsmc", 103 .name = "fsmc",
104 .modes = pmx_fsmc_modes, 104 .modes = pmx_fsmc_modes,
105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 105 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106 .enb_on_reset = 1, 106 .enb_on_reset = 1,
107}; 107};
108 108
109struct pmx_dev_mode pmx_rs485_0_1_modes[] = { 109static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110 { 110 {
111 .ids = 0x00, 111 .ids = 0x00,
112 .mask = PMX_MII_MASK, 112 .mask = PMX_MII_MASK,
113 }, 113 },
114}; 114};
115 115
116struct pmx_dev pmx_rs485_0_1 = { 116struct pmx_dev spear310_pmx_rs485_0_1 = {
117 .name = "rs485_0_1", 117 .name = "rs485_0_1",
118 .modes = pmx_rs485_0_1_modes, 118 .modes = pmx_rs485_0_1_modes,
119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), 119 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120 .enb_on_reset = 1, 120 .enb_on_reset = 1,
121}; 121};
122 122
123struct pmx_dev_mode pmx_tdm0_modes[] = { 123static struct pmx_dev_mode pmx_tdm0_modes[] = {
124 { 124 {
125 .ids = 0x00, 125 .ids = 0x00,
126 .mask = PMX_MII_MASK, 126 .mask = PMX_MII_MASK,
127 }, 127 },
128}; 128};
129 129
130struct pmx_dev pmx_tdm0 = { 130struct pmx_dev spear310_pmx_tdm0 = {
131 .name = "tdm0", 131 .name = "tdm0",
132 .modes = pmx_tdm0_modes, 132 .modes = pmx_tdm0_modes,
133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes), 133 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
@@ -135,122 +135,122 @@ struct pmx_dev pmx_tdm0 = {
135}; 135};
136 136
137/* pmx driver structure */ 137/* pmx driver structure */
138struct pmx_driver pmx_driver = { 138static struct pmx_driver pmx_driver = {
139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 139 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140}; 140};
141 141
142/* spear3xx shared irq */ 142/* spear3xx shared irq */
143struct shirq_dev_config shirq_ras1_config[] = { 143static struct shirq_dev_config shirq_ras1_config[] = {
144 { 144 {
145 .virq = VIRQ_SMII0, 145 .virq = SPEAR310_VIRQ_SMII0,
146 .status_mask = SMII0_IRQ_MASK, 146 .status_mask = SPEAR310_SMII0_IRQ_MASK,
147 }, { 147 }, {
148 .virq = VIRQ_SMII1, 148 .virq = SPEAR310_VIRQ_SMII1,
149 .status_mask = SMII1_IRQ_MASK, 149 .status_mask = SPEAR310_SMII1_IRQ_MASK,
150 }, { 150 }, {
151 .virq = VIRQ_SMII2, 151 .virq = SPEAR310_VIRQ_SMII2,
152 .status_mask = SMII2_IRQ_MASK, 152 .status_mask = SPEAR310_SMII2_IRQ_MASK,
153 }, { 153 }, {
154 .virq = VIRQ_SMII3, 154 .virq = SPEAR310_VIRQ_SMII3,
155 .status_mask = SMII3_IRQ_MASK, 155 .status_mask = SPEAR310_SMII3_IRQ_MASK,
156 }, { 156 }, {
157 .virq = VIRQ_WAKEUP_SMII0, 157 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
158 .status_mask = WAKEUP_SMII0_IRQ_MASK, 158 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
159 }, { 159 }, {
160 .virq = VIRQ_WAKEUP_SMII1, 160 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
161 .status_mask = WAKEUP_SMII1_IRQ_MASK, 161 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
162 }, { 162 }, {
163 .virq = VIRQ_WAKEUP_SMII2, 163 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
164 .status_mask = WAKEUP_SMII2_IRQ_MASK, 164 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
165 }, { 165 }, {
166 .virq = VIRQ_WAKEUP_SMII3, 166 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
167 .status_mask = WAKEUP_SMII3_IRQ_MASK, 167 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
168 }, 168 },
169}; 169};
170 170
171struct spear_shirq shirq_ras1 = { 171static struct spear_shirq shirq_ras1 = {
172 .irq = IRQ_GEN_RAS_1, 172 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
173 .dev_config = shirq_ras1_config, 173 .dev_config = shirq_ras1_config,
174 .dev_count = ARRAY_SIZE(shirq_ras1_config), 174 .dev_count = ARRAY_SIZE(shirq_ras1_config),
175 .regs = { 175 .regs = {
176 .enb_reg = -1, 176 .enb_reg = -1,
177 .status_reg = INT_STS_MASK_REG, 177 .status_reg = SPEAR310_INT_STS_MASK_REG,
178 .status_reg_mask = SHIRQ_RAS1_MASK, 178 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
179 .clear_reg = -1, 179 .clear_reg = -1,
180 }, 180 },
181}; 181};
182 182
183struct shirq_dev_config shirq_ras2_config[] = { 183static struct shirq_dev_config shirq_ras2_config[] = {
184 { 184 {
185 .virq = VIRQ_UART1, 185 .virq = SPEAR310_VIRQ_UART1,
186 .status_mask = UART1_IRQ_MASK, 186 .status_mask = SPEAR310_UART1_IRQ_MASK,
187 }, { 187 }, {
188 .virq = VIRQ_UART2, 188 .virq = SPEAR310_VIRQ_UART2,
189 .status_mask = UART2_IRQ_MASK, 189 .status_mask = SPEAR310_UART2_IRQ_MASK,
190 }, { 190 }, {
191 .virq = VIRQ_UART3, 191 .virq = SPEAR310_VIRQ_UART3,
192 .status_mask = UART3_IRQ_MASK, 192 .status_mask = SPEAR310_UART3_IRQ_MASK,
193 }, { 193 }, {
194 .virq = VIRQ_UART4, 194 .virq = SPEAR310_VIRQ_UART4,
195 .status_mask = UART4_IRQ_MASK, 195 .status_mask = SPEAR310_UART4_IRQ_MASK,
196 }, { 196 }, {
197 .virq = VIRQ_UART5, 197 .virq = SPEAR310_VIRQ_UART5,
198 .status_mask = UART5_IRQ_MASK, 198 .status_mask = SPEAR310_UART5_IRQ_MASK,
199 }, 199 },
200}; 200};
201 201
202struct spear_shirq shirq_ras2 = { 202static struct spear_shirq shirq_ras2 = {
203 .irq = IRQ_GEN_RAS_2, 203 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
204 .dev_config = shirq_ras2_config, 204 .dev_config = shirq_ras2_config,
205 .dev_count = ARRAY_SIZE(shirq_ras2_config), 205 .dev_count = ARRAY_SIZE(shirq_ras2_config),
206 .regs = { 206 .regs = {
207 .enb_reg = -1, 207 .enb_reg = -1,
208 .status_reg = INT_STS_MASK_REG, 208 .status_reg = SPEAR310_INT_STS_MASK_REG,
209 .status_reg_mask = SHIRQ_RAS2_MASK, 209 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
210 .clear_reg = -1, 210 .clear_reg = -1,
211 }, 211 },
212}; 212};
213 213
214struct shirq_dev_config shirq_ras3_config[] = { 214static struct shirq_dev_config shirq_ras3_config[] = {
215 { 215 {
216 .virq = VIRQ_EMI, 216 .virq = SPEAR310_VIRQ_EMI,
217 .status_mask = EMI_IRQ_MASK, 217 .status_mask = SPEAR310_EMI_IRQ_MASK,
218 }, 218 },
219}; 219};
220 220
221struct spear_shirq shirq_ras3 = { 221static struct spear_shirq shirq_ras3 = {
222 .irq = IRQ_GEN_RAS_3, 222 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
223 .dev_config = shirq_ras3_config, 223 .dev_config = shirq_ras3_config,
224 .dev_count = ARRAY_SIZE(shirq_ras3_config), 224 .dev_count = ARRAY_SIZE(shirq_ras3_config),
225 .regs = { 225 .regs = {
226 .enb_reg = -1, 226 .enb_reg = -1,
227 .status_reg = INT_STS_MASK_REG, 227 .status_reg = SPEAR310_INT_STS_MASK_REG,
228 .status_reg_mask = SHIRQ_RAS3_MASK, 228 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
229 .clear_reg = -1, 229 .clear_reg = -1,
230 }, 230 },
231}; 231};
232 232
233struct shirq_dev_config shirq_intrcomm_ras_config[] = { 233static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
234 { 234 {
235 .virq = VIRQ_TDM_HDLC, 235 .virq = SPEAR310_VIRQ_TDM_HDLC,
236 .status_mask = TDM_HDLC_IRQ_MASK, 236 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
237 }, { 237 }, {
238 .virq = VIRQ_RS485_0, 238 .virq = SPEAR310_VIRQ_RS485_0,
239 .status_mask = RS485_0_IRQ_MASK, 239 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
240 }, { 240 }, {
241 .virq = VIRQ_RS485_1, 241 .virq = SPEAR310_VIRQ_RS485_1,
242 .status_mask = RS485_1_IRQ_MASK, 242 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
243 }, 243 },
244}; 244};
245 245
246struct spear_shirq shirq_intrcomm_ras = { 246static struct spear_shirq shirq_intrcomm_ras = {
247 .irq = IRQ_INTRCOMM_RAS_ARM, 247 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
248 .dev_config = shirq_intrcomm_ras_config, 248 .dev_config = shirq_intrcomm_ras_config,
249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 249 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
250 .regs = { 250 .regs = {
251 .enb_reg = -1, 251 .enb_reg = -1,
252 .status_reg = INT_STS_MASK_REG, 252 .status_reg = SPEAR310_INT_STS_MASK_REG,
253 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 253 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
254 .clear_reg = -1, 254 .clear_reg = -1,
255 }, 255 },
256}; 256};
@@ -258,7 +258,8 @@ struct spear_shirq shirq_intrcomm_ras = {
258/* Add spear310 specific devices here */ 258/* Add spear310 specific devices here */
259 259
260/* spear310 routines */ 260/* spear310 routines */
261void __init spear310_init(void) 261void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
262 u8 pmx_dev_count)
262{ 263{
263 void __iomem *base; 264 void __iomem *base;
264 int ret = 0; 265 int ret = 0;
@@ -296,6 +297,10 @@ void __init spear310_init(void)
296 297
297 /* pmx initialization */ 298 /* pmx initialization */
298 pmx_driver.base = base; 299 pmx_driver.base = base;
300 pmx_driver.mode = pmx_mode;
301 pmx_driver.devs = pmx_devs;
302 pmx_driver.devs_count = pmx_dev_count;
303
299 ret = pmx_register(&pmx_driver); 304 ret = pmx_register(&pmx_driver);
300 if (ret) 305 if (ret)
301 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 306 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 2d7f333bd67b..c8684ce1f9b3 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -19,31 +19,31 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp, 23 &spear3xx_pmx_ssp,
24 &pmx_gpio_pin0, 24 &spear3xx_pmx_gpio_pin0,
25 &pmx_gpio_pin1, 25 &spear3xx_pmx_gpio_pin1,
26 &pmx_gpio_pin2, 26 &spear3xx_pmx_gpio_pin2,
27 &pmx_gpio_pin3, 27 &spear3xx_pmx_gpio_pin3,
28 &pmx_gpio_pin4, 28 &spear3xx_pmx_gpio_pin4,
29 &pmx_gpio_pin5, 29 &spear3xx_pmx_gpio_pin5,
30 &pmx_uart0, 30 &spear3xx_pmx_uart0,
31 31
32 /* spear310 specific devices */ 32 /* spear310 specific devices */
33 &pmx_emi_cs_0_1_4_5, 33 &spear310_pmx_emi_cs_0_1_4_5,
34 &pmx_emi_cs_2_3, 34 &spear310_pmx_emi_cs_2_3,
35 &pmx_uart1, 35 &spear310_pmx_uart1,
36 &pmx_uart2, 36 &spear310_pmx_uart2,
37 &pmx_uart3_4_5, 37 &spear310_pmx_uart3_4_5,
38 &pmx_fsmc, 38 &spear310_pmx_fsmc,
39 &pmx_rs485_0_1, 39 &spear310_pmx_rs485_0_1,
40 &pmx_tdm0, 40 &spear310_pmx_tdm0,
41}; 41};
42 42
43static struct amba_device *amba_devs[] __initdata = { 43static struct amba_device *amba_devs[] __initdata = {
44 /* spear3xx specific devices */ 44 /* spear3xx specific devices */
45 &gpio_device, 45 &spear3xx_gpio_device,
46 &uart_device, 46 &spear3xx_uart_device,
47 47
48 /* spear310 specific devices */ 48 /* spear310 specific devices */
49}; 49};
@@ -58,13 +58,8 @@ static void __init spear310_evb_init(void)
58{ 58{
59 unsigned int i; 59 unsigned int i;
60 60
61 /* padmux initialization, must be done before spear310_init */
62 pmx_driver.mode = NULL;
63 pmx_driver.devs = pmx_devs;
64 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
65
66 /* call spear310 machine init function */ 61 /* call spear310 machine init function */
67 spear310_init(); 62 spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
68 63
69 /* Add Platform Devices */ 64 /* Add Platform Devices */
70 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 65 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 741c1f414cbd..ee29bef43074 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -29,88 +29,88 @@
29#define SMALL_PRINTERS_MODE (1 << 3) 29#define SMALL_PRINTERS_MODE (1 << 3)
30#define ALL_MODES 0xF 30#define ALL_MODES 0xF
31 31
32struct pmx_mode auto_net_smii_mode = { 32struct pmx_mode spear320_auto_net_smii_mode = {
33 .id = AUTO_NET_SMII_MODE, 33 .id = AUTO_NET_SMII_MODE,
34 .name = "Automation Networking SMII Mode", 34 .name = "Automation Networking SMII Mode",
35 .mask = 0x00, 35 .mask = 0x00,
36}; 36};
37 37
38struct pmx_mode auto_net_mii_mode = { 38struct pmx_mode spear320_auto_net_mii_mode = {
39 .id = AUTO_NET_MII_MODE, 39 .id = AUTO_NET_MII_MODE,
40 .name = "Automation Networking MII Mode", 40 .name = "Automation Networking MII Mode",
41 .mask = 0x01, 41 .mask = 0x01,
42}; 42};
43 43
44struct pmx_mode auto_exp_mode = { 44struct pmx_mode spear320_auto_exp_mode = {
45 .id = AUTO_EXP_MODE, 45 .id = AUTO_EXP_MODE,
46 .name = "Automation Expanded Mode", 46 .name = "Automation Expanded Mode",
47 .mask = 0x02, 47 .mask = 0x02,
48}; 48};
49 49
50struct pmx_mode small_printers_mode = { 50struct pmx_mode spear320_small_printers_mode = {
51 .id = SMALL_PRINTERS_MODE, 51 .id = SMALL_PRINTERS_MODE,
52 .name = "Small Printers Mode", 52 .name = "Small Printers Mode",
53 .mask = 0x03, 53 .mask = 0x03,
54}; 54};
55 55
56/* devices */ 56/* devices */
57struct pmx_dev_mode pmx_clcd_modes[] = { 57static struct pmx_dev_mode pmx_clcd_modes[] = {
58 { 58 {
59 .ids = AUTO_NET_SMII_MODE, 59 .ids = AUTO_NET_SMII_MODE,
60 .mask = 0x0, 60 .mask = 0x0,
61 }, 61 },
62}; 62};
63 63
64struct pmx_dev pmx_clcd = { 64struct pmx_dev spear320_pmx_clcd = {
65 .name = "clcd", 65 .name = "clcd",
66 .modes = pmx_clcd_modes, 66 .modes = pmx_clcd_modes,
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 67 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
68 .enb_on_reset = 1, 68 .enb_on_reset = 1,
69}; 69};
70 70
71struct pmx_dev_mode pmx_emi_modes[] = { 71static struct pmx_dev_mode pmx_emi_modes[] = {
72 { 72 {
73 .ids = AUTO_EXP_MODE, 73 .ids = AUTO_EXP_MODE,
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
75 }, 75 },
76}; 76};
77 77
78struct pmx_dev pmx_emi = { 78struct pmx_dev spear320_pmx_emi = {
79 .name = "emi", 79 .name = "emi",
80 .modes = pmx_emi_modes, 80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes), 81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
82 .enb_on_reset = 1, 82 .enb_on_reset = 1,
83}; 83};
84 84
85struct pmx_dev_mode pmx_fsmc_modes[] = { 85static struct pmx_dev_mode pmx_fsmc_modes[] = {
86 { 86 {
87 .ids = ALL_MODES, 87 .ids = ALL_MODES,
88 .mask = 0x0, 88 .mask = 0x0,
89 }, 89 },
90}; 90};
91 91
92struct pmx_dev pmx_fsmc = { 92struct pmx_dev spear320_pmx_fsmc = {
93 .name = "fsmc", 93 .name = "fsmc",
94 .modes = pmx_fsmc_modes, 94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
96 .enb_on_reset = 1, 96 .enb_on_reset = 1,
97}; 97};
98 98
99struct pmx_dev_mode pmx_spp_modes[] = { 99static struct pmx_dev_mode pmx_spp_modes[] = {
100 { 100 {
101 .ids = SMALL_PRINTERS_MODE, 101 .ids = SMALL_PRINTERS_MODE,
102 .mask = 0x0, 102 .mask = 0x0,
103 }, 103 },
104}; 104};
105 105
106struct pmx_dev pmx_spp = { 106struct pmx_dev spear320_pmx_spp = {
107 .name = "spp", 107 .name = "spp",
108 .modes = pmx_spp_modes, 108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes), 109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
110 .enb_on_reset = 1, 110 .enb_on_reset = 1,
111}; 111};
112 112
113struct pmx_dev_mode pmx_sdhci_modes[] = { 113static struct pmx_dev_mode pmx_sdhci_modes[] = {
114 { 114 {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | 115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
116 SMALL_PRINTERS_MODE, 116 SMALL_PRINTERS_MODE,
@@ -118,42 +118,42 @@ struct pmx_dev_mode pmx_sdhci_modes[] = {
118 }, 118 },
119}; 119};
120 120
121struct pmx_dev pmx_sdhci = { 121struct pmx_dev spear320_pmx_sdhci = {
122 .name = "sdhci", 122 .name = "sdhci",
123 .modes = pmx_sdhci_modes, 123 .modes = pmx_sdhci_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes), 124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
125 .enb_on_reset = 1, 125 .enb_on_reset = 1,
126}; 126};
127 127
128struct pmx_dev_mode pmx_i2s_modes[] = { 128static struct pmx_dev_mode pmx_i2s_modes[] = {
129 { 129 {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK, 131 .mask = PMX_UART0_MODEM_MASK,
132 }, 132 },
133}; 133};
134 134
135struct pmx_dev pmx_i2s = { 135struct pmx_dev spear320_pmx_i2s = {
136 .name = "i2s", 136 .name = "i2s",
137 .modes = pmx_i2s_modes, 137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes), 138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
139 .enb_on_reset = 1, 139 .enb_on_reset = 1,
140}; 140};
141 141
142struct pmx_dev_mode pmx_uart1_modes[] = { 142static struct pmx_dev_mode pmx_uart1_modes[] = {
143 { 143 {
144 .ids = ALL_MODES, 144 .ids = ALL_MODES,
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
146 }, 146 },
147}; 147};
148 148
149struct pmx_dev pmx_uart1 = { 149struct pmx_dev spear320_pmx_uart1 = {
150 .name = "uart1", 150 .name = "uart1",
151 .modes = pmx_uart1_modes, 151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
153 .enb_on_reset = 1, 153 .enb_on_reset = 1,
154}; 154};
155 155
156struct pmx_dev_mode pmx_uart1_modem_modes[] = { 156static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
157 { 157 {
158 .ids = AUTO_EXP_MODE, 158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | 159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
@@ -165,42 +165,42 @@ struct pmx_dev_mode pmx_uart1_modem_modes[] = {
165 }, 165 },
166}; 166};
167 167
168struct pmx_dev pmx_uart1_modem = { 168struct pmx_dev spear320_pmx_uart1_modem = {
169 .name = "uart1_modem", 169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes, 170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), 171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
172 .enb_on_reset = 1, 172 .enb_on_reset = 1,
173}; 173};
174 174
175struct pmx_dev_mode pmx_uart2_modes[] = { 175static struct pmx_dev_mode pmx_uart2_modes[] = {
176 { 176 {
177 .ids = ALL_MODES, 177 .ids = ALL_MODES,
178 .mask = PMX_FIRDA_MASK, 178 .mask = PMX_FIRDA_MASK,
179 }, 179 },
180}; 180};
181 181
182struct pmx_dev pmx_uart2 = { 182struct pmx_dev spear320_pmx_uart2 = {
183 .name = "uart2", 183 .name = "uart2",
184 .modes = pmx_uart2_modes, 184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
186 .enb_on_reset = 1, 186 .enb_on_reset = 1,
187}; 187};
188 188
189struct pmx_dev_mode pmx_touchscreen_modes[] = { 189static struct pmx_dev_mode pmx_touchscreen_modes[] = {
190 { 190 {
191 .ids = AUTO_NET_SMII_MODE, 191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK, 192 .mask = PMX_SSP_CS_MASK,
193 }, 193 },
194}; 194};
195 195
196struct pmx_dev pmx_touchscreen = { 196struct pmx_dev spear320_pmx_touchscreen = {
197 .name = "touchscreen", 197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes, 198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), 199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
200 .enb_on_reset = 1, 200 .enb_on_reset = 1,
201}; 201};
202 202
203struct pmx_dev_mode pmx_can_modes[] = { 203static struct pmx_dev_mode pmx_can_modes[] = {
204 { 204 {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, 205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
@@ -208,28 +208,28 @@ struct pmx_dev_mode pmx_can_modes[] = {
208 }, 208 },
209}; 209};
210 210
211struct pmx_dev pmx_can = { 211struct pmx_dev spear320_pmx_can = {
212 .name = "can", 212 .name = "can",
213 .modes = pmx_can_modes, 213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes), 214 .mode_count = ARRAY_SIZE(pmx_can_modes),
215 .enb_on_reset = 1, 215 .enb_on_reset = 1,
216}; 216};
217 217
218struct pmx_dev_mode pmx_sdhci_led_modes[] = { 218static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
219 { 219 {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK, 221 .mask = PMX_SSP_CS_MASK,
222 }, 222 },
223}; 223};
224 224
225struct pmx_dev pmx_sdhci_led = { 225struct pmx_dev spear320_pmx_sdhci_led = {
226 .name = "sdhci_led", 226 .name = "sdhci_led",
227 .modes = pmx_sdhci_led_modes, 227 .modes = pmx_sdhci_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), 228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
229 .enb_on_reset = 1, 229 .enb_on_reset = 1,
230}; 230};
231 231
232struct pmx_dev_mode pmx_pwm0_modes[] = { 232static struct pmx_dev_mode pmx_pwm0_modes[] = {
233 { 233 {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK, 235 .mask = PMX_UART0_MODEM_MASK,
@@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_pwm0_modes[] = {
239 }, 239 },
240}; 240};
241 241
242struct pmx_dev pmx_pwm0 = { 242struct pmx_dev spear320_pmx_pwm0 = {
243 .name = "pwm0", 243 .name = "pwm0",
244 .modes = pmx_pwm0_modes, 244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes), 245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
246 .enb_on_reset = 1, 246 .enb_on_reset = 1,
247}; 247};
248 248
249struct pmx_dev_mode pmx_pwm1_modes[] = { 249static struct pmx_dev_mode pmx_pwm1_modes[] = {
250 { 250 {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK, 252 .mask = PMX_UART0_MODEM_MASK,
@@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_pwm1_modes[] = {
256 }, 256 },
257}; 257};
258 258
259struct pmx_dev pmx_pwm1 = { 259struct pmx_dev spear320_pmx_pwm1 = {
260 .name = "pwm1", 260 .name = "pwm1",
261 .modes = pmx_pwm1_modes, 261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes), 262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
263 .enb_on_reset = 1, 263 .enb_on_reset = 1,
264}; 264};
265 265
266struct pmx_dev_mode pmx_pwm2_modes[] = { 266static struct pmx_dev_mode pmx_pwm2_modes[] = {
267 { 267 {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK, 269 .mask = PMX_SSP_CS_MASK,
@@ -273,105 +273,105 @@ struct pmx_dev_mode pmx_pwm2_modes[] = {
273 }, 273 },
274}; 274};
275 275
276struct pmx_dev pmx_pwm2 = { 276struct pmx_dev spear320_pmx_pwm2 = {
277 .name = "pwm2", 277 .name = "pwm2",
278 .modes = pmx_pwm2_modes, 278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes), 279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
280 .enb_on_reset = 1, 280 .enb_on_reset = 1,
281}; 281};
282 282
283struct pmx_dev_mode pmx_pwm3_modes[] = { 283static struct pmx_dev_mode pmx_pwm3_modes[] = {
284 { 284 {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK, 286 .mask = PMX_MII_MASK,
287 }, 287 },
288}; 288};
289 289
290struct pmx_dev pmx_pwm3 = { 290struct pmx_dev spear320_pmx_pwm3 = {
291 .name = "pwm3", 291 .name = "pwm3",
292 .modes = pmx_pwm3_modes, 292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes), 293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
294 .enb_on_reset = 1, 294 .enb_on_reset = 1,
295}; 295};
296 296
297struct pmx_dev_mode pmx_ssp1_modes[] = { 297static struct pmx_dev_mode pmx_ssp1_modes[] = {
298 { 298 {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK, 300 .mask = PMX_MII_MASK,
301 }, 301 },
302}; 302};
303 303
304struct pmx_dev pmx_ssp1 = { 304struct pmx_dev spear320_pmx_ssp1 = {
305 .name = "ssp1", 305 .name = "ssp1",
306 .modes = pmx_ssp1_modes, 306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes), 307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
308 .enb_on_reset = 1, 308 .enb_on_reset = 1,
309}; 309};
310 310
311struct pmx_dev_mode pmx_ssp2_modes[] = { 311static struct pmx_dev_mode pmx_ssp2_modes[] = {
312 { 312 {
313 .ids = AUTO_NET_SMII_MODE, 313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK, 314 .mask = PMX_MII_MASK,
315 }, 315 },
316}; 316};
317 317
318struct pmx_dev pmx_ssp2 = { 318struct pmx_dev spear320_pmx_ssp2 = {
319 .name = "ssp2", 319 .name = "ssp2",
320 .modes = pmx_ssp2_modes, 320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes), 321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
322 .enb_on_reset = 1, 322 .enb_on_reset = 1,
323}; 323};
324 324
325struct pmx_dev_mode pmx_mii1_modes[] = { 325static struct pmx_dev_mode pmx_mii1_modes[] = {
326 { 326 {
327 .ids = AUTO_NET_MII_MODE, 327 .ids = AUTO_NET_MII_MODE,
328 .mask = 0x0, 328 .mask = 0x0,
329 }, 329 },
330}; 330};
331 331
332struct pmx_dev pmx_mii1 = { 332struct pmx_dev spear320_pmx_mii1 = {
333 .name = "mii1", 333 .name = "mii1",
334 .modes = pmx_mii1_modes, 334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes), 335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
336 .enb_on_reset = 1, 336 .enb_on_reset = 1,
337}; 337};
338 338
339struct pmx_dev_mode pmx_smii0_modes[] = { 339static struct pmx_dev_mode pmx_smii0_modes[] = {
340 { 340 {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK, 342 .mask = PMX_MII_MASK,
343 }, 343 },
344}; 344};
345 345
346struct pmx_dev pmx_smii0 = { 346struct pmx_dev spear320_pmx_smii0 = {
347 .name = "smii0", 347 .name = "smii0",
348 .modes = pmx_smii0_modes, 348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes), 349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
350 .enb_on_reset = 1, 350 .enb_on_reset = 1,
351}; 351};
352 352
353struct pmx_dev_mode pmx_smii1_modes[] = { 353static struct pmx_dev_mode pmx_smii1_modes[] = {
354 { 354 {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, 355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK, 356 .mask = PMX_MII_MASK,
357 }, 357 },
358}; 358};
359 359
360struct pmx_dev pmx_smii1 = { 360struct pmx_dev spear320_pmx_smii1 = {
361 .name = "smii1", 361 .name = "smii1",
362 .modes = pmx_smii1_modes, 362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes), 363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
364 .enb_on_reset = 1, 364 .enb_on_reset = 1,
365}; 365};
366 366
367struct pmx_dev_mode pmx_i2c1_modes[] = { 367static struct pmx_dev_mode pmx_i2c1_modes[] = {
368 { 368 {
369 .ids = AUTO_EXP_MODE, 369 .ids = AUTO_EXP_MODE,
370 .mask = 0x0, 370 .mask = 0x0,
371 }, 371 },
372}; 372};
373 373
374struct pmx_dev pmx_i2c1 = { 374struct pmx_dev spear320_pmx_i2c1 = {
375 .name = "i2c1", 375 .name = "i2c1",
376 .modes = pmx_i2c1_modes, 376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes), 377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
@@ -379,131 +379,131 @@ struct pmx_dev pmx_i2c1 = {
379}; 379};
380 380
381/* pmx driver structure */ 381/* pmx driver structure */
382struct pmx_driver pmx_driver = { 382static struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, 383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
385}; 385};
386 386
387/* spear3xx shared irq */ 387/* spear3xx shared irq */
388struct shirq_dev_config shirq_ras1_config[] = { 388static struct shirq_dev_config shirq_ras1_config[] = {
389 { 389 {
390 .virq = VIRQ_EMI, 390 .virq = SPEAR320_VIRQ_EMI,
391 .status_mask = EMI_IRQ_MASK, 391 .status_mask = SPEAR320_EMI_IRQ_MASK,
392 .clear_mask = EMI_IRQ_MASK, 392 .clear_mask = SPEAR320_EMI_IRQ_MASK,
393 }, { 393 }, {
394 .virq = VIRQ_CLCD, 394 .virq = SPEAR320_VIRQ_CLCD,
395 .status_mask = CLCD_IRQ_MASK, 395 .status_mask = SPEAR320_CLCD_IRQ_MASK,
396 .clear_mask = CLCD_IRQ_MASK, 396 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
397 }, { 397 }, {
398 .virq = VIRQ_SPP, 398 .virq = SPEAR320_VIRQ_SPP,
399 .status_mask = SPP_IRQ_MASK, 399 .status_mask = SPEAR320_SPP_IRQ_MASK,
400 .clear_mask = SPP_IRQ_MASK, 400 .clear_mask = SPEAR320_SPP_IRQ_MASK,
401 }, 401 },
402}; 402};
403 403
404struct spear_shirq shirq_ras1 = { 404static struct spear_shirq shirq_ras1 = {
405 .irq = IRQ_GEN_RAS_1, 405 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
406 .dev_config = shirq_ras1_config, 406 .dev_config = shirq_ras1_config,
407 .dev_count = ARRAY_SIZE(shirq_ras1_config), 407 .dev_count = ARRAY_SIZE(shirq_ras1_config),
408 .regs = { 408 .regs = {
409 .enb_reg = -1, 409 .enb_reg = -1,
410 .status_reg = INT_STS_MASK_REG, 410 .status_reg = SPEAR320_INT_STS_MASK_REG,
411 .status_reg_mask = SHIRQ_RAS1_MASK, 411 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
412 .clear_reg = INT_CLR_MASK_REG, 412 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
413 .reset_to_clear = 1, 413 .reset_to_clear = 1,
414 }, 414 },
415}; 415};
416 416
417struct shirq_dev_config shirq_ras3_config[] = { 417static struct shirq_dev_config shirq_ras3_config[] = {
418 { 418 {
419 .virq = VIRQ_PLGPIO, 419 .virq = SPEAR320_VIRQ_PLGPIO,
420 .enb_mask = GPIO_IRQ_MASK, 420 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
421 .status_mask = GPIO_IRQ_MASK, 421 .status_mask = SPEAR320_GPIO_IRQ_MASK,
422 .clear_mask = GPIO_IRQ_MASK, 422 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
423 }, { 423 }, {
424 .virq = VIRQ_I2S_PLAY, 424 .virq = SPEAR320_VIRQ_I2S_PLAY,
425 .enb_mask = I2S_PLAY_IRQ_MASK, 425 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
426 .status_mask = I2S_PLAY_IRQ_MASK, 426 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
427 .clear_mask = I2S_PLAY_IRQ_MASK, 427 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
428 }, { 428 }, {
429 .virq = VIRQ_I2S_REC, 429 .virq = SPEAR320_VIRQ_I2S_REC,
430 .enb_mask = I2S_REC_IRQ_MASK, 430 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
431 .status_mask = I2S_REC_IRQ_MASK, 431 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
432 .clear_mask = I2S_REC_IRQ_MASK, 432 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
433 }, 433 },
434}; 434};
435 435
436struct spear_shirq shirq_ras3 = { 436static struct spear_shirq shirq_ras3 = {
437 .irq = IRQ_GEN_RAS_3, 437 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
438 .dev_config = shirq_ras3_config, 438 .dev_config = shirq_ras3_config,
439 .dev_count = ARRAY_SIZE(shirq_ras3_config), 439 .dev_count = ARRAY_SIZE(shirq_ras3_config),
440 .regs = { 440 .regs = {
441 .enb_reg = INT_ENB_MASK_REG, 441 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
442 .reset_to_enb = 1, 442 .reset_to_enb = 1,
443 .status_reg = INT_STS_MASK_REG, 443 .status_reg = SPEAR320_INT_STS_MASK_REG,
444 .status_reg_mask = SHIRQ_RAS3_MASK, 444 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
445 .clear_reg = INT_CLR_MASK_REG, 445 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
446 .reset_to_clear = 1, 446 .reset_to_clear = 1,
447 }, 447 },
448}; 448};
449 449
450struct shirq_dev_config shirq_intrcomm_ras_config[] = { 450static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
451 { 451 {
452 .virq = VIRQ_CANU, 452 .virq = SPEAR320_VIRQ_CANU,
453 .status_mask = CAN_U_IRQ_MASK, 453 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
454 .clear_mask = CAN_U_IRQ_MASK, 454 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
455 }, { 455 }, {
456 .virq = VIRQ_CANL, 456 .virq = SPEAR320_VIRQ_CANL,
457 .status_mask = CAN_L_IRQ_MASK, 457 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
458 .clear_mask = CAN_L_IRQ_MASK, 458 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
459 }, { 459 }, {
460 .virq = VIRQ_UART1, 460 .virq = SPEAR320_VIRQ_UART1,
461 .status_mask = UART1_IRQ_MASK, 461 .status_mask = SPEAR320_UART1_IRQ_MASK,
462 .clear_mask = UART1_IRQ_MASK, 462 .clear_mask = SPEAR320_UART1_IRQ_MASK,
463 }, { 463 }, {
464 .virq = VIRQ_UART2, 464 .virq = SPEAR320_VIRQ_UART2,
465 .status_mask = UART2_IRQ_MASK, 465 .status_mask = SPEAR320_UART2_IRQ_MASK,
466 .clear_mask = UART2_IRQ_MASK, 466 .clear_mask = SPEAR320_UART2_IRQ_MASK,
467 }, { 467 }, {
468 .virq = VIRQ_SSP1, 468 .virq = SPEAR320_VIRQ_SSP1,
469 .status_mask = SSP1_IRQ_MASK, 469 .status_mask = SPEAR320_SSP1_IRQ_MASK,
470 .clear_mask = SSP1_IRQ_MASK, 470 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
471 }, { 471 }, {
472 .virq = VIRQ_SSP2, 472 .virq = SPEAR320_VIRQ_SSP2,
473 .status_mask = SSP2_IRQ_MASK, 473 .status_mask = SPEAR320_SSP2_IRQ_MASK,
474 .clear_mask = SSP2_IRQ_MASK, 474 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
475 }, { 475 }, {
476 .virq = VIRQ_SMII0, 476 .virq = SPEAR320_VIRQ_SMII0,
477 .status_mask = SMII0_IRQ_MASK, 477 .status_mask = SPEAR320_SMII0_IRQ_MASK,
478 .clear_mask = SMII0_IRQ_MASK, 478 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
479 }, { 479 }, {
480 .virq = VIRQ_MII1_SMII1, 480 .virq = SPEAR320_VIRQ_MII1_SMII1,
481 .status_mask = MII1_SMII1_IRQ_MASK, 481 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
482 .clear_mask = MII1_SMII1_IRQ_MASK, 482 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
483 }, { 483 }, {
484 .virq = VIRQ_WAKEUP_SMII0, 484 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
485 .status_mask = WAKEUP_SMII0_IRQ_MASK, 485 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
486 .clear_mask = WAKEUP_SMII0_IRQ_MASK, 486 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
487 }, { 487 }, {
488 .virq = VIRQ_WAKEUP_MII1_SMII1, 488 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
489 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 489 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
490 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 490 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
491 }, { 491 }, {
492 .virq = VIRQ_I2C, 492 .virq = SPEAR320_VIRQ_I2C1,
493 .status_mask = I2C1_IRQ_MASK, 493 .status_mask = SPEAR320_I2C1_IRQ_MASK,
494 .clear_mask = I2C1_IRQ_MASK, 494 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
495 }, 495 },
496}; 496};
497 497
498struct spear_shirq shirq_intrcomm_ras = { 498static struct spear_shirq shirq_intrcomm_ras = {
499 .irq = IRQ_INTRCOMM_RAS_ARM, 499 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
500 .dev_config = shirq_intrcomm_ras_config, 500 .dev_config = shirq_intrcomm_ras_config,
501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
502 .regs = { 502 .regs = {
503 .enb_reg = -1, 503 .enb_reg = -1,
504 .status_reg = INT_STS_MASK_REG, 504 .status_reg = SPEAR320_INT_STS_MASK_REG,
505 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 505 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
506 .clear_reg = INT_CLR_MASK_REG, 506 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
507 .reset_to_clear = 1, 507 .reset_to_clear = 1,
508 }, 508 },
509}; 509};
@@ -511,7 +511,8 @@ struct spear_shirq shirq_intrcomm_ras = {
511/* Add spear320 specific devices here */ 511/* Add spear320 specific devices here */
512 512
513/* spear320 routines */ 513/* spear320 routines */
514void __init spear320_init(void) 514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
515 u8 pmx_dev_count)
515{ 516{
516 void __iomem *base; 517 void __iomem *base;
517 int ret = 0; 518 int ret = 0;
@@ -543,6 +544,10 @@ void __init spear320_init(void)
543 544
544 /* pmx initialization */ 545 /* pmx initialization */
545 pmx_driver.base = base; 546 pmx_driver.base = base;
547 pmx_driver.mode = pmx_mode;
548 pmx_driver.devs = pmx_devs;
549 pmx_driver.devs_count = pmx_dev_count;
550
546 ret = pmx_register(&pmx_driver); 551 ret = pmx_register(&pmx_driver);
547 if (ret) 552 if (ret)
548 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 553 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 8213e4b66c14..a12b353940d6 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -19,28 +19,28 @@
19/* padmux devices to enable */ 19/* padmux devices to enable */
20static struct pmx_dev *pmx_devs[] = { 20static struct pmx_dev *pmx_devs[] = {
21 /* spear3xx specific devices */ 21 /* spear3xx specific devices */
22 &pmx_i2c, 22 &spear3xx_pmx_i2c,
23 &pmx_ssp, 23 &spear3xx_pmx_ssp,
24 &pmx_mii, 24 &spear3xx_pmx_mii,
25 &pmx_uart0, 25 &spear3xx_pmx_uart0,
26 26
27 /* spear320 specific devices */ 27 /* spear320 specific devices */
28 &pmx_fsmc, 28 &spear320_pmx_fsmc,
29 &pmx_sdhci, 29 &spear320_pmx_sdhci,
30 &pmx_i2s, 30 &spear320_pmx_i2s,
31 &pmx_uart1, 31 &spear320_pmx_uart1,
32 &pmx_uart2, 32 &spear320_pmx_uart2,
33 &pmx_can, 33 &spear320_pmx_can,
34 &pmx_pwm0, 34 &spear320_pmx_pwm0,
35 &pmx_pwm1, 35 &spear320_pmx_pwm1,
36 &pmx_pwm2, 36 &spear320_pmx_pwm2,
37 &pmx_mii1, 37 &spear320_pmx_mii1,
38}; 38};
39 39
40static struct amba_device *amba_devs[] __initdata = { 40static struct amba_device *amba_devs[] __initdata = {
41 /* spear3xx specific devices */ 41 /* spear3xx specific devices */
42 &gpio_device, 42 &spear3xx_gpio_device,
43 &uart_device, 43 &spear3xx_uart_device,
44 44
45 /* spear320 specific devices */ 45 /* spear320 specific devices */
46}; 46};
@@ -55,13 +55,9 @@ static void __init spear320_evb_init(void)
55{ 55{
56 unsigned int i; 56 unsigned int i;
57 57
58 /* padmux initialization, must be done before spear320_init */
59 pmx_driver.mode = &auto_net_mii_mode;
60 pmx_driver.devs = pmx_devs;
61 pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
62
63 /* call spear320 machine init function */ 58 /* call spear320 machine init function */
64 spear320_init(); 59 spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
60 ARRAY_SIZE(pmx_devs));
65 61
66 /* Add Platform Devices */ 62 /* Add Platform Devices */
67 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs)); 63 platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index d3ba8ca1bc59..10af45da86a0 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -25,10 +25,10 @@
25/* gpio device registration */ 25/* gpio device registration */
26static struct pl061_platform_data gpio_plat_data = { 26static struct pl061_platform_data gpio_plat_data = {
27 .gpio_base = 0, 27 .gpio_base = 0,
28 .irq_base = SPEAR_GPIO_INT_BASE, 28 .irq_base = SPEAR3XX_GPIO_INT_BASE,
29}; 29};
30 30
31struct amba_device gpio_device = { 31struct amba_device spear3xx_gpio_device = {
32 .dev = { 32 .dev = {
33 .init_name = "gpio", 33 .init_name = "gpio",
34 .platform_data = &gpio_plat_data, 34 .platform_data = &gpio_plat_data,
@@ -38,11 +38,11 @@ struct amba_device gpio_device = {
38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1, 38 .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
39 .flags = IORESOURCE_MEM, 39 .flags = IORESOURCE_MEM,
40 }, 40 },
41 .irq = {IRQ_BASIC_GPIO, NO_IRQ}, 41 .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
42}; 42};
43 43
44/* uart device registration */ 44/* uart device registration */
45struct amba_device uart_device = { 45struct amba_device spear3xx_uart_device = {
46 .dev = { 46 .dev = {
47 .init_name = "uart", 47 .init_name = "uart",
48 }, 48 },
@@ -51,7 +51,7 @@ struct amba_device uart_device = {
51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1, 51 .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
52 .flags = IORESOURCE_MEM, 52 .flags = IORESOURCE_MEM,
53 }, 53 },
54 .irq = {IRQ_UART, NO_IRQ}, 54 .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
55}; 55};
56 56
57/* Do spear3xx familiy common initialization part here */ 57/* Do spear3xx familiy common initialization part here */
@@ -97,215 +97,215 @@ void __init spear3xx_map_io(void)
97 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); 97 iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
98 98
99 /* This will initialize clock framework */ 99 /* This will initialize clock framework */
100 clk_init(); 100 spear3xx_clk_init();
101} 101}
102 102
103/* pad multiplexing support */ 103/* pad multiplexing support */
104/* devices */ 104/* devices */
105struct pmx_dev_mode pmx_firda_modes[] = { 105static struct pmx_dev_mode pmx_firda_modes[] = {
106 { 106 {
107 .ids = 0xffffffff, 107 .ids = 0xffffffff,
108 .mask = PMX_FIRDA_MASK, 108 .mask = PMX_FIRDA_MASK,
109 }, 109 },
110}; 110};
111 111
112struct pmx_dev pmx_firda = { 112struct pmx_dev spear3xx_pmx_firda = {
113 .name = "firda", 113 .name = "firda",
114 .modes = pmx_firda_modes, 114 .modes = pmx_firda_modes,
115 .mode_count = ARRAY_SIZE(pmx_firda_modes), 115 .mode_count = ARRAY_SIZE(pmx_firda_modes),
116 .enb_on_reset = 0, 116 .enb_on_reset = 0,
117}; 117};
118 118
119struct pmx_dev_mode pmx_i2c_modes[] = { 119static struct pmx_dev_mode pmx_i2c_modes[] = {
120 { 120 {
121 .ids = 0xffffffff, 121 .ids = 0xffffffff,
122 .mask = PMX_I2C_MASK, 122 .mask = PMX_I2C_MASK,
123 }, 123 },
124}; 124};
125 125
126struct pmx_dev pmx_i2c = { 126struct pmx_dev spear3xx_pmx_i2c = {
127 .name = "i2c", 127 .name = "i2c",
128 .modes = pmx_i2c_modes, 128 .modes = pmx_i2c_modes,
129 .mode_count = ARRAY_SIZE(pmx_i2c_modes), 129 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
130 .enb_on_reset = 0, 130 .enb_on_reset = 0,
131}; 131};
132 132
133struct pmx_dev_mode pmx_ssp_cs_modes[] = { 133static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
134 { 134 {
135 .ids = 0xffffffff, 135 .ids = 0xffffffff,
136 .mask = PMX_SSP_CS_MASK, 136 .mask = PMX_SSP_CS_MASK,
137 }, 137 },
138}; 138};
139 139
140struct pmx_dev pmx_ssp_cs = { 140struct pmx_dev spear3xx_pmx_ssp_cs = {
141 .name = "ssp_chip_selects", 141 .name = "ssp_chip_selects",
142 .modes = pmx_ssp_cs_modes, 142 .modes = pmx_ssp_cs_modes,
143 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), 143 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
144 .enb_on_reset = 0, 144 .enb_on_reset = 0,
145}; 145};
146 146
147struct pmx_dev_mode pmx_ssp_modes[] = { 147static struct pmx_dev_mode pmx_ssp_modes[] = {
148 { 148 {
149 .ids = 0xffffffff, 149 .ids = 0xffffffff,
150 .mask = PMX_SSP_MASK, 150 .mask = PMX_SSP_MASK,
151 }, 151 },
152}; 152};
153 153
154struct pmx_dev pmx_ssp = { 154struct pmx_dev spear3xx_pmx_ssp = {
155 .name = "ssp", 155 .name = "ssp",
156 .modes = pmx_ssp_modes, 156 .modes = pmx_ssp_modes,
157 .mode_count = ARRAY_SIZE(pmx_ssp_modes), 157 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
158 .enb_on_reset = 0, 158 .enb_on_reset = 0,
159}; 159};
160 160
161struct pmx_dev_mode pmx_mii_modes[] = { 161static struct pmx_dev_mode pmx_mii_modes[] = {
162 { 162 {
163 .ids = 0xffffffff, 163 .ids = 0xffffffff,
164 .mask = PMX_MII_MASK, 164 .mask = PMX_MII_MASK,
165 }, 165 },
166}; 166};
167 167
168struct pmx_dev pmx_mii = { 168struct pmx_dev spear3xx_pmx_mii = {
169 .name = "mii", 169 .name = "mii",
170 .modes = pmx_mii_modes, 170 .modes = pmx_mii_modes,
171 .mode_count = ARRAY_SIZE(pmx_mii_modes), 171 .mode_count = ARRAY_SIZE(pmx_mii_modes),
172 .enb_on_reset = 0, 172 .enb_on_reset = 0,
173}; 173};
174 174
175struct pmx_dev_mode pmx_gpio_pin0_modes[] = { 175static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
176 { 176 {
177 .ids = 0xffffffff, 177 .ids = 0xffffffff,
178 .mask = PMX_GPIO_PIN0_MASK, 178 .mask = PMX_GPIO_PIN0_MASK,
179 }, 179 },
180}; 180};
181 181
182struct pmx_dev pmx_gpio_pin0 = { 182struct pmx_dev spear3xx_pmx_gpio_pin0 = {
183 .name = "gpio_pin0", 183 .name = "gpio_pin0",
184 .modes = pmx_gpio_pin0_modes, 184 .modes = pmx_gpio_pin0_modes,
185 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), 185 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
186 .enb_on_reset = 0, 186 .enb_on_reset = 0,
187}; 187};
188 188
189struct pmx_dev_mode pmx_gpio_pin1_modes[] = { 189static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
190 { 190 {
191 .ids = 0xffffffff, 191 .ids = 0xffffffff,
192 .mask = PMX_GPIO_PIN1_MASK, 192 .mask = PMX_GPIO_PIN1_MASK,
193 }, 193 },
194}; 194};
195 195
196struct pmx_dev pmx_gpio_pin1 = { 196struct pmx_dev spear3xx_pmx_gpio_pin1 = {
197 .name = "gpio_pin1", 197 .name = "gpio_pin1",
198 .modes = pmx_gpio_pin1_modes, 198 .modes = pmx_gpio_pin1_modes,
199 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), 199 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
200 .enb_on_reset = 0, 200 .enb_on_reset = 0,
201}; 201};
202 202
203struct pmx_dev_mode pmx_gpio_pin2_modes[] = { 203static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
204 { 204 {
205 .ids = 0xffffffff, 205 .ids = 0xffffffff,
206 .mask = PMX_GPIO_PIN2_MASK, 206 .mask = PMX_GPIO_PIN2_MASK,
207 }, 207 },
208}; 208};
209 209
210struct pmx_dev pmx_gpio_pin2 = { 210struct pmx_dev spear3xx_pmx_gpio_pin2 = {
211 .name = "gpio_pin2", 211 .name = "gpio_pin2",
212 .modes = pmx_gpio_pin2_modes, 212 .modes = pmx_gpio_pin2_modes,
213 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), 213 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
214 .enb_on_reset = 0, 214 .enb_on_reset = 0,
215}; 215};
216 216
217struct pmx_dev_mode pmx_gpio_pin3_modes[] = { 217static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
218 { 218 {
219 .ids = 0xffffffff, 219 .ids = 0xffffffff,
220 .mask = PMX_GPIO_PIN3_MASK, 220 .mask = PMX_GPIO_PIN3_MASK,
221 }, 221 },
222}; 222};
223 223
224struct pmx_dev pmx_gpio_pin3 = { 224struct pmx_dev spear3xx_pmx_gpio_pin3 = {
225 .name = "gpio_pin3", 225 .name = "gpio_pin3",
226 .modes = pmx_gpio_pin3_modes, 226 .modes = pmx_gpio_pin3_modes,
227 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), 227 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
228 .enb_on_reset = 0, 228 .enb_on_reset = 0,
229}; 229};
230 230
231struct pmx_dev_mode pmx_gpio_pin4_modes[] = { 231static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
232 { 232 {
233 .ids = 0xffffffff, 233 .ids = 0xffffffff,
234 .mask = PMX_GPIO_PIN4_MASK, 234 .mask = PMX_GPIO_PIN4_MASK,
235 }, 235 },
236}; 236};
237 237
238struct pmx_dev pmx_gpio_pin4 = { 238struct pmx_dev spear3xx_pmx_gpio_pin4 = {
239 .name = "gpio_pin4", 239 .name = "gpio_pin4",
240 .modes = pmx_gpio_pin4_modes, 240 .modes = pmx_gpio_pin4_modes,
241 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), 241 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
242 .enb_on_reset = 0, 242 .enb_on_reset = 0,
243}; 243};
244 244
245struct pmx_dev_mode pmx_gpio_pin5_modes[] = { 245static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
246 { 246 {
247 .ids = 0xffffffff, 247 .ids = 0xffffffff,
248 .mask = PMX_GPIO_PIN5_MASK, 248 .mask = PMX_GPIO_PIN5_MASK,
249 }, 249 },
250}; 250};
251 251
252struct pmx_dev pmx_gpio_pin5 = { 252struct pmx_dev spear3xx_pmx_gpio_pin5 = {
253 .name = "gpio_pin5", 253 .name = "gpio_pin5",
254 .modes = pmx_gpio_pin5_modes, 254 .modes = pmx_gpio_pin5_modes,
255 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), 255 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
256 .enb_on_reset = 0, 256 .enb_on_reset = 0,
257}; 257};
258 258
259struct pmx_dev_mode pmx_uart0_modem_modes[] = { 259static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
260 { 260 {
261 .ids = 0xffffffff, 261 .ids = 0xffffffff,
262 .mask = PMX_UART0_MODEM_MASK, 262 .mask = PMX_UART0_MODEM_MASK,
263 }, 263 },
264}; 264};
265 265
266struct pmx_dev pmx_uart0_modem = { 266struct pmx_dev spear3xx_pmx_uart0_modem = {
267 .name = "uart0_modem", 267 .name = "uart0_modem",
268 .modes = pmx_uart0_modem_modes, 268 .modes = pmx_uart0_modem_modes,
269 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), 269 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
270 .enb_on_reset = 0, 270 .enb_on_reset = 0,
271}; 271};
272 272
273struct pmx_dev_mode pmx_uart0_modes[] = { 273static struct pmx_dev_mode pmx_uart0_modes[] = {
274 { 274 {
275 .ids = 0xffffffff, 275 .ids = 0xffffffff,
276 .mask = PMX_UART0_MASK, 276 .mask = PMX_UART0_MASK,
277 }, 277 },
278}; 278};
279 279
280struct pmx_dev pmx_uart0 = { 280struct pmx_dev spear3xx_pmx_uart0 = {
281 .name = "uart0", 281 .name = "uart0",
282 .modes = pmx_uart0_modes, 282 .modes = pmx_uart0_modes,
283 .mode_count = ARRAY_SIZE(pmx_uart0_modes), 283 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
284 .enb_on_reset = 0, 284 .enb_on_reset = 0,
285}; 285};
286 286
287struct pmx_dev_mode pmx_timer_3_4_modes[] = { 287static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
288 { 288 {
289 .ids = 0xffffffff, 289 .ids = 0xffffffff,
290 .mask = PMX_TIMER_3_4_MASK, 290 .mask = PMX_TIMER_3_4_MASK,
291 }, 291 },
292}; 292};
293 293
294struct pmx_dev pmx_timer_3_4 = { 294struct pmx_dev spear3xx_pmx_timer_3_4 = {
295 .name = "timer_3_4", 295 .name = "timer_3_4",
296 .modes = pmx_timer_3_4_modes, 296 .modes = pmx_timer_3_4_modes,
297 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), 297 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
298 .enb_on_reset = 0, 298 .enb_on_reset = 0,
299}; 299};
300 300
301struct pmx_dev_mode pmx_timer_1_2_modes[] = { 301static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
302 { 302 {
303 .ids = 0xffffffff, 303 .ids = 0xffffffff,
304 .mask = PMX_TIMER_1_2_MASK, 304 .mask = PMX_TIMER_1_2_MASK,
305 }, 305 },
306}; 306};
307 307
308struct pmx_dev pmx_timer_1_2 = { 308struct pmx_dev spear3xx_pmx_timer_1_2 = {
309 .name = "timer_1_2", 309 .name = "timer_1_2",
310 .modes = pmx_timer_1_2_modes, 310 .modes = pmx_timer_1_2_modes,
311 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), 311 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -314,210 +314,210 @@ struct pmx_dev pmx_timer_1_2 = {
314 314
315#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) 315#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
316/* plgpios devices */ 316/* plgpios devices */
317struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { 317static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
318 { 318 {
319 .ids = 0x00, 319 .ids = 0x00,
320 .mask = PMX_FIRDA_MASK, 320 .mask = PMX_FIRDA_MASK,
321 }, 321 },
322}; 322};
323 323
324struct pmx_dev pmx_plgpio_0_1 = { 324struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
325 .name = "plgpio 0 and 1", 325 .name = "plgpio 0 and 1",
326 .modes = pmx_plgpio_0_1_modes, 326 .modes = pmx_plgpio_0_1_modes,
327 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), 327 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
328 .enb_on_reset = 1, 328 .enb_on_reset = 1,
329}; 329};
330 330
331struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { 331static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
332 { 332 {
333 .ids = 0x00, 333 .ids = 0x00,
334 .mask = PMX_UART0_MASK, 334 .mask = PMX_UART0_MASK,
335 }, 335 },
336}; 336};
337 337
338struct pmx_dev pmx_plgpio_2_3 = { 338struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
339 .name = "plgpio 2 and 3", 339 .name = "plgpio 2 and 3",
340 .modes = pmx_plgpio_2_3_modes, 340 .modes = pmx_plgpio_2_3_modes,
341 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), 341 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
342 .enb_on_reset = 1, 342 .enb_on_reset = 1,
343}; 343};
344 344
345struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { 345static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
346 { 346 {
347 .ids = 0x00, 347 .ids = 0x00,
348 .mask = PMX_I2C_MASK, 348 .mask = PMX_I2C_MASK,
349 }, 349 },
350}; 350};
351 351
352struct pmx_dev pmx_plgpio_4_5 = { 352struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
353 .name = "plgpio 4 and 5", 353 .name = "plgpio 4 and 5",
354 .modes = pmx_plgpio_4_5_modes, 354 .modes = pmx_plgpio_4_5_modes,
355 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), 355 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
356 .enb_on_reset = 1, 356 .enb_on_reset = 1,
357}; 357};
358 358
359struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { 359static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
360 { 360 {
361 .ids = 0x00, 361 .ids = 0x00,
362 .mask = PMX_SSP_MASK, 362 .mask = PMX_SSP_MASK,
363 }, 363 },
364}; 364};
365 365
366struct pmx_dev pmx_plgpio_6_9 = { 366struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
367 .name = "plgpio 6 to 9", 367 .name = "plgpio 6 to 9",
368 .modes = pmx_plgpio_6_9_modes, 368 .modes = pmx_plgpio_6_9_modes,
369 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), 369 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
370 .enb_on_reset = 1, 370 .enb_on_reset = 1,
371}; 371};
372 372
373struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { 373static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
374 { 374 {
375 .ids = 0x00, 375 .ids = 0x00,
376 .mask = PMX_MII_MASK, 376 .mask = PMX_MII_MASK,
377 }, 377 },
378}; 378};
379 379
380struct pmx_dev pmx_plgpio_10_27 = { 380struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
381 .name = "plgpio 10 to 27", 381 .name = "plgpio 10 to 27",
382 .modes = pmx_plgpio_10_27_modes, 382 .modes = pmx_plgpio_10_27_modes,
383 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), 383 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
384 .enb_on_reset = 1, 384 .enb_on_reset = 1,
385}; 385};
386 386
387struct pmx_dev_mode pmx_plgpio_28_modes[] = { 387static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
388 { 388 {
389 .ids = 0x00, 389 .ids = 0x00,
390 .mask = PMX_GPIO_PIN0_MASK, 390 .mask = PMX_GPIO_PIN0_MASK,
391 }, 391 },
392}; 392};
393 393
394struct pmx_dev pmx_plgpio_28 = { 394struct pmx_dev spear3xx_pmx_plgpio_28 = {
395 .name = "plgpio 28", 395 .name = "plgpio 28",
396 .modes = pmx_plgpio_28_modes, 396 .modes = pmx_plgpio_28_modes,
397 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), 397 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
398 .enb_on_reset = 1, 398 .enb_on_reset = 1,
399}; 399};
400 400
401struct pmx_dev_mode pmx_plgpio_29_modes[] = { 401static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
402 { 402 {
403 .ids = 0x00, 403 .ids = 0x00,
404 .mask = PMX_GPIO_PIN1_MASK, 404 .mask = PMX_GPIO_PIN1_MASK,
405 }, 405 },
406}; 406};
407 407
408struct pmx_dev pmx_plgpio_29 = { 408struct pmx_dev spear3xx_pmx_plgpio_29 = {
409 .name = "plgpio 29", 409 .name = "plgpio 29",
410 .modes = pmx_plgpio_29_modes, 410 .modes = pmx_plgpio_29_modes,
411 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), 411 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
412 .enb_on_reset = 1, 412 .enb_on_reset = 1,
413}; 413};
414 414
415struct pmx_dev_mode pmx_plgpio_30_modes[] = { 415static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
416 { 416 {
417 .ids = 0x00, 417 .ids = 0x00,
418 .mask = PMX_GPIO_PIN2_MASK, 418 .mask = PMX_GPIO_PIN2_MASK,
419 }, 419 },
420}; 420};
421 421
422struct pmx_dev pmx_plgpio_30 = { 422struct pmx_dev spear3xx_pmx_plgpio_30 = {
423 .name = "plgpio 30", 423 .name = "plgpio 30",
424 .modes = pmx_plgpio_30_modes, 424 .modes = pmx_plgpio_30_modes,
425 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), 425 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
426 .enb_on_reset = 1, 426 .enb_on_reset = 1,
427}; 427};
428 428
429struct pmx_dev_mode pmx_plgpio_31_modes[] = { 429static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
430 { 430 {
431 .ids = 0x00, 431 .ids = 0x00,
432 .mask = PMX_GPIO_PIN3_MASK, 432 .mask = PMX_GPIO_PIN3_MASK,
433 }, 433 },
434}; 434};
435 435
436struct pmx_dev pmx_plgpio_31 = { 436struct pmx_dev spear3xx_pmx_plgpio_31 = {
437 .name = "plgpio 31", 437 .name = "plgpio 31",
438 .modes = pmx_plgpio_31_modes, 438 .modes = pmx_plgpio_31_modes,
439 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), 439 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
440 .enb_on_reset = 1, 440 .enb_on_reset = 1,
441}; 441};
442 442
443struct pmx_dev_mode pmx_plgpio_32_modes[] = { 443static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
444 { 444 {
445 .ids = 0x00, 445 .ids = 0x00,
446 .mask = PMX_GPIO_PIN4_MASK, 446 .mask = PMX_GPIO_PIN4_MASK,
447 }, 447 },
448}; 448};
449 449
450struct pmx_dev pmx_plgpio_32 = { 450struct pmx_dev spear3xx_pmx_plgpio_32 = {
451 .name = "plgpio 32", 451 .name = "plgpio 32",
452 .modes = pmx_plgpio_32_modes, 452 .modes = pmx_plgpio_32_modes,
453 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), 453 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
454 .enb_on_reset = 1, 454 .enb_on_reset = 1,
455}; 455};
456 456
457struct pmx_dev_mode pmx_plgpio_33_modes[] = { 457static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
458 { 458 {
459 .ids = 0x00, 459 .ids = 0x00,
460 .mask = PMX_GPIO_PIN5_MASK, 460 .mask = PMX_GPIO_PIN5_MASK,
461 }, 461 },
462}; 462};
463 463
464struct pmx_dev pmx_plgpio_33 = { 464struct pmx_dev spear3xx_pmx_plgpio_33 = {
465 .name = "plgpio 33", 465 .name = "plgpio 33",
466 .modes = pmx_plgpio_33_modes, 466 .modes = pmx_plgpio_33_modes,
467 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), 467 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
468 .enb_on_reset = 1, 468 .enb_on_reset = 1,
469}; 469};
470 470
471struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { 471static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
472 { 472 {
473 .ids = 0x00, 473 .ids = 0x00,
474 .mask = PMX_SSP_CS_MASK, 474 .mask = PMX_SSP_CS_MASK,
475 }, 475 },
476}; 476};
477 477
478struct pmx_dev pmx_plgpio_34_36 = { 478struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
479 .name = "plgpio 34 to 36", 479 .name = "plgpio 34 to 36",
480 .modes = pmx_plgpio_34_36_modes, 480 .modes = pmx_plgpio_34_36_modes,
481 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), 481 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
482 .enb_on_reset = 1, 482 .enb_on_reset = 1,
483}; 483};
484 484
485struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { 485static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
486 { 486 {
487 .ids = 0x00, 487 .ids = 0x00,
488 .mask = PMX_UART0_MODEM_MASK, 488 .mask = PMX_UART0_MODEM_MASK,
489 }, 489 },
490}; 490};
491 491
492struct pmx_dev pmx_plgpio_37_42 = { 492struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
493 .name = "plgpio 37 to 42", 493 .name = "plgpio 37 to 42",
494 .modes = pmx_plgpio_37_42_modes, 494 .modes = pmx_plgpio_37_42_modes,
495 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), 495 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
496 .enb_on_reset = 1, 496 .enb_on_reset = 1,
497}; 497};
498 498
499struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { 499static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
500 { 500 {
501 .ids = 0x00, 501 .ids = 0x00,
502 .mask = PMX_TIMER_1_2_MASK, 502 .mask = PMX_TIMER_1_2_MASK,
503 }, 503 },
504}; 504};
505 505
506struct pmx_dev pmx_plgpio_43_44_47_48 = { 506struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
507 .name = "plgpio 43, 44, 47 and 48", 507 .name = "plgpio 43, 44, 47 and 48",
508 .modes = pmx_plgpio_43_44_47_48_modes, 508 .modes = pmx_plgpio_43_44_47_48_modes,
509 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), 509 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
510 .enb_on_reset = 1, 510 .enb_on_reset = 1,
511}; 511};
512 512
513struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { 513static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
514 { 514 {
515 .ids = 0x00, 515 .ids = 0x00,
516 .mask = PMX_TIMER_3_4_MASK, 516 .mask = PMX_TIMER_3_4_MASK,
517 }, 517 },
518}; 518};
519 519
520struct pmx_dev pmx_plgpio_45_46_49_50 = { 520struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
521 .name = "plgpio 45, 46, 49 and 50", 521 .name = "plgpio 45, 46, 49 and 50",
522 .modes = pmx_plgpio_45_46_49_50_modes, 522 .modes = pmx_plgpio_45_46_49_50_modes,
523 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), 523 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 00:43:08 -0500