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-rw-r--r--arch/arm/mach-spear3xx/Kconfig3
-rw-r--r--arch/arm/mach-spear3xx/Makefile2
-rw-r--r--arch/arm/mach-spear3xx/clock.c892
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h147
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h13
-rw-r--r--arch/arm/mach-spear3xx/spear300.c390
-rw-r--r--arch/arm/mach-spear3xx/spear310.c162
-rw-r--r--arch/arm/mach-spear3xx/spear320.c415
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c427
10 files changed, 35 insertions, 2418 deletions
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index d9fe11cb6f16..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -7,16 +7,19 @@ if ARCH_SPEAR3XX
7menu "SPEAr3xx Implementations" 7menu "SPEAr3xx Implementations"
8config MACH_SPEAR300 8config MACH_SPEAR300
9 bool "SPEAr300 Machine support with Device Tree" 9 bool "SPEAr300 Machine support with Device Tree"
10 select PINCTRL_SPEAR300
10 help 11 help
11 Supports ST SPEAr300 machine configured via the device-tree 12 Supports ST SPEAr300 machine configured via the device-tree
12 13
13config MACH_SPEAR310 14config MACH_SPEAR310
14 bool "SPEAr310 Machine support with Device Tree" 15 bool "SPEAr310 Machine support with Device Tree"
16 select PINCTRL_SPEAR310
15 help 17 help
16 Supports ST SPEAr310 machine configured via the device-tree 18 Supports ST SPEAr310 machine configured via the device-tree
17 19
18config MACH_SPEAR320 20config MACH_SPEAR320
19 bool "SPEAr320 Machine support with Device Tree" 21 bool "SPEAr320 Machine support with Device Tree"
22 select PINCTRL_SPEAR320
20 help 23 help
21 Supports ST SPEAr320 machine configured via the device-tree 24 Supports ST SPEAr320 machine configured via the device-tree
22endmenu 25endmenu
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index 17b5d83cf2d5..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# common files 5# common files
6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index cd6c11099083..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,892 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clkdev.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/of_platform.h>
19#include <asm/mach-types.h>
20#include <plat/clock.h>
21#include <mach/misc_regs.h>
22#include <mach/spear.h>
23
24#define PLL1_CTR (MISC_BASE + 0x008)
25#define PLL1_FRQ (MISC_BASE + 0x00C)
26#define PLL1_MOD (MISC_BASE + 0x010)
27#define PLL2_CTR (MISC_BASE + 0x014)
28/* PLL_CTR register masks */
29#define PLL_ENABLE 2
30#define PLL_MODE_SHIFT 4
31#define PLL_MODE_MASK 0x3
32#define PLL_MODE_NORMAL 0
33#define PLL_MODE_FRACTION 1
34#define PLL_MODE_DITH_DSB 2
35#define PLL_MODE_DITH_SSB 3
36
37#define PLL2_FRQ (MISC_BASE + 0x018)
38/* PLL FRQ register masks */
39#define PLL_DIV_N_SHIFT 0
40#define PLL_DIV_N_MASK 0xFF
41#define PLL_DIV_P_SHIFT 8
42#define PLL_DIV_P_MASK 0x7
43#define PLL_NORM_FDBK_M_SHIFT 24
44#define PLL_NORM_FDBK_M_MASK 0xFF
45#define PLL_DITH_FDBK_M_SHIFT 16
46#define PLL_DITH_FDBK_M_MASK 0xFFFF
47
48#define PLL2_MOD (MISC_BASE + 0x01C)
49#define PLL_CLK_CFG (MISC_BASE + 0x020)
50#define CORE_CLK_CFG (MISC_BASE + 0x024)
51/* CORE CLK CFG register masks */
52#define PLL_HCLK_RATIO_SHIFT 10
53#define PLL_HCLK_RATIO_MASK 0x3
54#define HCLK_PCLK_RATIO_SHIFT 8
55#define HCLK_PCLK_RATIO_MASK 0x3
56
57#define PERIP_CLK_CFG (MISC_BASE + 0x028)
58/* PERIP_CLK_CFG register masks */
59#define UART_CLK_SHIFT 4
60#define UART_CLK_MASK 0x1
61#define FIRDA_CLK_SHIFT 5
62#define FIRDA_CLK_MASK 0x3
63#define GPT0_CLK_SHIFT 8
64#define GPT1_CLK_SHIFT 11
65#define GPT2_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART_CLK_ENB 3
73#define SSP_CLK_ENB 5
74#define I2C_CLK_ENB 7
75#define JPEG_CLK_ENB 8
76#define FIRDA_CLK_ENB 10
77#define GPT1_CLK_ENB 11
78#define GPT2_CLK_ENB 12
79#define ADC_CLK_ENB 15
80#define RTC_CLK_ENB 17
81#define GPIO_CLK_ENB 18
82#define DMA_CLK_ENB 19
83#define SMI_CLK_ENB 21
84#define GMAC_CLK_ENB 23
85#define USBD_CLK_ENB 24
86#define USBH_CLK_ENB 25
87#define C3_CLK_ENB 31
88
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90
91#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
92#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
93#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
94/* gpt synthesizer register masks */
95#define GPT_MSCALE_SHIFT 0
96#define GPT_MSCALE_MASK 0xFFF
97#define GPT_NSCALE_SHIFT 12
98#define GPT_NSCALE_MASK 0xF
99
100#define AMEM_CLK_CFG (MISC_BASE + 0x050)
101#define EXPI_CLK_CFG (MISC_BASE + 0x054)
102#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
103#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
104#define UART_CLK_SYNT (MISC_BASE + 0x064)
105#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
106#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
107#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
108#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
109#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
110/* aux clk synthesiser register masks for irda to ras4 */
111#define AUX_SYNT_ENB 31
112#define AUX_EQ_SEL_SHIFT 30
113#define AUX_EQ_SEL_MASK 1
114#define AUX_EQ1_SEL 0
115#define AUX_EQ2_SEL 1
116#define AUX_XSCALE_SHIFT 16
117#define AUX_XSCALE_MASK 0xFFF
118#define AUX_YSCALE_SHIFT 0
119#define AUX_YSCALE_MASK 0xFFF
120
121/* root clks */
122/* 32 KHz oscillator clock */
123static struct clk osc_32k_clk = {
124 .flags = ALWAYS_ENABLED,
125 .rate = 32000,
126};
127
128/* 24 MHz oscillator clock */
129static struct clk osc_24m_clk = {
130 .flags = ALWAYS_ENABLED,
131 .rate = 24000000,
132};
133
134/* clock derived from 32 KHz osc clk */
135/* rtc clock */
136static struct clk rtc_clk = {
137 .pclk = &osc_32k_clk,
138 .en_reg = PERIP1_CLK_ENB,
139 .en_reg_bit = RTC_CLK_ENB,
140 .recalc = &follow_parent,
141};
142
143/* clock derived from 24 MHz osc clk */
144/* pll masks structure */
145static struct pll_clk_masks pll1_masks = {
146 .mode_mask = PLL_MODE_MASK,
147 .mode_shift = PLL_MODE_SHIFT,
148 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
149 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
150 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
151 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
152 .div_p_mask = PLL_DIV_P_MASK,
153 .div_p_shift = PLL_DIV_P_SHIFT,
154 .div_n_mask = PLL_DIV_N_MASK,
155 .div_n_shift = PLL_DIV_N_SHIFT,
156};
157
158/* pll1 configuration structure */
159static struct pll_clk_config pll1_config = {
160 .mode_reg = PLL1_CTR,
161 .cfg_reg = PLL1_FRQ,
162 .masks = &pll1_masks,
163};
164
165/* pll rate configuration table, in ascending order of rates */
166struct pll_rate_tbl pll_rtbl[] = {
167 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
168 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
169};
170
171/* PLL1 clock */
172static struct clk pll1_clk = {
173 .flags = ENABLED_ON_INIT,
174 .pclk = &osc_24m_clk,
175 .en_reg = PLL1_CTR,
176 .en_reg_bit = PLL_ENABLE,
177 .calc_rate = &pll_calc_rate,
178 .recalc = &pll_clk_recalc,
179 .set_rate = &pll_clk_set_rate,
180 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
181 .private_data = &pll1_config,
182};
183
184/* PLL3 48 MHz clock */
185static struct clk pll3_48m_clk = {
186 .flags = ALWAYS_ENABLED,
187 .pclk = &osc_24m_clk,
188 .rate = 48000000,
189};
190
191/* watch dog timer clock */
192static struct clk wdt_clk = {
193 .flags = ALWAYS_ENABLED,
194 .pclk = &osc_24m_clk,
195 .recalc = &follow_parent,
196};
197
198/* clock derived from pll1 clk */
199/* cpu clock */
200static struct clk cpu_clk = {
201 .flags = ALWAYS_ENABLED,
202 .pclk = &pll1_clk,
203 .recalc = &follow_parent,
204};
205
206/* ahb masks structure */
207static struct bus_clk_masks ahb_masks = {
208 .mask = PLL_HCLK_RATIO_MASK,
209 .shift = PLL_HCLK_RATIO_SHIFT,
210};
211
212/* ahb configuration structure */
213static struct bus_clk_config ahb_config = {
214 .reg = CORE_CLK_CFG,
215 .masks = &ahb_masks,
216};
217
218/* ahb rate configuration table, in ascending order of rates */
219struct bus_rate_tbl bus_rtbl[] = {
220 {.div = 3}, /* == parent divided by 4 */
221 {.div = 2}, /* == parent divided by 3 */
222 {.div = 1}, /* == parent divided by 2 */
223 {.div = 0}, /* == parent divided by 1 */
224};
225
226/* ahb clock */
227static struct clk ahb_clk = {
228 .flags = ALWAYS_ENABLED,
229 .pclk = &pll1_clk,
230 .calc_rate = &bus_calc_rate,
231 .recalc = &bus_clk_recalc,
232 .set_rate = &bus_clk_set_rate,
233 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
234 .private_data = &ahb_config,
235};
236
237/* auxiliary synthesizers masks */
238static struct aux_clk_masks aux_masks = {
239 .eq_sel_mask = AUX_EQ_SEL_MASK,
240 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
241 .eq1_mask = AUX_EQ1_SEL,
242 .eq2_mask = AUX_EQ2_SEL,
243 .xscale_sel_mask = AUX_XSCALE_MASK,
244 .xscale_sel_shift = AUX_XSCALE_SHIFT,
245 .yscale_sel_mask = AUX_YSCALE_MASK,
246 .yscale_sel_shift = AUX_YSCALE_SHIFT,
247};
248
249/* uart synth configurations */
250static struct aux_clk_config uart_synth_config = {
251 .synth_reg = UART_CLK_SYNT,
252 .masks = &aux_masks,
253};
254
255/* aux rate configuration table, in ascending order of rates */
256struct aux_rate_tbl aux_rtbl[] = {
257 /* For PLL1 = 332 MHz */
258 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
259 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
260 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
261};
262
263/* uart synth clock */
264static struct clk uart_synth_clk = {
265 .en_reg = UART_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
272 .private_data = &uart_synth_config,
273};
274
275/* uart parents */
276static struct pclk_info uart_pclk_info[] = {
277 {
278 .pclk = &uart_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* uart parent select structure */
287static struct pclk_sel uart_pclk_sel = {
288 .pclk_info = uart_pclk_info,
289 .pclk_count = ARRAY_SIZE(uart_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = UART_CLK_MASK,
292};
293
294/* uart clock */
295static struct clk uart_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = UART_CLK_ENB,
298 .pclk_sel = &uart_pclk_sel,
299 .pclk_sel_shift = UART_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* firda configurations */
304static struct aux_clk_config firda_synth_config = {
305 .synth_reg = FIRDA_CLK_SYNT,
306 .masks = &aux_masks,
307};
308
309/* firda synth clock */
310static struct clk firda_synth_clk = {
311 .en_reg = FIRDA_CLK_SYNT,
312 .en_reg_bit = AUX_SYNT_ENB,
313 .pclk = &pll1_clk,
314 .calc_rate = &aux_calc_rate,
315 .recalc = &aux_clk_recalc,
316 .set_rate = &aux_clk_set_rate,
317 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
318 .private_data = &firda_synth_config,
319};
320
321/* firda parents */
322static struct pclk_info firda_pclk_info[] = {
323 {
324 .pclk = &firda_synth_clk,
325 .pclk_val = AUX_CLK_PLL1_VAL,
326 }, {
327 .pclk = &pll3_48m_clk,
328 .pclk_val = AUX_CLK_PLL3_VAL,
329 },
330};
331
332/* firda parent select structure */
333static struct pclk_sel firda_pclk_sel = {
334 .pclk_info = firda_pclk_info,
335 .pclk_count = ARRAY_SIZE(firda_pclk_info),
336 .pclk_sel_reg = PERIP_CLK_CFG,
337 .pclk_sel_mask = FIRDA_CLK_MASK,
338};
339
340/* firda clock */
341static struct clk firda_clk = {
342 .en_reg = PERIP1_CLK_ENB,
343 .en_reg_bit = FIRDA_CLK_ENB,
344 .pclk_sel = &firda_pclk_sel,
345 .pclk_sel_shift = FIRDA_CLK_SHIFT,
346 .recalc = &follow_parent,
347};
348
349/* gpt synthesizer masks */
350static struct gpt_clk_masks gpt_masks = {
351 .mscale_sel_mask = GPT_MSCALE_MASK,
352 .mscale_sel_shift = GPT_MSCALE_SHIFT,
353 .nscale_sel_mask = GPT_NSCALE_MASK,
354 .nscale_sel_shift = GPT_NSCALE_SHIFT,
355};
356
357/* gpt rate configuration table, in ascending order of rates */
358struct gpt_rate_tbl gpt_rtbl[] = {
359 /* For pll1 = 332 MHz */
360 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
361 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
362 {.mscale = 1, .nscale = 0}, /* 83 MHz */
363};
364
365/* gpt0 synth clk config*/
366static struct gpt_clk_config gpt0_synth_config = {
367 .synth_reg = PRSC1_CLK_CFG,
368 .masks = &gpt_masks,
369};
370
371/* gpt synth clock */
372static struct clk gpt0_synth_clk = {
373 .flags = ALWAYS_ENABLED,
374 .pclk = &pll1_clk,
375 .calc_rate = &gpt_calc_rate,
376 .recalc = &gpt_clk_recalc,
377 .set_rate = &gpt_clk_set_rate,
378 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
379 .private_data = &gpt0_synth_config,
380};
381
382/* gpt parents */
383static struct pclk_info gpt0_pclk_info[] = {
384 {
385 .pclk = &gpt0_synth_clk,
386 .pclk_val = AUX_CLK_PLL1_VAL,
387 }, {
388 .pclk = &pll3_48m_clk,
389 .pclk_val = AUX_CLK_PLL3_VAL,
390 },
391};
392
393/* gpt parent select structure */
394static struct pclk_sel gpt0_pclk_sel = {
395 .pclk_info = gpt0_pclk_info,
396 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
397 .pclk_sel_reg = PERIP_CLK_CFG,
398 .pclk_sel_mask = GPT_CLK_MASK,
399};
400
401/* gpt0 timer clock */
402static struct clk gpt0_clk = {
403 .flags = ALWAYS_ENABLED,
404 .pclk_sel = &gpt0_pclk_sel,
405 .pclk_sel_shift = GPT0_CLK_SHIFT,
406 .recalc = &follow_parent,
407};
408
409/* gpt1 synth clk configurations */
410static struct gpt_clk_config gpt1_synth_config = {
411 .synth_reg = PRSC2_CLK_CFG,
412 .masks = &gpt_masks,
413};
414
415/* gpt1 synth clock */
416static struct clk gpt1_synth_clk = {
417 .flags = ALWAYS_ENABLED,
418 .pclk = &pll1_clk,
419 .calc_rate = &gpt_calc_rate,
420 .recalc = &gpt_clk_recalc,
421 .set_rate = &gpt_clk_set_rate,
422 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
423 .private_data = &gpt1_synth_config,
424};
425
426static struct pclk_info gpt1_pclk_info[] = {
427 {
428 .pclk = &gpt1_synth_clk,
429 .pclk_val = AUX_CLK_PLL1_VAL,
430 }, {
431 .pclk = &pll3_48m_clk,
432 .pclk_val = AUX_CLK_PLL3_VAL,
433 },
434};
435
436/* gpt parent select structure */
437static struct pclk_sel gpt1_pclk_sel = {
438 .pclk_info = gpt1_pclk_info,
439 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
440 .pclk_sel_reg = PERIP_CLK_CFG,
441 .pclk_sel_mask = GPT_CLK_MASK,
442};
443
444/* gpt1 timer clock */
445static struct clk gpt1_clk = {
446 .en_reg = PERIP1_CLK_ENB,
447 .en_reg_bit = GPT1_CLK_ENB,
448 .pclk_sel = &gpt1_pclk_sel,
449 .pclk_sel_shift = GPT1_CLK_SHIFT,
450 .recalc = &follow_parent,
451};
452
453/* gpt2 synth clk configurations */
454static struct gpt_clk_config gpt2_synth_config = {
455 .synth_reg = PRSC3_CLK_CFG,
456 .masks = &gpt_masks,
457};
458
459/* gpt1 synth clock */
460static struct clk gpt2_synth_clk = {
461 .flags = ALWAYS_ENABLED,
462 .pclk = &pll1_clk,
463 .calc_rate = &gpt_calc_rate,
464 .recalc = &gpt_clk_recalc,
465 .set_rate = &gpt_clk_set_rate,
466 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
467 .private_data = &gpt2_synth_config,
468};
469
470static struct pclk_info gpt2_pclk_info[] = {
471 {
472 .pclk = &gpt2_synth_clk,
473 .pclk_val = AUX_CLK_PLL1_VAL,
474 }, {
475 .pclk = &pll3_48m_clk,
476 .pclk_val = AUX_CLK_PLL3_VAL,
477 },
478};
479
480/* gpt parent select structure */
481static struct pclk_sel gpt2_pclk_sel = {
482 .pclk_info = gpt2_pclk_info,
483 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
484 .pclk_sel_reg = PERIP_CLK_CFG,
485 .pclk_sel_mask = GPT_CLK_MASK,
486};
487
488/* gpt2 timer clock */
489static struct clk gpt2_clk = {
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = GPT2_CLK_ENB,
492 .pclk_sel = &gpt2_pclk_sel,
493 .pclk_sel_shift = GPT2_CLK_SHIFT,
494 .recalc = &follow_parent,
495};
496
497/* clock derived from pll3 clk */
498/* usbh clock */
499static struct clk usbh_clk = {
500 .pclk = &pll3_48m_clk,
501 .en_reg = PERIP1_CLK_ENB,
502 .en_reg_bit = USBH_CLK_ENB,
503 .recalc = &follow_parent,
504};
505
506/* usbd clock */
507static struct clk usbd_clk = {
508 .pclk = &pll3_48m_clk,
509 .en_reg = PERIP1_CLK_ENB,
510 .en_reg_bit = USBD_CLK_ENB,
511 .recalc = &follow_parent,
512};
513
514/* clock derived from usbh clk */
515/* usbh0 clock */
516static struct clk usbh0_clk = {
517 .flags = ALWAYS_ENABLED,
518 .pclk = &usbh_clk,
519 .recalc = &follow_parent,
520};
521
522/* usbh1 clock */
523static struct clk usbh1_clk = {
524 .flags = ALWAYS_ENABLED,
525 .pclk = &usbh_clk,
526 .recalc = &follow_parent,
527};
528
529/* clock derived from ahb clk */
530/* apb masks structure */
531static struct bus_clk_masks apb_masks = {
532 .mask = HCLK_PCLK_RATIO_MASK,
533 .shift = HCLK_PCLK_RATIO_SHIFT,
534};
535
536/* apb configuration structure */
537static struct bus_clk_config apb_config = {
538 .reg = CORE_CLK_CFG,
539 .masks = &apb_masks,
540};
541
542/* apb clock */
543static struct clk apb_clk = {
544 .flags = ALWAYS_ENABLED,
545 .pclk = &ahb_clk,
546 .calc_rate = &bus_calc_rate,
547 .recalc = &bus_clk_recalc,
548 .set_rate = &bus_clk_set_rate,
549 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
550 .private_data = &apb_config,
551};
552
553/* i2c clock */
554static struct clk i2c_clk = {
555 .pclk = &ahb_clk,
556 .en_reg = PERIP1_CLK_ENB,
557 .en_reg_bit = I2C_CLK_ENB,
558 .recalc = &follow_parent,
559};
560
561/* dma clock */
562static struct clk dma_clk = {
563 .pclk = &ahb_clk,
564 .en_reg = PERIP1_CLK_ENB,
565 .en_reg_bit = DMA_CLK_ENB,
566 .recalc = &follow_parent,
567};
568
569/* jpeg clock */
570static struct clk jpeg_clk = {
571 .pclk = &ahb_clk,
572 .en_reg = PERIP1_CLK_ENB,
573 .en_reg_bit = JPEG_CLK_ENB,
574 .recalc = &follow_parent,
575};
576
577/* gmac clock */
578static struct clk gmac_clk = {
579 .pclk = &ahb_clk,
580 .en_reg = PERIP1_CLK_ENB,
581 .en_reg_bit = GMAC_CLK_ENB,
582 .recalc = &follow_parent,
583};
584
585/* smi clock */
586static struct clk smi_clk = {
587 .pclk = &ahb_clk,
588 .en_reg = PERIP1_CLK_ENB,
589 .en_reg_bit = SMI_CLK_ENB,
590 .recalc = &follow_parent,
591};
592
593/* c3 clock */
594static struct clk c3_clk = {
595 .pclk = &ahb_clk,
596 .en_reg = PERIP1_CLK_ENB,
597 .en_reg_bit = C3_CLK_ENB,
598 .recalc = &follow_parent,
599};
600
601/* clock derived from apb clk */
602/* adc clock */
603static struct clk adc_clk = {
604 .pclk = &apb_clk,
605 .en_reg = PERIP1_CLK_ENB,
606 .en_reg_bit = ADC_CLK_ENB,
607 .recalc = &follow_parent,
608};
609
610#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
611/* emi clock */
612static struct clk emi_clk = {
613 .flags = ALWAYS_ENABLED,
614 .pclk = &ahb_clk,
615 .recalc = &follow_parent,
616};
617#endif
618
619/* ssp clock */
620static struct clk ssp0_clk = {
621 .pclk = &apb_clk,
622 .en_reg = PERIP1_CLK_ENB,
623 .en_reg_bit = SSP_CLK_ENB,
624 .recalc = &follow_parent,
625};
626
627/* gpio clock */
628static struct clk gpio_clk = {
629 .pclk = &apb_clk,
630 .en_reg = PERIP1_CLK_ENB,
631 .en_reg_bit = GPIO_CLK_ENB,
632 .recalc = &follow_parent,
633};
634
635static struct clk dummy_apb_pclk;
636
637#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
638 defined(CONFIG_MACH_SPEAR320)
639/* fsmc clock */
640static struct clk fsmc_clk = {
641 .flags = ALWAYS_ENABLED,
642 .pclk = &ahb_clk,
643 .recalc = &follow_parent,
644};
645#endif
646
647/* common clocks to spear310 and spear320 */
648#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
649/* uart1 clock */
650static struct clk uart1_clk = {
651 .flags = ALWAYS_ENABLED,
652 .pclk = &apb_clk,
653 .recalc = &follow_parent,
654};
655
656/* uart2 clock */
657static struct clk uart2_clk = {
658 .flags = ALWAYS_ENABLED,
659 .pclk = &apb_clk,
660 .recalc = &follow_parent,
661};
662#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
663
664/* common clocks to spear300 and spear320 */
665#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
666/* clcd clock */
667static struct clk clcd_clk = {
668 .flags = ALWAYS_ENABLED,
669 .pclk = &pll3_48m_clk,
670 .recalc = &follow_parent,
671};
672
673/* sdhci clock */
674static struct clk sdhci_clk = {
675 .flags = ALWAYS_ENABLED,
676 .pclk = &ahb_clk,
677 .recalc = &follow_parent,
678};
679#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
680
681/* spear300 machine specific clock structures */
682#ifdef CONFIG_MACH_SPEAR300
683/* gpio1 clock */
684static struct clk gpio1_clk = {
685 .flags = ALWAYS_ENABLED,
686 .pclk = &apb_clk,
687 .recalc = &follow_parent,
688};
689
690/* keyboard clock */
691static struct clk kbd_clk = {
692 .flags = ALWAYS_ENABLED,
693 .pclk = &apb_clk,
694 .recalc = &follow_parent,
695};
696
697#endif
698
699/* spear310 machine specific clock structures */
700#ifdef CONFIG_MACH_SPEAR310
701/* uart3 clock */
702static struct clk uart3_clk = {
703 .flags = ALWAYS_ENABLED,
704 .pclk = &apb_clk,
705 .recalc = &follow_parent,
706};
707
708/* uart4 clock */
709static struct clk uart4_clk = {
710 .flags = ALWAYS_ENABLED,
711 .pclk = &apb_clk,
712 .recalc = &follow_parent,
713};
714
715/* uart5 clock */
716static struct clk uart5_clk = {
717 .flags = ALWAYS_ENABLED,
718 .pclk = &apb_clk,
719 .recalc = &follow_parent,
720};
721#endif
722
723/* spear320 machine specific clock structures */
724#ifdef CONFIG_MACH_SPEAR320
725/* can0 clock */
726static struct clk can0_clk = {
727 .flags = ALWAYS_ENABLED,
728 .pclk = &apb_clk,
729 .recalc = &follow_parent,
730};
731
732/* can1 clock */
733static struct clk can1_clk = {
734 .flags = ALWAYS_ENABLED,
735 .pclk = &apb_clk,
736 .recalc = &follow_parent,
737};
738
739/* i2c1 clock */
740static struct clk i2c1_clk = {
741 .flags = ALWAYS_ENABLED,
742 .pclk = &ahb_clk,
743 .recalc = &follow_parent,
744};
745
746/* ssp1 clock */
747static struct clk ssp1_clk = {
748 .flags = ALWAYS_ENABLED,
749 .pclk = &apb_clk,
750 .recalc = &follow_parent,
751};
752
753/* ssp2 clock */
754static struct clk ssp2_clk = {
755 .flags = ALWAYS_ENABLED,
756 .pclk = &apb_clk,
757 .recalc = &follow_parent,
758};
759
760/* pwm clock */
761static struct clk pwm_clk = {
762 .flags = ALWAYS_ENABLED,
763 .pclk = &apb_clk,
764 .recalc = &follow_parent,
765};
766#endif
767
768/* array of all spear 3xx clock lookups */
769static struct clk_lookup spear_clk_lookups[] = {
770 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
771 /* root clks */
772 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
773 CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
774 /* clock derived from 32 KHz osc clk */
775 CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
776 /* clock derived from 24 MHz osc clk */
777 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
778 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
779 CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
780 /* clock derived from pll1 clk */
781 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
782 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
783 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
784 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
785 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
786 CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
787 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
788 CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
789 CLKDEV_INIT("firda", NULL, &firda_clk),
790 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
791 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
792 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
793 /* clock derived from pll3 clk */
794 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
795 CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
796 /* clock derived from usbh clk */
797 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
798 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
799 /* clock derived from ahb clk */
800 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
801 CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
802 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
803 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
804 CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
805 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
806 CLKDEV_INIT("c3", NULL, &c3_clk),
807 /* clock derived from apb clk */
808 CLKDEV_INIT("adc", NULL, &adc_clk),
809 CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
810 CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
811};
812
813/* array of all spear 300 clock lookups */
814#ifdef CONFIG_MACH_SPEAR300
815static struct clk_lookup spear300_clk_lookups[] = {
816 CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
817 CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
818 CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
819 CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
820 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
821};
822
823void __init spear300_clk_init(void)
824{
825 int i;
826
827 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
828 clk_register(&spear_clk_lookups[i]);
829
830 for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
831 clk_register(&spear300_clk_lookups[i]);
832
833 clk_init();
834}
835#endif
836
837/* array of all spear 310 clock lookups */
838#ifdef CONFIG_MACH_SPEAR310
839static struct clk_lookup spear310_clk_lookups[] = {
840 CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
841 CLKDEV_INIT(NULL, "emi", &emi_clk),
842 CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
843 CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
844 CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
845 CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
846 CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
847};
848
849void __init spear310_clk_init(void)
850{
851 int i;
852
853 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
854 clk_register(&spear_clk_lookups[i]);
855
856 for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
857 clk_register(&spear310_clk_lookups[i]);
858
859 clk_init();
860}
861#endif
862
863/* array of all spear 320 clock lookups */
864#ifdef CONFIG_MACH_SPEAR320
865static struct clk_lookup spear320_clk_lookups[] = {
866 CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
867 CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
868 CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
869 CLKDEV_INIT(NULL, "emi", &emi_clk),
870 CLKDEV_INIT("pwm", NULL, &pwm_clk),
871 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
872 CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
873 CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
874 CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
875 CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
876 CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
877 CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
878};
879
880void __init spear320_clk_init(void)
881{
882 int i;
883
884 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
885 clk_register(&spear_clk_lookups[i]);
886
887 for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
888 clk_register(&spear320_clk_lookups[i]);
889
890 clk_init();
891}
892#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index efb69357429a..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -20,7 +20,6 @@
20#include <linux/amba/bus.h> 20#include <linux/amba/bus.h>
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h>
24 23
25/* Add spear3xx family device structure declarations here */ 24/* Add spear3xx family device structure declarations here */
26extern struct sys_timer spear3xx_timer; 25extern struct sys_timer spear3xx_timer;
@@ -29,154 +28,10 @@ extern struct pl08x_platform_data pl080_plat_data;
29 28
30/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
31void __init spear_setup_of_timer(void); 30void __init spear_setup_of_timer(void);
31void __init spear3xx_clk_init(void);
32void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
33void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
34 34
35void spear_restart(char, const char *); 35void spear_restart(char, const char *);
36 36
37/* pad mux declarations */
38#define PMX_FIRDA_MASK (1 << 14)
39#define PMX_I2C_MASK (1 << 13)
40#define PMX_SSP_CS_MASK (1 << 12)
41#define PMX_SSP_MASK (1 << 11)
42#define PMX_MII_MASK (1 << 10)
43#define PMX_GPIO_PIN0_MASK (1 << 9)
44#define PMX_GPIO_PIN1_MASK (1 << 8)
45#define PMX_GPIO_PIN2_MASK (1 << 7)
46#define PMX_GPIO_PIN3_MASK (1 << 6)
47#define PMX_GPIO_PIN4_MASK (1 << 5)
48#define PMX_GPIO_PIN5_MASK (1 << 4)
49#define PMX_UART0_MODEM_MASK (1 << 3)
50#define PMX_UART0_MASK (1 << 2)
51#define PMX_TIMER_3_4_MASK (1 << 1)
52#define PMX_TIMER_1_2_MASK (1 << 0)
53
54/* pad mux devices */
55extern struct pmx_dev spear3xx_pmx_firda;
56extern struct pmx_dev spear3xx_pmx_i2c;
57extern struct pmx_dev spear3xx_pmx_ssp_cs;
58extern struct pmx_dev spear3xx_pmx_ssp;
59extern struct pmx_dev spear3xx_pmx_mii;
60extern struct pmx_dev spear3xx_pmx_gpio_pin0;
61extern struct pmx_dev spear3xx_pmx_gpio_pin1;
62extern struct pmx_dev spear3xx_pmx_gpio_pin2;
63extern struct pmx_dev spear3xx_pmx_gpio_pin3;
64extern struct pmx_dev spear3xx_pmx_gpio_pin4;
65extern struct pmx_dev spear3xx_pmx_gpio_pin5;
66extern struct pmx_dev spear3xx_pmx_uart0_modem;
67extern struct pmx_dev spear3xx_pmx_uart0;
68extern struct pmx_dev spear3xx_pmx_timer_3_4;
69extern struct pmx_dev spear3xx_pmx_timer_1_2;
70
71#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
72/* padmux plgpio devices */
73extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
74extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
75extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
76extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
77extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
78extern struct pmx_dev spear3xx_pmx_plgpio_28;
79extern struct pmx_dev spear3xx_pmx_plgpio_29;
80extern struct pmx_dev spear3xx_pmx_plgpio_30;
81extern struct pmx_dev spear3xx_pmx_plgpio_31;
82extern struct pmx_dev spear3xx_pmx_plgpio_32;
83extern struct pmx_dev spear3xx_pmx_plgpio_33;
84extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
85extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
86extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
87extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
88#endif
89
90/* spear300 declarations */
91#ifdef CONFIG_MACH_SPEAR300
92/* pad mux modes */
93extern struct pmx_mode spear300_nand_mode;
94extern struct pmx_mode spear300_nor_mode;
95extern struct pmx_mode spear300_photo_frame_mode;
96extern struct pmx_mode spear300_lend_ip_phone_mode;
97extern struct pmx_mode spear300_hend_ip_phone_mode;
98extern struct pmx_mode spear300_lend_wifi_phone_mode;
99extern struct pmx_mode spear300_hend_wifi_phone_mode;
100extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
101extern struct pmx_mode spear300_ata_pabx_i2s_mode;
102extern struct pmx_mode spear300_caml_lcdw_mode;
103extern struct pmx_mode spear300_camu_lcd_mode;
104extern struct pmx_mode spear300_camu_wlcd_mode;
105extern struct pmx_mode spear300_caml_lcd_mode;
106
107/* pad mux devices */
108extern struct pmx_dev spear300_pmx_fsmc_2_chips;
109extern struct pmx_dev spear300_pmx_fsmc_4_chips;
110extern struct pmx_dev spear300_pmx_keyboard;
111extern struct pmx_dev spear300_pmx_clcd;
112extern struct pmx_dev spear300_pmx_telecom_gpio;
113extern struct pmx_dev spear300_pmx_telecom_tdm;
114extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
115extern struct pmx_dev spear300_pmx_telecom_camera;
116extern struct pmx_dev spear300_pmx_telecom_dac;
117extern struct pmx_dev spear300_pmx_telecom_i2s;
118extern struct pmx_dev spear300_pmx_telecom_boot_pins;
119extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
120extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
121extern struct pmx_dev spear300_pmx_gpio1;
122
123/* Add spear300 machine declarations here */
124void __init spear300_clk_init(void);
125
126#endif /* CONFIG_MACH_SPEAR300 */
127
128/* spear310 declarations */
129#ifdef CONFIG_MACH_SPEAR310
130/* pad mux devices */
131extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
132extern struct pmx_dev spear310_pmx_emi_cs_2_3;
133extern struct pmx_dev spear310_pmx_uart1;
134extern struct pmx_dev spear310_pmx_uart2;
135extern struct pmx_dev spear310_pmx_uart3_4_5;
136extern struct pmx_dev spear310_pmx_fsmc;
137extern struct pmx_dev spear310_pmx_rs485_0_1;
138extern struct pmx_dev spear310_pmx_tdm0;
139
140/* Add spear310 machine declarations here */
141void __init spear310_clk_init(void);
142
143#endif /* CONFIG_MACH_SPEAR310 */
144
145/* spear320 declarations */
146#ifdef CONFIG_MACH_SPEAR320
147/* pad mux modes */
148extern struct pmx_mode spear320_auto_net_smii_mode;
149extern struct pmx_mode spear320_auto_net_mii_mode;
150extern struct pmx_mode spear320_auto_exp_mode;
151extern struct pmx_mode spear320_small_printers_mode;
152
153/* pad mux devices */
154extern struct pmx_dev spear320_pmx_clcd;
155extern struct pmx_dev spear320_pmx_emi;
156extern struct pmx_dev spear320_pmx_fsmc;
157extern struct pmx_dev spear320_pmx_spp;
158extern struct pmx_dev spear320_pmx_sdhci;
159extern struct pmx_dev spear320_pmx_i2s;
160extern struct pmx_dev spear320_pmx_uart1;
161extern struct pmx_dev spear320_pmx_uart1_modem;
162extern struct pmx_dev spear320_pmx_uart2;
163extern struct pmx_dev spear320_pmx_touchscreen;
164extern struct pmx_dev spear320_pmx_can;
165extern struct pmx_dev spear320_pmx_sdhci_led;
166extern struct pmx_dev spear320_pmx_pwm0;
167extern struct pmx_dev spear320_pmx_pwm1;
168extern struct pmx_dev spear320_pmx_pwm2;
169extern struct pmx_dev spear320_pmx_pwm3;
170extern struct pmx_dev spear320_pmx_ssp1;
171extern struct pmx_dev spear320_pmx_ssp2;
172extern struct pmx_dev spear320_pmx_mii1;
173extern struct pmx_dev spear320_pmx_smii0;
174extern struct pmx_dev spear320_pmx_smii1;
175extern struct pmx_dev spear320_pmx_i2c1;
176
177/* Add spear320 machine declarations here */
178void __init spear320_clk_init(void);
179
180#endif /* CONFIG_MACH_SPEAR320 */
181
182#endif /* __MACH_GENERIC_H */ 37#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index e0ab72e61507..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/spear.h>
18
17#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
18#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
19 21
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 04da906b0d4c..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -44,4 +44,17 @@
44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
46 46
47/* SPEAr320 Macros */
48#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
49#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
50#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
51#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
52 #define SPEAR320_UARTX_PCLK_MASK 0x1
53 #define SPEAR320_UART2_PCLK_SHIFT 8
54 #define SPEAR320_UART3_PCLK_SHIFT 9
55 #define SPEAR320_UART4_PCLK_SHIFT 10
56 #define SPEAR320_UART5_PCLK_SHIFT 11
57 #define SPEAR320_UART6_PCLK_SHIFT 12
58 #define SPEAR320_RS485_PCLK_SHIFT 13
59
47#endif /* __MACH_SPEAR3XX_H */ 60#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index febcdd8d4e92..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -60,357 +60,6 @@
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ 60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
62 62
63/* pad multiplexing support */
64/* muxing registers */
65#define PAD_MUX_CONFIG_REG 0x00
66#define MODE_CONFIG_REG 0x04
67
68/* modes */
69#define NAND_MODE (1 << 0)
70#define NOR_MODE (1 << 1)
71#define PHOTO_FRAME_MODE (1 << 2)
72#define LEND_IP_PHONE_MODE (1 << 3)
73#define HEND_IP_PHONE_MODE (1 << 4)
74#define LEND_WIFI_PHONE_MODE (1 << 5)
75#define HEND_WIFI_PHONE_MODE (1 << 6)
76#define ATA_PABX_WI2S_MODE (1 << 7)
77#define ATA_PABX_I2S_MODE (1 << 8)
78#define CAML_LCDW_MODE (1 << 9)
79#define CAMU_LCD_MODE (1 << 10)
80#define CAMU_WLCD_MODE (1 << 11)
81#define CAML_LCD_MODE (1 << 12)
82#define ALL_MODES 0x1FFF
83
84struct pmx_mode spear300_nand_mode = {
85 .id = NAND_MODE,
86 .name = "nand mode",
87 .mask = 0x00,
88};
89
90struct pmx_mode spear300_nor_mode = {
91 .id = NOR_MODE,
92 .name = "nor mode",
93 .mask = 0x01,
94};
95
96struct pmx_mode spear300_photo_frame_mode = {
97 .id = PHOTO_FRAME_MODE,
98 .name = "photo frame mode",
99 .mask = 0x02,
100};
101
102struct pmx_mode spear300_lend_ip_phone_mode = {
103 .id = LEND_IP_PHONE_MODE,
104 .name = "lend ip phone mode",
105 .mask = 0x03,
106};
107
108struct pmx_mode spear300_hend_ip_phone_mode = {
109 .id = HEND_IP_PHONE_MODE,
110 .name = "hend ip phone mode",
111 .mask = 0x04,
112};
113
114struct pmx_mode spear300_lend_wifi_phone_mode = {
115 .id = LEND_WIFI_PHONE_MODE,
116 .name = "lend wifi phone mode",
117 .mask = 0x05,
118};
119
120struct pmx_mode spear300_hend_wifi_phone_mode = {
121 .id = HEND_WIFI_PHONE_MODE,
122 .name = "hend wifi phone mode",
123 .mask = 0x06,
124};
125
126struct pmx_mode spear300_ata_pabx_wi2s_mode = {
127 .id = ATA_PABX_WI2S_MODE,
128 .name = "ata pabx wi2s mode",
129 .mask = 0x07,
130};
131
132struct pmx_mode spear300_ata_pabx_i2s_mode = {
133 .id = ATA_PABX_I2S_MODE,
134 .name = "ata pabx i2s mode",
135 .mask = 0x08,
136};
137
138struct pmx_mode spear300_caml_lcdw_mode = {
139 .id = CAML_LCDW_MODE,
140 .name = "caml lcdw mode",
141 .mask = 0x0C,
142};
143
144struct pmx_mode spear300_camu_lcd_mode = {
145 .id = CAMU_LCD_MODE,
146 .name = "camu lcd mode",
147 .mask = 0x0D,
148};
149
150struct pmx_mode spear300_camu_wlcd_mode = {
151 .id = CAMU_WLCD_MODE,
152 .name = "camu wlcd mode",
153 .mask = 0x0E,
154};
155
156struct pmx_mode spear300_caml_lcd_mode = {
157 .id = CAML_LCD_MODE,
158 .name = "caml lcd mode",
159 .mask = 0x0F,
160};
161
162/* devices */
163static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
164 {
165 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
166 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
167 .mask = PMX_FIRDA_MASK,
168 },
169};
170
171struct pmx_dev spear300_pmx_fsmc_2_chips = {
172 .name = "fsmc_2_chips",
173 .modes = pmx_fsmc_2_chips_modes,
174 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
175 .enb_on_reset = 1,
176};
177
178static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
179 {
180 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
181 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
182 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
183 },
184};
185
186struct pmx_dev spear300_pmx_fsmc_4_chips = {
187 .name = "fsmc_4_chips",
188 .modes = pmx_fsmc_4_chips_modes,
189 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
190 .enb_on_reset = 1,
191};
192
193static struct pmx_dev_mode pmx_keyboard_modes[] = {
194 {
195 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
196 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
197 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
198 CAML_LCD_MODE,
199 .mask = 0x0,
200 },
201};
202
203struct pmx_dev spear300_pmx_keyboard = {
204 .name = "keyboard",
205 .modes = pmx_keyboard_modes,
206 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
207 .enb_on_reset = 1,
208};
209
210static struct pmx_dev_mode pmx_clcd_modes[] = {
211 {
212 .ids = PHOTO_FRAME_MODE,
213 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
214 }, {
215 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
216 CAMU_LCD_MODE | CAML_LCD_MODE,
217 .mask = PMX_TIMER_3_4_MASK,
218 },
219};
220
221struct pmx_dev spear300_pmx_clcd = {
222 .name = "clcd",
223 .modes = pmx_clcd_modes,
224 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
225 .enb_on_reset = 1,
226};
227
228static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
229 {
230 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
231 .mask = PMX_MII_MASK,
232 }, {
233 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
234 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
235 }, {
236 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
237 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
238 }, {
239 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
240 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
241 }, {
242 .ids = ATA_PABX_WI2S_MODE,
243 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
244 | PMX_UART0_MODEM_MASK,
245 },
246};
247
248struct pmx_dev spear300_pmx_telecom_gpio = {
249 .name = "telecom_gpio",
250 .modes = pmx_telecom_gpio_modes,
251 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
256 {
257 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
258 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
259 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
260 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
261 | CAMU_WLCD_MODE | CAML_LCD_MODE,
262 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
263 },
264};
265
266struct pmx_dev spear300_pmx_telecom_tdm = {
267 .name = "telecom_tdm",
268 .modes = pmx_telecom_tdm_modes,
269 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
270 .enb_on_reset = 1,
271};
272
273static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
274 {
275 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
276 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
277 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
278 CAML_LCDW_MODE | CAML_LCD_MODE,
279 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
280 },
281};
282
283struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
284 .name = "telecom_spi_cs_i2c_clk",
285 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
286 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
287 .enb_on_reset = 1,
288};
289
290static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
291 {
292 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
293 .mask = PMX_MII_MASK,
294 }, {
295 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
296 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
297 },
298};
299
300struct pmx_dev spear300_pmx_telecom_camera = {
301 .name = "telecom_camera",
302 .modes = pmx_telecom_camera_modes,
303 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
304 .enb_on_reset = 1,
305};
306
307static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
308 {
309 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
310 | CAMU_WLCD_MODE | CAML_LCD_MODE,
311 .mask = PMX_TIMER_1_2_MASK,
312 },
313};
314
315struct pmx_dev spear300_pmx_telecom_dac = {
316 .name = "telecom_dac",
317 .modes = pmx_telecom_dac_modes,
318 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
319 .enb_on_reset = 1,
320};
321
322static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
323 {
324 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
325 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
326 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
327 | CAMU_WLCD_MODE | CAML_LCD_MODE,
328 .mask = PMX_UART0_MODEM_MASK,
329 },
330};
331
332struct pmx_dev spear300_pmx_telecom_i2s = {
333 .name = "telecom_i2s",
334 .modes = pmx_telecom_i2s_modes,
335 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
336 .enb_on_reset = 1,
337};
338
339static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
340 {
341 .ids = NAND_MODE | NOR_MODE,
342 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
343 PMX_TIMER_3_4_MASK,
344 },
345};
346
347struct pmx_dev spear300_pmx_telecom_boot_pins = {
348 .name = "telecom_boot_pins",
349 .modes = pmx_telecom_boot_pins_modes,
350 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
355 {
356 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
357 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
358 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
359 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
360 ATA_PABX_I2S_MODE,
361 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
362 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
363 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
364 },
365};
366
367struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
368 .name = "telecom_sdhci_4bit",
369 .modes = pmx_telecom_sdhci_4bit_modes,
370 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
371 .enb_on_reset = 1,
372};
373
374static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
375 {
376 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
377 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
378 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
379 CAMU_WLCD_MODE | CAML_LCD_MODE,
380 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
381 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
382 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
383 },
384};
385
386struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
387 .name = "telecom_sdhci_8bit",
388 .modes = pmx_telecom_sdhci_8bit_modes,
389 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
390 .enb_on_reset = 1,
391};
392
393static struct pmx_dev_mode pmx_gpio1_modes[] = {
394 {
395 .ids = PHOTO_FRAME_MODE,
396 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
397 PMX_TIMER_3_4_MASK,
398 },
399};
400
401struct pmx_dev spear300_pmx_gpio1 = {
402 .name = "arm gpio1",
403 .modes = pmx_gpio1_modes,
404 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
405 .enb_on_reset = 1,
406};
407
408/* pmx driver structure */
409static struct pmx_driver pmx_driver = {
410 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
411 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
412};
413
414/* spear3xx shared irq */ 63/* spear3xx shared irq */
415static struct shirq_dev_config shirq_ras1_config[] = { 64static struct shirq_dev_config shirq_ras1_config[] = {
416 { 65 {
@@ -464,22 +113,6 @@ static struct spear_shirq shirq_ras1 = {
464 }, 113 },
465}; 114};
466 115
467/* padmux devices to enable */
468static struct pmx_dev *spear300_evb_pmx_devs[] = {
469 /* spear3xx specific devices */
470 &spear3xx_pmx_i2c,
471 &spear3xx_pmx_ssp_cs,
472 &spear3xx_pmx_ssp,
473 &spear3xx_pmx_mii,
474 &spear3xx_pmx_uart0,
475
476 /* spear300 specific devices */
477 &spear300_pmx_fsmc_2_chips,
478 &spear300_pmx_clcd,
479 &spear300_pmx_telecom_sdhci_4bit,
480 &spear300_pmx_gpio1,
481};
482
483/* DMAC platform data's slave info */ 116/* DMAC platform data's slave info */
484struct pl08x_channel_data spear300_dma_info[] = { 117struct pl08x_channel_data spear300_dma_info[] = {
485 { 118 {
@@ -678,7 +311,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
678 311
679static void __init spear300_dt_init(void) 312static void __init spear300_dt_init(void)
680{ 313{
681 int ret = -EINVAL; 314 int ret;
682 315
683 pl080_plat_data.slave_channels = spear300_dma_info; 316 pl080_plat_data.slave_channels = spear300_dma_info;
684 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); 317 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
@@ -693,26 +326,6 @@ static void __init spear300_dt_init(void)
693 if (ret) 326 if (ret)
694 pr_err("Error registering Shared IRQ\n"); 327 pr_err("Error registering Shared IRQ\n");
695 } 328 }
696
697 if (of_machine_is_compatible("st,spear300-evb")) {
698 /* pmx initialization */
699 pmx_driver.mode = &spear300_photo_frame_mode;
700 pmx_driver.devs = spear300_evb_pmx_devs;
701 pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs);
702
703 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
704 if (pmx_driver.base) {
705 ret = pmx_register(&pmx_driver);
706 if (ret)
707 pr_err("padmux: registration failed. err no: %d\n",
708 ret);
709 /* Free Mapping, device selection already done */
710 iounmap(pmx_driver.base);
711 }
712
713 if (ret)
714 pr_err("Initialization Failed");
715 }
716} 329}
717 330
718static const char * const spear300_dt_board_compat[] = { 331static const char * const spear300_dt_board_compat[] = {
@@ -724,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = {
724static void __init spear300_map_io(void) 337static void __init spear300_map_io(void)
725{ 338{
726 spear3xx_map_io(); 339 spear3xx_map_io();
727 spear300_clk_init();
728} 340}
729 341
730DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index b26e41566b50..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -82,128 +82,6 @@
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) 82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83 83
84 84
85/* pad multiplexing support */
86/* muxing registers */
87#define PAD_MUX_CONFIG_REG 0x08
88
89/* devices */
90static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
91 {
92 .ids = 0x00,
93 .mask = PMX_TIMER_3_4_MASK,
94 },
95};
96
97struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
98 .name = "emi_cs_0_1_4_5",
99 .modes = pmx_emi_cs_0_1_4_5_modes,
100 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
101 .enb_on_reset = 1,
102};
103
104static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
105 {
106 .ids = 0x00,
107 .mask = PMX_TIMER_1_2_MASK,
108 },
109};
110
111struct pmx_dev spear310_pmx_emi_cs_2_3 = {
112 .name = "emi_cs_2_3",
113 .modes = pmx_emi_cs_2_3_modes,
114 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
115 .enb_on_reset = 1,
116};
117
118static struct pmx_dev_mode pmx_uart1_modes[] = {
119 {
120 .ids = 0x00,
121 .mask = PMX_FIRDA_MASK,
122 },
123};
124
125struct pmx_dev spear310_pmx_uart1 = {
126 .name = "uart1",
127 .modes = pmx_uart1_modes,
128 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
129 .enb_on_reset = 1,
130};
131
132static struct pmx_dev_mode pmx_uart2_modes[] = {
133 {
134 .ids = 0x00,
135 .mask = PMX_TIMER_1_2_MASK,
136 },
137};
138
139struct pmx_dev spear310_pmx_uart2 = {
140 .name = "uart2",
141 .modes = pmx_uart2_modes,
142 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
143 .enb_on_reset = 1,
144};
145
146static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
147 {
148 .ids = 0x00,
149 .mask = PMX_UART0_MODEM_MASK,
150 },
151};
152
153struct pmx_dev spear310_pmx_uart3_4_5 = {
154 .name = "uart3_4_5",
155 .modes = pmx_uart3_4_5_modes,
156 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
157 .enb_on_reset = 1,
158};
159
160static struct pmx_dev_mode pmx_fsmc_modes[] = {
161 {
162 .ids = 0x00,
163 .mask = PMX_SSP_CS_MASK,
164 },
165};
166
167struct pmx_dev spear310_pmx_fsmc = {
168 .name = "fsmc",
169 .modes = pmx_fsmc_modes,
170 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
171 .enb_on_reset = 1,
172};
173
174static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
175 {
176 .ids = 0x00,
177 .mask = PMX_MII_MASK,
178 },
179};
180
181struct pmx_dev spear310_pmx_rs485_0_1 = {
182 .name = "rs485_0_1",
183 .modes = pmx_rs485_0_1_modes,
184 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
185 .enb_on_reset = 1,
186};
187
188static struct pmx_dev_mode pmx_tdm0_modes[] = {
189 {
190 .ids = 0x00,
191 .mask = PMX_MII_MASK,
192 },
193};
194
195struct pmx_dev spear310_pmx_tdm0 = {
196 .name = "tdm0",
197 .modes = pmx_tdm0_modes,
198 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
199 .enb_on_reset = 1,
200};
201
202/* pmx driver structure */
203static struct pmx_driver pmx_driver = {
204 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
205};
206
207/* spear3xx shared irq */ 85/* spear3xx shared irq */
208static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
209 { 87 {
@@ -320,30 +198,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
320 }, 198 },
321}; 199};
322 200
323/* padmux devices to enable */
324static struct pmx_dev *spear310_evb_pmx_devs[] = {
325 /* spear3xx specific devices */
326 &spear3xx_pmx_i2c,
327 &spear3xx_pmx_ssp,
328 &spear3xx_pmx_gpio_pin0,
329 &spear3xx_pmx_gpio_pin1,
330 &spear3xx_pmx_gpio_pin2,
331 &spear3xx_pmx_gpio_pin3,
332 &spear3xx_pmx_gpio_pin4,
333 &spear3xx_pmx_gpio_pin5,
334 &spear3xx_pmx_uart0,
335
336 /* spear310 specific devices */
337 &spear310_pmx_emi_cs_0_1_4_5,
338 &spear310_pmx_emi_cs_2_3,
339 &spear310_pmx_uart1,
340 &spear310_pmx_uart2,
341 &spear310_pmx_uart3_4_5,
342 &spear310_pmx_fsmc,
343 &spear310_pmx_rs485_0_1,
344 &spear310_pmx_tdm0,
345};
346
347/* DMAC platform data's slave info */ 201/* DMAC platform data's slave info */
348struct pl08x_channel_data spear310_dma_info[] = { 202struct pl08x_channel_data spear310_dma_info[] = {
349 { 203 {
@@ -578,7 +432,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
578static void __init spear310_dt_init(void) 432static void __init spear310_dt_init(void)
579{ 433{
580 void __iomem *base; 434 void __iomem *base;
581 int ret = 0; 435 int ret;
582 436
583 pl080_plat_data.slave_channels = spear310_dma_info; 437 pl080_plat_data.slave_channels = spear310_dma_info;
584 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); 438 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
@@ -613,19 +467,6 @@ static void __init spear310_dt_init(void)
613 if (ret) 467 if (ret)
614 pr_err("Error registering Shared IRQ 4\n"); 468 pr_err("Error registering Shared IRQ 4\n");
615 } 469 }
616
617 if (of_machine_is_compatible("st,spear310-evb")) {
618 /* pmx initialization */
619 pmx_driver.base = base;
620 pmx_driver.mode = NULL;
621 pmx_driver.devs = spear310_evb_pmx_devs;
622 pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs);
623
624 ret = pmx_register(&pmx_driver);
625 if (ret)
626 pr_err("padmux: registration failed. err no: %d\n",
627 ret);
628 }
629} 470}
630 471
631static const char * const spear310_dt_board_compat[] = { 472static const char * const spear310_dt_board_compat[] = {
@@ -637,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = {
637static void __init spear310_map_io(void) 478static void __init spear310_map_io(void)
638{ 479{
639 spear3xx_map_io(); 480 spear3xx_map_io();
640 spear310_clk_init();
641} 481}
642 482
643DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 2f5979b0c169..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -27,7 +27,6 @@
27#define SPEAR320_UART2_BASE UL(0xA4000000) 27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000) 28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000) 29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
31 30
32/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
33#define SPEAR320_INT_STS_MASK_REG 0x04 32#define SPEAR320_INT_STS_MASK_REG 0x04
@@ -83,373 +82,6 @@
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) 82#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) 83#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
85 84
86/* pad multiplexing support */
87/* muxing registers */
88#define PAD_MUX_CONFIG_REG 0x0C
89#define MODE_CONFIG_REG 0x10
90
91/* modes */
92#define AUTO_NET_SMII_MODE (1 << 0)
93#define AUTO_NET_MII_MODE (1 << 1)
94#define AUTO_EXP_MODE (1 << 2)
95#define SMALL_PRINTERS_MODE (1 << 3)
96#define ALL_MODES 0xF
97
98struct pmx_mode spear320_auto_net_smii_mode = {
99 .id = AUTO_NET_SMII_MODE,
100 .name = "Automation Networking SMII Mode",
101 .mask = 0x00,
102};
103
104struct pmx_mode spear320_auto_net_mii_mode = {
105 .id = AUTO_NET_MII_MODE,
106 .name = "Automation Networking MII Mode",
107 .mask = 0x01,
108};
109
110struct pmx_mode spear320_auto_exp_mode = {
111 .id = AUTO_EXP_MODE,
112 .name = "Automation Expanded Mode",
113 .mask = 0x02,
114};
115
116struct pmx_mode spear320_small_printers_mode = {
117 .id = SMALL_PRINTERS_MODE,
118 .name = "Small Printers Mode",
119 .mask = 0x03,
120};
121
122/* devices */
123static struct pmx_dev_mode pmx_clcd_modes[] = {
124 {
125 .ids = AUTO_NET_SMII_MODE,
126 .mask = 0x0,
127 },
128};
129
130struct pmx_dev spear320_pmx_clcd = {
131 .name = "clcd",
132 .modes = pmx_clcd_modes,
133 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_emi_modes[] = {
138 {
139 .ids = AUTO_EXP_MODE,
140 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
141 },
142};
143
144struct pmx_dev spear320_pmx_emi = {
145 .name = "emi",
146 .modes = pmx_emi_modes,
147 .mode_count = ARRAY_SIZE(pmx_emi_modes),
148 .enb_on_reset = 1,
149};
150
151static struct pmx_dev_mode pmx_fsmc_modes[] = {
152 {
153 .ids = ALL_MODES,
154 .mask = 0x0,
155 },
156};
157
158struct pmx_dev spear320_pmx_fsmc = {
159 .name = "fsmc",
160 .modes = pmx_fsmc_modes,
161 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
162 .enb_on_reset = 1,
163};
164
165static struct pmx_dev_mode pmx_spp_modes[] = {
166 {
167 .ids = SMALL_PRINTERS_MODE,
168 .mask = 0x0,
169 },
170};
171
172struct pmx_dev spear320_pmx_spp = {
173 .name = "spp",
174 .modes = pmx_spp_modes,
175 .mode_count = ARRAY_SIZE(pmx_spp_modes),
176 .enb_on_reset = 1,
177};
178
179static struct pmx_dev_mode pmx_sdhci_modes[] = {
180 {
181 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
182 SMALL_PRINTERS_MODE,
183 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
184 },
185};
186
187struct pmx_dev spear320_pmx_sdhci = {
188 .name = "sdhci",
189 .modes = pmx_sdhci_modes,
190 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
191 .enb_on_reset = 1,
192};
193
194static struct pmx_dev_mode pmx_i2s_modes[] = {
195 {
196 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
197 .mask = PMX_UART0_MODEM_MASK,
198 },
199};
200
201struct pmx_dev spear320_pmx_i2s = {
202 .name = "i2s",
203 .modes = pmx_i2s_modes,
204 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
205 .enb_on_reset = 1,
206};
207
208static struct pmx_dev_mode pmx_uart1_modes[] = {
209 {
210 .ids = ALL_MODES,
211 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
212 },
213};
214
215struct pmx_dev spear320_pmx_uart1 = {
216 .name = "uart1",
217 .modes = pmx_uart1_modes,
218 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
219 .enb_on_reset = 1,
220};
221
222static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
223 {
224 .ids = AUTO_EXP_MODE,
225 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
226 PMX_SSP_CS_MASK,
227 }, {
228 .ids = SMALL_PRINTERS_MODE,
229 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
230 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
231 },
232};
233
234struct pmx_dev spear320_pmx_uart1_modem = {
235 .name = "uart1_modem",
236 .modes = pmx_uart1_modem_modes,
237 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
238 .enb_on_reset = 1,
239};
240
241static struct pmx_dev_mode pmx_uart2_modes[] = {
242 {
243 .ids = ALL_MODES,
244 .mask = PMX_FIRDA_MASK,
245 },
246};
247
248struct pmx_dev spear320_pmx_uart2 = {
249 .name = "uart2",
250 .modes = pmx_uart2_modes,
251 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
252 .enb_on_reset = 1,
253};
254
255static struct pmx_dev_mode pmx_touchscreen_modes[] = {
256 {
257 .ids = AUTO_NET_SMII_MODE,
258 .mask = PMX_SSP_CS_MASK,
259 },
260};
261
262struct pmx_dev spear320_pmx_touchscreen = {
263 .name = "touchscreen",
264 .modes = pmx_touchscreen_modes,
265 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
266 .enb_on_reset = 1,
267};
268
269static struct pmx_dev_mode pmx_can_modes[] = {
270 {
271 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
272 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
273 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_can = {
278 .name = "can",
279 .modes = pmx_can_modes,
280 .mode_count = ARRAY_SIZE(pmx_can_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
285 {
286 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
287 .mask = PMX_SSP_CS_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_sdhci_led = {
292 .name = "sdhci_led",
293 .modes = pmx_sdhci_led_modes,
294 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_pwm0_modes[] = {
299 {
300 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
301 .mask = PMX_UART0_MODEM_MASK,
302 }, {
303 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
304 .mask = PMX_MII_MASK,
305 },
306};
307
308struct pmx_dev spear320_pmx_pwm0 = {
309 .name = "pwm0",
310 .modes = pmx_pwm0_modes,
311 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
312 .enb_on_reset = 1,
313};
314
315static struct pmx_dev_mode pmx_pwm1_modes[] = {
316 {
317 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
318 .mask = PMX_UART0_MODEM_MASK,
319 }, {
320 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
321 .mask = PMX_MII_MASK,
322 },
323};
324
325struct pmx_dev spear320_pmx_pwm1 = {
326 .name = "pwm1",
327 .modes = pmx_pwm1_modes,
328 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
329 .enb_on_reset = 1,
330};
331
332static struct pmx_dev_mode pmx_pwm2_modes[] = {
333 {
334 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
335 .mask = PMX_SSP_CS_MASK,
336 }, {
337 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
338 .mask = PMX_MII_MASK,
339 },
340};
341
342struct pmx_dev spear320_pmx_pwm2 = {
343 .name = "pwm2",
344 .modes = pmx_pwm2_modes,
345 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
346 .enb_on_reset = 1,
347};
348
349static struct pmx_dev_mode pmx_pwm3_modes[] = {
350 {
351 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
352 .mask = PMX_MII_MASK,
353 },
354};
355
356struct pmx_dev spear320_pmx_pwm3 = {
357 .name = "pwm3",
358 .modes = pmx_pwm3_modes,
359 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
360 .enb_on_reset = 1,
361};
362
363static struct pmx_dev_mode pmx_ssp1_modes[] = {
364 {
365 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
366 .mask = PMX_MII_MASK,
367 },
368};
369
370struct pmx_dev spear320_pmx_ssp1 = {
371 .name = "ssp1",
372 .modes = pmx_ssp1_modes,
373 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
374 .enb_on_reset = 1,
375};
376
377static struct pmx_dev_mode pmx_ssp2_modes[] = {
378 {
379 .ids = AUTO_NET_SMII_MODE,
380 .mask = PMX_MII_MASK,
381 },
382};
383
384struct pmx_dev spear320_pmx_ssp2 = {
385 .name = "ssp2",
386 .modes = pmx_ssp2_modes,
387 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
388 .enb_on_reset = 1,
389};
390
391static struct pmx_dev_mode pmx_mii1_modes[] = {
392 {
393 .ids = AUTO_NET_MII_MODE,
394 .mask = 0x0,
395 },
396};
397
398struct pmx_dev spear320_pmx_mii1 = {
399 .name = "mii1",
400 .modes = pmx_mii1_modes,
401 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
402 .enb_on_reset = 1,
403};
404
405static struct pmx_dev_mode pmx_smii0_modes[] = {
406 {
407 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
408 .mask = PMX_MII_MASK,
409 },
410};
411
412struct pmx_dev spear320_pmx_smii0 = {
413 .name = "smii0",
414 .modes = pmx_smii0_modes,
415 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
416 .enb_on_reset = 1,
417};
418
419static struct pmx_dev_mode pmx_smii1_modes[] = {
420 {
421 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
422 .mask = PMX_MII_MASK,
423 },
424};
425
426struct pmx_dev spear320_pmx_smii1 = {
427 .name = "smii1",
428 .modes = pmx_smii1_modes,
429 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
430 .enb_on_reset = 1,
431};
432
433static struct pmx_dev_mode pmx_i2c1_modes[] = {
434 {
435 .ids = AUTO_EXP_MODE,
436 .mask = 0x0,
437 },
438};
439
440struct pmx_dev spear320_pmx_i2c1 = {
441 .name = "i2c1",
442 .modes = pmx_i2c1_modes,
443 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
444 .enb_on_reset = 1,
445};
446
447/* pmx driver structure */
448static struct pmx_driver pmx_driver = {
449 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
450 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
451};
452
453/* spear3xx shared irq */ 85/* spear3xx shared irq */
454static struct shirq_dev_config shirq_ras1_config[] = { 86static struct shirq_dev_config shirq_ras1_config[] = {
455 { 87 {
@@ -574,27 +206,6 @@ static struct spear_shirq shirq_intrcomm_ras = {
574 }, 206 },
575}; 207};
576 208
577/* padmux devices to enable */
578static struct pmx_dev *spear320_evb_pmx_devs[] = {
579 /* spear3xx specific devices */
580 &spear3xx_pmx_i2c,
581 &spear3xx_pmx_ssp,
582 &spear3xx_pmx_mii,
583 &spear3xx_pmx_uart0,
584
585 /* spear320 specific devices */
586 &spear320_pmx_fsmc,
587 &spear320_pmx_sdhci,
588 &spear320_pmx_i2s,
589 &spear320_pmx_uart1,
590 &spear320_pmx_uart2,
591 &spear320_pmx_can,
592 &spear320_pmx_pwm0,
593 &spear320_pmx_pwm1,
594 &spear320_pmx_pwm2,
595 &spear320_pmx_mii1,
596};
597
598/* DMAC platform data's slave info */ 209/* DMAC platform data's slave info */
599struct pl08x_channel_data spear320_dma_info[] = { 210struct pl08x_channel_data spear320_dma_info[] = {
600 { 211 {
@@ -832,7 +443,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
832static void __init spear320_dt_init(void) 443static void __init spear320_dt_init(void)
833{ 444{
834 void __iomem *base; 445 void __iomem *base;
835 int ret = 0; 446 int ret;
836 447
837 pl080_plat_data.slave_channels = spear320_dma_info; 448 pl080_plat_data.slave_channels = spear320_dma_info;
838 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); 449 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
@@ -861,19 +472,6 @@ static void __init spear320_dt_init(void)
861 if (ret) 472 if (ret)
862 pr_err("Error registering Shared IRQ 4\n"); 473 pr_err("Error registering Shared IRQ 4\n");
863 } 474 }
864
865 if (of_machine_is_compatible("st,spear320-evb")) {
866 /* pmx initialization */
867 pmx_driver.base = base;
868 pmx_driver.mode = &spear320_auto_net_mii_mode;
869 pmx_driver.devs = spear320_evb_pmx_devs;
870 pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs);
871
872 ret = pmx_register(&pmx_driver);
873 if (ret)
874 pr_err("padmux: registration failed. err no: %d\n",
875 ret);
876 }
877} 475}
878 476
879static const char * const spear320_dt_board_compat[] = { 477static const char * const spear320_dt_board_compat[] = {
@@ -882,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = {
882 NULL, 480 NULL,
883}; 481};
884 482
483struct map_desc spear320_io_desc[] __initdata = {
484 {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
491
885static void __init spear320_map_io(void) 492static void __init spear320_map_io(void)
886{ 493{
494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
887 spear3xx_map_io(); 495 spear3xx_map_io();
888 spear320_clk_init();
889} 496}
890 497
891DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 25c6c67d5b07..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -23,431 +23,6 @@
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/spear.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */
27/* devices */
28static struct pmx_dev_mode pmx_firda_modes[] = {
29 {
30 .ids = 0xffffffff,
31 .mask = PMX_FIRDA_MASK,
32 },
33};
34
35struct pmx_dev spear3xx_pmx_firda = {
36 .name = "firda",
37 .modes = pmx_firda_modes,
38 .mode_count = ARRAY_SIZE(pmx_firda_modes),
39 .enb_on_reset = 0,
40};
41
42static struct pmx_dev_mode pmx_i2c_modes[] = {
43 {
44 .ids = 0xffffffff,
45 .mask = PMX_I2C_MASK,
46 },
47};
48
49struct pmx_dev spear3xx_pmx_i2c = {
50 .name = "i2c",
51 .modes = pmx_i2c_modes,
52 .mode_count = ARRAY_SIZE(pmx_i2c_modes),
53 .enb_on_reset = 0,
54};
55
56static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
57 {
58 .ids = 0xffffffff,
59 .mask = PMX_SSP_CS_MASK,
60 },
61};
62
63struct pmx_dev spear3xx_pmx_ssp_cs = {
64 .name = "ssp_chip_selects",
65 .modes = pmx_ssp_cs_modes,
66 .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
67 .enb_on_reset = 0,
68};
69
70static struct pmx_dev_mode pmx_ssp_modes[] = {
71 {
72 .ids = 0xffffffff,
73 .mask = PMX_SSP_MASK,
74 },
75};
76
77struct pmx_dev spear3xx_pmx_ssp = {
78 .name = "ssp",
79 .modes = pmx_ssp_modes,
80 .mode_count = ARRAY_SIZE(pmx_ssp_modes),
81 .enb_on_reset = 0,
82};
83
84static struct pmx_dev_mode pmx_mii_modes[] = {
85 {
86 .ids = 0xffffffff,
87 .mask = PMX_MII_MASK,
88 },
89};
90
91struct pmx_dev spear3xx_pmx_mii = {
92 .name = "mii",
93 .modes = pmx_mii_modes,
94 .mode_count = ARRAY_SIZE(pmx_mii_modes),
95 .enb_on_reset = 0,
96};
97
98static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
99 {
100 .ids = 0xffffffff,
101 .mask = PMX_GPIO_PIN0_MASK,
102 },
103};
104
105struct pmx_dev spear3xx_pmx_gpio_pin0 = {
106 .name = "gpio_pin0",
107 .modes = pmx_gpio_pin0_modes,
108 .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
109 .enb_on_reset = 0,
110};
111
112static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
113 {
114 .ids = 0xffffffff,
115 .mask = PMX_GPIO_PIN1_MASK,
116 },
117};
118
119struct pmx_dev spear3xx_pmx_gpio_pin1 = {
120 .name = "gpio_pin1",
121 .modes = pmx_gpio_pin1_modes,
122 .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
123 .enb_on_reset = 0,
124};
125
126static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
127 {
128 .ids = 0xffffffff,
129 .mask = PMX_GPIO_PIN2_MASK,
130 },
131};
132
133struct pmx_dev spear3xx_pmx_gpio_pin2 = {
134 .name = "gpio_pin2",
135 .modes = pmx_gpio_pin2_modes,
136 .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
137 .enb_on_reset = 0,
138};
139
140static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
141 {
142 .ids = 0xffffffff,
143 .mask = PMX_GPIO_PIN3_MASK,
144 },
145};
146
147struct pmx_dev spear3xx_pmx_gpio_pin3 = {
148 .name = "gpio_pin3",
149 .modes = pmx_gpio_pin3_modes,
150 .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
151 .enb_on_reset = 0,
152};
153
154static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
155 {
156 .ids = 0xffffffff,
157 .mask = PMX_GPIO_PIN4_MASK,
158 },
159};
160
161struct pmx_dev spear3xx_pmx_gpio_pin4 = {
162 .name = "gpio_pin4",
163 .modes = pmx_gpio_pin4_modes,
164 .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
165 .enb_on_reset = 0,
166};
167
168static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
169 {
170 .ids = 0xffffffff,
171 .mask = PMX_GPIO_PIN5_MASK,
172 },
173};
174
175struct pmx_dev spear3xx_pmx_gpio_pin5 = {
176 .name = "gpio_pin5",
177 .modes = pmx_gpio_pin5_modes,
178 .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
179 .enb_on_reset = 0,
180};
181
182static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
183 {
184 .ids = 0xffffffff,
185 .mask = PMX_UART0_MODEM_MASK,
186 },
187};
188
189struct pmx_dev spear3xx_pmx_uart0_modem = {
190 .name = "uart0_modem",
191 .modes = pmx_uart0_modem_modes,
192 .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
193 .enb_on_reset = 0,
194};
195
196static struct pmx_dev_mode pmx_uart0_modes[] = {
197 {
198 .ids = 0xffffffff,
199 .mask = PMX_UART0_MASK,
200 },
201};
202
203struct pmx_dev spear3xx_pmx_uart0 = {
204 .name = "uart0",
205 .modes = pmx_uart0_modes,
206 .mode_count = ARRAY_SIZE(pmx_uart0_modes),
207 .enb_on_reset = 0,
208};
209
210static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
211 {
212 .ids = 0xffffffff,
213 .mask = PMX_TIMER_3_4_MASK,
214 },
215};
216
217struct pmx_dev spear3xx_pmx_timer_3_4 = {
218 .name = "timer_3_4",
219 .modes = pmx_timer_3_4_modes,
220 .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
221 .enb_on_reset = 0,
222};
223
224static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
225 {
226 .ids = 0xffffffff,
227 .mask = PMX_TIMER_1_2_MASK,
228 },
229};
230
231struct pmx_dev spear3xx_pmx_timer_1_2 = {
232 .name = "timer_1_2",
233 .modes = pmx_timer_1_2_modes,
234 .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
235 .enb_on_reset = 0,
236};
237
238#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
239/* plgpios devices */
240static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
241 {
242 .ids = 0x00,
243 .mask = PMX_FIRDA_MASK,
244 },
245};
246
247struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
248 .name = "plgpio 0 and 1",
249 .modes = pmx_plgpio_0_1_modes,
250 .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
251 .enb_on_reset = 1,
252};
253
254static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
255 {
256 .ids = 0x00,
257 .mask = PMX_UART0_MASK,
258 },
259};
260
261struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
262 .name = "plgpio 2 and 3",
263 .modes = pmx_plgpio_2_3_modes,
264 .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
265 .enb_on_reset = 1,
266};
267
268static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
269 {
270 .ids = 0x00,
271 .mask = PMX_I2C_MASK,
272 },
273};
274
275struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
276 .name = "plgpio 4 and 5",
277 .modes = pmx_plgpio_4_5_modes,
278 .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
279 .enb_on_reset = 1,
280};
281
282static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
283 {
284 .ids = 0x00,
285 .mask = PMX_SSP_MASK,
286 },
287};
288
289struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
290 .name = "plgpio 6 to 9",
291 .modes = pmx_plgpio_6_9_modes,
292 .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
293 .enb_on_reset = 1,
294};
295
296static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
297 {
298 .ids = 0x00,
299 .mask = PMX_MII_MASK,
300 },
301};
302
303struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
304 .name = "plgpio 10 to 27",
305 .modes = pmx_plgpio_10_27_modes,
306 .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
307 .enb_on_reset = 1,
308};
309
310static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
311 {
312 .ids = 0x00,
313 .mask = PMX_GPIO_PIN0_MASK,
314 },
315};
316
317struct pmx_dev spear3xx_pmx_plgpio_28 = {
318 .name = "plgpio 28",
319 .modes = pmx_plgpio_28_modes,
320 .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
321 .enb_on_reset = 1,
322};
323
324static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
325 {
326 .ids = 0x00,
327 .mask = PMX_GPIO_PIN1_MASK,
328 },
329};
330
331struct pmx_dev spear3xx_pmx_plgpio_29 = {
332 .name = "plgpio 29",
333 .modes = pmx_plgpio_29_modes,
334 .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
335 .enb_on_reset = 1,
336};
337
338static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
339 {
340 .ids = 0x00,
341 .mask = PMX_GPIO_PIN2_MASK,
342 },
343};
344
345struct pmx_dev spear3xx_pmx_plgpio_30 = {
346 .name = "plgpio 30",
347 .modes = pmx_plgpio_30_modes,
348 .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
353 {
354 .ids = 0x00,
355 .mask = PMX_GPIO_PIN3_MASK,
356 },
357};
358
359struct pmx_dev spear3xx_pmx_plgpio_31 = {
360 .name = "plgpio 31",
361 .modes = pmx_plgpio_31_modes,
362 .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
363 .enb_on_reset = 1,
364};
365
366static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
367 {
368 .ids = 0x00,
369 .mask = PMX_GPIO_PIN4_MASK,
370 },
371};
372
373struct pmx_dev spear3xx_pmx_plgpio_32 = {
374 .name = "plgpio 32",
375 .modes = pmx_plgpio_32_modes,
376 .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
377 .enb_on_reset = 1,
378};
379
380static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
381 {
382 .ids = 0x00,
383 .mask = PMX_GPIO_PIN5_MASK,
384 },
385};
386
387struct pmx_dev spear3xx_pmx_plgpio_33 = {
388 .name = "plgpio 33",
389 .modes = pmx_plgpio_33_modes,
390 .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
391 .enb_on_reset = 1,
392};
393
394static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
395 {
396 .ids = 0x00,
397 .mask = PMX_SSP_CS_MASK,
398 },
399};
400
401struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
402 .name = "plgpio 34 to 36",
403 .modes = pmx_plgpio_34_36_modes,
404 .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
405 .enb_on_reset = 1,
406};
407
408static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
409 {
410 .ids = 0x00,
411 .mask = PMX_UART0_MODEM_MASK,
412 },
413};
414
415struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
416 .name = "plgpio 37 to 42",
417 .modes = pmx_plgpio_37_42_modes,
418 .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
419 .enb_on_reset = 1,
420};
421
422static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
423 {
424 .ids = 0x00,
425 .mask = PMX_TIMER_1_2_MASK,
426 },
427};
428
429struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
430 .name = "plgpio 43, 44, 47 and 48",
431 .modes = pmx_plgpio_43_44_47_48_modes,
432 .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
433 .enb_on_reset = 1,
434};
435
436static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
437 {
438 .ids = 0x00,
439 .mask = PMX_TIMER_3_4_MASK,
440 },
441};
442
443struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
444 .name = "plgpio 45, 46, 49 and 50",
445 .modes = pmx_plgpio_45_46_49_50_modes,
446 .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
447 .enb_on_reset = 1,
448};
449#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
450
451/* ssp device registration */ 26/* ssp device registration */
452struct pl022_ssp_controller pl022_plat_data = { 27struct pl022_ssp_controller pl022_plat_data = {
453 .bus_id = 0, 28 .bus_id = 0,
@@ -515,6 +90,8 @@ static void __init spear3xx_timer_init(void)
515 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
516 struct clk *gpt_clk, *pclk; 91 struct clk *gpt_clk, *pclk;
517 92
93 spear3xx_clk_init();
94
518 /* get the system timer clock */ 95 /* get the system timer clock */
519 gpt_clk = clk_get_sys("gpt0", NULL); 96 gpt_clk = clk_get_sys("gpt0", NULL);
520 if (IS_ERR(gpt_clk)) { 97 if (IS_ERR(gpt_clk)) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 17:59:47 -0500