17 files changed, 709 insertions, 482 deletions

diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 18febf92f20a..98bc7edc95a6 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -13,8 +13,8 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <mach/misc_regs.h>
 #include <plat/clock.h>
+#include <mach/misc_regs.h>
 
 /* root clks */
 /* 32 KHz oscillator clock */
@@ -39,18 +39,43 @@ static struct clk rtc_clk = {
 };
 
 /* clock derived from 24 MHz osc clk */
+/* pll masks structure */
+static struct pll_clk_masks pll1_masks = {
+        .mode_mask = PLL_MODE_MASK,
+        .mode_shift = PLL_MODE_SHIFT,
+        .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
+        .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
+        .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
+        .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
+        .div_p_mask = PLL_DIV_P_MASK,
+        .div_p_shift = PLL_DIV_P_SHIFT,
+        .div_n_mask = PLL_DIV_N_MASK,
+        .div_n_shift = PLL_DIV_N_SHIFT,
+};
+
 /* pll1 configuration structure */
 static struct pll_clk_config pll1_config = {
         .mode_reg = PLL1_CTR,
         .cfg_reg = PLL1_FRQ,
+        .masks = &pll1_masks,
+};
+
+/* pll rate configuration table, in ascending order of rates */
+struct pll_rate_tbl pll_rtbl[] = {
+        {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
+        {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
 };
 
 /* PLL1 clock */
 static struct clk pll1_clk = {
+        .flags = ENABLED_ON_INIT,
         .pclk = &osc_24m_clk,
         .en_reg = PLL1_CTR,
         .en_reg_bit = PLL_ENABLE,
-        .recalc = &pll1_clk_recalc,
+        .calc_rate = &pll_calc_rate,
+        .recalc = &pll_clk_recalc,
+        .set_rate = &pll_clk_set_rate,
+        .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
         .private_data = &pll1_config,
 };
 
@@ -76,36 +101,83 @@ static struct clk cpu_clk = {
         .recalc = &follow_parent,
 };
 
+/* ahb masks structure */
+static struct bus_clk_masks ahb_masks = {
+        .mask = PLL_HCLK_RATIO_MASK,
+        .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
 /* ahb configuration structure */
 static struct bus_clk_config ahb_config = {
         .reg = CORE_CLK_CFG,
-        .mask = PLL_HCLK_RATIO_MASK,
-        .shift = PLL_HCLK_RATIO_SHIFT,
+        .masks = &ahb_masks,
+};
+
+/* ahb rate configuration table, in ascending order of rates */
+struct bus_rate_tbl bus_rtbl[] = {
+        {.div = 3}, /* == parent divided by 4 */
+        {.div = 2}, /* == parent divided by 3 */
+        {.div = 1}, /* == parent divided by 2 */
+        {.div = 0}, /* == parent divided by 1 */
 };
 
 /* ahb clock */
 static struct clk ahb_clk = {
         .flags = ALWAYS_ENABLED,
         .pclk = &pll1_clk,
+        .calc_rate = &bus_calc_rate,
         .recalc = &bus_clk_recalc,
+        .set_rate = &bus_clk_set_rate,
+        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
         .private_data = &ahb_config,
 };
 
-/* uart configurations */
-static struct aux_clk_config uart_config = {
+/* auxiliary synthesizers masks */
+static struct aux_clk_masks aux_masks = {
+        .eq_sel_mask = AUX_EQ_SEL_MASK,
+        .eq_sel_shift = AUX_EQ_SEL_SHIFT,
+        .eq1_mask = AUX_EQ1_SEL,
+        .eq2_mask = AUX_EQ2_SEL,
+        .xscale_sel_mask = AUX_XSCALE_MASK,
+        .xscale_sel_shift = AUX_XSCALE_SHIFT,
+        .yscale_sel_mask = AUX_YSCALE_MASK,
+        .yscale_sel_shift = AUX_YSCALE_SHIFT,
+};
+
+/* uart synth configurations */
+static struct aux_clk_config uart_synth_config = {
         .synth_reg = UART_CLK_SYNT,
+        .masks = &aux_masks,
+};
+
+/* aux rate configuration table, in ascending order of rates */
+struct aux_rate_tbl aux_rtbl[] = {
+        /* For PLL1 = 332 MHz */
+        {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
+        {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
+        {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
+};
+
+/* uart synth clock */
+static struct clk uart_synth_clk = {
+        .en_reg = UART_CLK_SYNT,
+        .en_reg_bit = AUX_SYNT_ENB,
+        .pclk = &pll1_clk,
+        .calc_rate = &aux_calc_rate,
+        .recalc = &aux_clk_recalc,
+        .set_rate = &aux_clk_set_rate,
+        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+        .private_data = &uart_synth_config,
 };
 
 /* uart parents */
 static struct pclk_info uart_pclk_info[] = {
         {
-                .pclk = &pll1_clk,
-                .pclk_mask = AUX_CLK_PLL1_MASK,
-                .scalable = 1,
+                .pclk = &uart_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
         }, {
                 .pclk = &pll3_48m_clk,
-                .pclk_mask = AUX_CLK_PLL3_MASK,
-                .scalable = 0,
+                .pclk_val = AUX_CLK_PLL3_VAL,
         },
 };
 
@@ -123,25 +195,35 @@ static struct clk uart_clk = {
         .en_reg_bit = UART_CLK_ENB,
         .pclk_sel = &uart_pclk_sel,
         .pclk_sel_shift = UART_CLK_SHIFT,
-        .recalc = &aux_clk_recalc,
-        .private_data = &uart_config,
+        .recalc = &follow_parent,
 };
 
 /* firda configurations */
-static struct aux_clk_config firda_config = {
+static struct aux_clk_config firda_synth_config = {
         .synth_reg = FIRDA_CLK_SYNT,
+        .masks = &aux_masks,
+};
+
+/* firda synth clock */
+static struct clk firda_synth_clk = {
+        .en_reg = FIRDA_CLK_SYNT,
+        .en_reg_bit = AUX_SYNT_ENB,
+        .pclk = &pll1_clk,
+        .calc_rate = &aux_calc_rate,
+        .recalc = &aux_clk_recalc,
+        .set_rate = &aux_clk_set_rate,
+        .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
+        .private_data = &firda_synth_config,
 };
 
 /* firda parents */
 static struct pclk_info firda_pclk_info[] = {
         {
-                .pclk = &pll1_clk,
-                .pclk_mask = AUX_CLK_PLL1_MASK,
-                .scalable = 1,
+                .pclk = &firda_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
         }, {
                 .pclk = &pll3_48m_clk,
-                .pclk_mask = AUX_CLK_PLL3_MASK,
-                .scalable = 0,
+                .pclk_val = AUX_CLK_PLL3_VAL,
         },
 };
 
@@ -159,73 +241,155 @@ static struct clk firda_clk = {
         .en_reg_bit = FIRDA_CLK_ENB,
         .pclk_sel = &firda_pclk_sel,
         .pclk_sel_shift = FIRDA_CLK_SHIFT,
-        .recalc = &aux_clk_recalc,
-        .private_data = &firda_config,
+        .recalc = &follow_parent,
+};
+
+/* gpt synthesizer masks */
+static struct gpt_clk_masks gpt_masks = {
+        .mscale_sel_mask = GPT_MSCALE_MASK,
+        .mscale_sel_shift = GPT_MSCALE_SHIFT,
+        .nscale_sel_mask = GPT_NSCALE_MASK,
+        .nscale_sel_shift = GPT_NSCALE_SHIFT,
+};
+
+/* gpt rate configuration table, in ascending order of rates */
+struct gpt_rate_tbl gpt_rtbl[] = {
+        /* For pll1 = 332 MHz */
+        {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
+        {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
+        {.mscale = 1, .nscale = 0}, /* 83 MHz */
+};
+
+/* gpt0 synth clk config*/
+static struct gpt_clk_config gpt0_synth_config = {
+        .synth_reg = PRSC1_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt synth clock */
+static struct clk gpt0_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt0_synth_config,
 };
 
 /* gpt parents */
-static struct pclk_info gpt_pclk_info[] = {
+static struct pclk_info gpt0_pclk_info[] = {
         {
-                .pclk = &pll1_clk,
-                .pclk_mask = AUX_CLK_PLL1_MASK,
-                .scalable = 1,
+                .pclk = &gpt0_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
         }, {
                 .pclk = &pll3_48m_clk,
-                .pclk_mask = AUX_CLK_PLL3_MASK,
-                .scalable = 0,
+                .pclk_val = AUX_CLK_PLL3_VAL,
         },
 };
 
 /* gpt parent select structure */
-static struct pclk_sel gpt_pclk_sel = {
-        .pclk_info = gpt_pclk_info,
-        .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+static struct pclk_sel gpt0_pclk_sel = {
+        .pclk_info = gpt0_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
         .pclk_sel_reg = PERIP_CLK_CFG,
         .pclk_sel_mask = GPT_CLK_MASK,
 };
 
-/* gpt0 configurations */
-static struct aux_clk_config gpt0_config = {
-        .synth_reg = PRSC1_CLK_CFG,
-};
-
 /* gpt0 timer clock */
 static struct clk gpt0_clk = {
         .flags = ALWAYS_ENABLED,
-        .pclk_sel = &gpt_pclk_sel,
+        .pclk_sel = &gpt0_pclk_sel,
         .pclk_sel_shift = GPT0_CLK_SHIFT,
-        .recalc = &gpt_clk_recalc,
-        .private_data = &gpt0_config,
+        .recalc = &follow_parent,
 };
 
-/* gpt1 configurations */
-static struct aux_clk_config gpt1_config = {
+/* gpt1 synth clk configurations */
+static struct gpt_clk_config gpt1_synth_config = {
         .synth_reg = PRSC2_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt1 synth clock */
+static struct clk gpt1_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt1_synth_config,
+};
+
+static struct pclk_info gpt1_pclk_info[] = {
+        {
+                .pclk = &gpt1_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt1_pclk_sel = {
+        .pclk_info = gpt1_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = GPT_CLK_MASK,
 };
 
 /* gpt1 timer clock */
 static struct clk gpt1_clk = {
         .en_reg = PERIP1_CLK_ENB,
         .en_reg_bit = GPT1_CLK_ENB,
-        .pclk_sel = &gpt_pclk_sel,
+        .pclk_sel = &gpt1_pclk_sel,
         .pclk_sel_shift = GPT1_CLK_SHIFT,
-        .recalc = &gpt_clk_recalc,
-        .private_data = &gpt1_config,
+        .recalc = &follow_parent,
 };
 
-/* gpt2 configurations */
-static struct aux_clk_config gpt2_config = {
+/* gpt2 synth clk configurations */
+static struct gpt_clk_config gpt2_synth_config = {
         .synth_reg = PRSC3_CLK_CFG,
+        .masks = &gpt_masks,
+};
+
+/* gpt1 synth clock */
+static struct clk gpt2_synth_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll1_clk,
+        .calc_rate = &gpt_calc_rate,
+        .recalc = &gpt_clk_recalc,
+        .set_rate = &gpt_clk_set_rate,
+        .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
+        .private_data = &gpt2_synth_config,
+};
+
+static struct pclk_info gpt2_pclk_info[] = {
+        {
+                .pclk = &gpt2_synth_clk,
+                .pclk_val = AUX_CLK_PLL1_VAL,
+        }, {
+                .pclk = &pll3_48m_clk,
+                .pclk_val = AUX_CLK_PLL3_VAL,
+        },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt2_pclk_sel = {
+        .pclk_info = gpt2_pclk_info,
+        .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
+        .pclk_sel_reg = PERIP_CLK_CFG,
+        .pclk_sel_mask = GPT_CLK_MASK,
 };
 
 /* gpt2 timer clock */
 static struct clk gpt2_clk = {
         .en_reg = PERIP1_CLK_ENB,
         .en_reg_bit = GPT2_CLK_ENB,
-        .pclk_sel = &gpt_pclk_sel,
+        .pclk_sel = &gpt2_pclk_sel,
         .pclk_sel_shift = GPT2_CLK_SHIFT,
-        .recalc = &gpt_clk_recalc,
-        .private_data = &gpt2_config,
+        .recalc = &follow_parent,
 };
 
 /* clock derived from pll3 clk */
@@ -245,26 +409,27 @@ static struct clk usbd_clk = {
         .recalc = &follow_parent,
 };
 
-/* clcd clock */
-static struct clk clcd_clk = {
-        .flags = ALWAYS_ENABLED,
-        .pclk = &pll3_48m_clk,
-        .recalc = &follow_parent,
+/* clock derived from ahb clk */
+/* apb masks structure */
+static struct bus_clk_masks apb_masks = {
+        .mask = HCLK_PCLK_RATIO_MASK,
+        .shift = HCLK_PCLK_RATIO_SHIFT,
 };
 
-/* clock derived from ahb clk */
 /* apb configuration structure */
 static struct bus_clk_config apb_config = {
         .reg = CORE_CLK_CFG,
-        .mask = HCLK_PCLK_RATIO_MASK,
-        .shift = HCLK_PCLK_RATIO_SHIFT,
+        .masks = &apb_masks,
 };
 
 /* apb clock */
 static struct clk apb_clk = {
         .flags = ALWAYS_ENABLED,
         .pclk = &ahb_clk,
+        .calc_rate = &bus_calc_rate,
         .recalc = &bus_clk_recalc,
+        .set_rate = &bus_clk_set_rate,
+        .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
         .private_data = &apb_config,
 };
 
@@ -325,8 +490,17 @@ static struct clk adc_clk = {
         .recalc = &follow_parent,
 };
 
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* emi clock */
+static struct clk emi_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
 /* ssp clock */
-static struct clk ssp_clk = {
+static struct clk ssp0_clk = {
         .pclk = &apb_clk,
         .en_reg = PERIP1_CLK_ENB,
         .en_reg_bit = SSP_CLK_ENB,
@@ -343,14 +517,145 @@ static struct clk gpio_clk = {
 
 static struct clk dummy_apb_pclk;
 
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
+        defined(CONFIG_MACH_SPEAR320)
+/* fsmc clock */
+static struct clk fsmc_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* common clocks to spear310 and spear320 */
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* uart1 clock */
+static struct clk uart1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart2 clock */
+static struct clk uart2_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
+
+/* common clocks to spear300 and spear320 */
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+/* clcd clock */
+static struct clk clcd_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &pll3_48m_clk,
+        .recalc = &follow_parent,
+};
+
+/* sdhci clock */
+static struct clk sdhci_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+
+/* spear300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR300
+/* gpio1 clock */
+static struct clk gpio1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* keyboard clock */
+static struct clk kbd_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+#endif
+
+/* spear310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR310
+/* uart3 clock */
+static struct clk uart3_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart4 clock */
+static struct clk uart4_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* uart5 clock */
+static struct clk uart5_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
+/* spear320 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR320
+/* can0 clock */
+static struct clk can0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* can1 clock */
+static struct clk can1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* i2c1 clock */
+static struct clk i2c1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &ahb_clk,
+        .recalc = &follow_parent,
+};
+
+/* ssp1 clock */
+static struct clk ssp1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* ssp2 clock */
+static struct clk ssp2_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+
+/* pwm clock */
+static struct clk pwm_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &apb_clk,
+        .recalc = &follow_parent,
+};
+#endif
+
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
+        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
         /* root clks */
         { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
         { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
         /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc",              .clk = &rtc_clk},
+        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
         /* clock derived from 24 MHz osc clk */
         { .con_id = "pll1_clk",         .clk = &pll1_clk},
         { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
@@ -358,18 +663,22 @@ static struct clk_lookup spear_clk_lookups[] = {
         /* clock derived from pll1 clk */
         { .con_id = "cpu_clk",          .clk = &cpu_clk},
         { .con_id = "ahb_clk",          .clk = &ahb_clk},
+        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
+        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
+        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
+        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
+        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
         { .dev_id = "uart",             .clk = &uart_clk},
         { .dev_id = "firda",            .clk = &firda_clk},
         { .dev_id = "gpt0",             .clk = &gpt0_clk},
         { .dev_id = "gpt1",             .clk = &gpt1_clk},
         { .dev_id = "gpt2",             .clk = &gpt2_clk},
         /* clock derived from pll3 clk */
-        { .dev_id = "usbh",             .clk = &usbh_clk},
-        { .dev_id = "usbd",             .clk = &usbd_clk},
-        { .dev_id = "clcd",             .clk = &clcd_clk},
+        { .dev_id = "designware_udc",   .clk = &usbd_clk},
+        { .con_id = "usbh_clk",         .clk = &usbh_clk},
         /* clock derived from ahb clk */
         { .con_id = "apb_clk",          .clk = &apb_clk},
-        { .dev_id = "i2c",              .clk = &i2c_clk},
+        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
         { .dev_id = "dma",              .clk = &dma_clk},
         { .dev_id = "jpeg",             .clk = &jpeg_clk},
         { .dev_id = "gmac",             .clk = &gmac_clk},
@@ -377,8 +686,50 @@ static struct clk_lookup spear_clk_lookups[] = {
         { .dev_id = "c3",               .clk = &c3_clk},
         /* clock derived from apb clk */
         { .dev_id = "adc",              .clk = &adc_clk},
-        { .dev_id = "ssp",              .clk = &ssp_clk},
+        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
         { .dev_id = "gpio",             .clk = &gpio_clk},
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+        { .dev_id = "physmap-flash",    .clk = &emi_clk},
+#endif
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
+        defined(CONFIG_MACH_SPEAR320)
+        { .con_id = "fsmc",             .clk = &fsmc_clk},
+#endif
+
+/* common clocks to spear310 and spear320 */
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+        { .dev_id = "uart1",            .clk = &uart1_clk},
+        { .dev_id = "uart2",            .clk = &uart2_clk},
+#endif
+
+        /* common clock to spear300 and spear320 */
+#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
+        { .dev_id = "clcd",             .clk = &clcd_clk},
+        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
+
+        /* spear300 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR300
+        { .dev_id = "gpio1",            .clk = &gpio1_clk},
+        { .dev_id = "keyboard",         .clk = &kbd_clk},
+#endif
+
+        /* spear310 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR310
+        { .dev_id = "uart3",            .clk = &uart3_clk},
+        { .dev_id = "uart4",            .clk = &uart4_clk},
+        { .dev_id = "uart5",            .clk = &uart5_clk},
+
+#endif
+        /* spear320 machine specific clock structures */
+#ifdef CONFIG_MACH_SPEAR320
+        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
+        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
+        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
+        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
+        { .dev_id = "pwm",              .clk = &pwm_clk},
+#endif
 };
 
 void __init clk_init(void)
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
index 947625d6b48d..53da4224ba3d 100644
--- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -11,9 +11,8 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/hardware.h>
-#include <mach/spear.h>
 #include <asm/hardware/vic.h>
+#include <mach/hardware.h>
 
                 .macro  disable_fiq
                 .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index af7e02c909a3..8e30636909ef 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,11 +14,11 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
 #include <plat/padmux.h>
 
 /* spear3xx declarations */
@@ -33,14 +33,14 @@
 /* Add spear3xx family device structure declarations here */
 extern struct amba_device gpio_device;
 extern struct amba_device uart_device;
-extern struct sys_timer spear_sys_timer;
+extern struct sys_timer spear3xx_timer;
 
 /* Add spear3xx family function declarations here */
 void __init clk_init(void);
+void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
 void __init spear3xx_init_irq(void);
 void __init spear3xx_init(void);
-void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
 
 /* pad mux declarations */
 #define PMX_FIRDA_MASK          (1 << 14)
@@ -129,12 +129,10 @@ extern struct pmx_dev pmx_telecom_camera;
 extern struct pmx_dev pmx_telecom_dac;
 extern struct pmx_dev pmx_telecom_i2s;
 extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdio_4bit;
-extern struct pmx_dev pmx_telecom_sdio_8bit;
+extern struct pmx_dev pmx_telecom_sdhci_4bit;
+extern struct pmx_dev pmx_telecom_sdhci_8bit;
 extern struct pmx_dev pmx_gpio1;
 
-void spear300_pmx_init(void);
-
 /* Add spear300 machine function declarations here */
 void __init spear300_init(void);
 
@@ -154,8 +152,6 @@ extern struct pmx_dev pmx_fsmc;
 extern struct pmx_dev pmx_rs485_0_1;
 extern struct pmx_dev pmx_tdm0;
 
-void spear310_pmx_init(void);
-
 /* Add spear310 machine function declarations here */
 void __init spear310_init(void);
 
@@ -176,14 +172,14 @@ extern struct pmx_dev pmx_clcd;
 extern struct pmx_dev pmx_emi;
 extern struct pmx_dev pmx_fsmc;
 extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdio;
+extern struct pmx_dev pmx_sdhci;
 extern struct pmx_dev pmx_i2s;
 extern struct pmx_dev pmx_uart1;
 extern struct pmx_dev pmx_uart1_modem;
 extern struct pmx_dev pmx_uart2;
 extern struct pmx_dev pmx_touchscreen;
 extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdio_led;
+extern struct pmx_dev pmx_sdhci_led;
 extern struct pmx_dev pmx_pwm0;
 extern struct pmx_dev pmx_pwm1;
 extern struct pmx_dev pmx_pwm2;
@@ -195,8 +191,6 @@ extern struct pmx_dev pmx_smii0;
 extern struct pmx_dev pmx_smii1;
 extern struct pmx_dev pmx_i2c1;
 
-void spear320_pmx_init(void);
-
 /* Add spear320 machine function declarations here */
 void __init spear320_init(void);
 
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4a86e6a3c444..4660c0d8ec0d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -14,6 +14,9 @@
 #ifndef __MACH_HARDWARE_H
 #define __MACH_HARDWARE_H
 
+#include <plat/hardware.h>
+#include <mach/spear.h>
+
 /* Vitual to physical translation of statically mapped space */
 #define IO_ADDRESS(x)           (x | 0xF0000000)
 
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 7f940b818473..a1a7f481866d 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -69,7 +69,7 @@
 #define IRQ_CLCD                                IRQ_GEN_RAS_3
 
 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDIO                                IRQ_INTRCOMM_RAS_ARM
+#define IRQ_SDHCI                               IRQ_INTRCOMM_RAS_ARM
 
 /* GPIO pins virtual irqs */
 #define SPEAR_GPIO_INT_BASE                     (VIRQ_START + 9)
@@ -115,7 +115,7 @@
 #define VIRQ_SPP                                (VIRQ_START + 2)
 
 /* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDIO                                IRQ_GEN_RAS_2
+#define IRQ_SDHCI                               IRQ_GEN_RAS_2
 
 /* IRQs sharing IRQ_GEN_RAS_3 */
 #define VIRQ_PLGPIO                             (VIRQ_START + 3)
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 38d767a1aba0..5bd8cd8d4852 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,16 +14,16 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
-#define MISC_BASE               VA_SPEAR3XX_ICM3_MISC_REG_BASE
+#define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
 
-#define SOC_CFG_CTR             ((unsigned int *)(MISC_BASE + 0x000))
-#define DIAG_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x004))
-#define PLL1_CTR                ((unsigned int *)(MISC_BASE + 0x008))
-#define PLL1_FRQ                ((unsigned int *)(MISC_BASE + 0x00C))
-#define PLL1_MOD                ((unsigned int *)(MISC_BASE + 0x010))
-#define PLL2_CTR                ((unsigned int *)(MISC_BASE + 0x014))
+#define SOC_CFG_CTR             (MISC_BASE + 0x000)
+#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
 /* PLL_CTR register masks */
 #define PLL_ENABLE              2
 #define PLL_MODE_SHIFT          4
@@ -33,7 +33,7 @@
 #define PLL_MODE_DITH_DSB       2
 #define PLL_MODE_DITH_SSB       3
 
-#define PLL2_FRQ                ((unsigned int *)(MISC_BASE + 0x018))
+#define PLL2_FRQ                (MISC_BASE + 0x018)
 /* PLL FRQ register masks */
 #define PLL_DIV_N_SHIFT         0
 #define PLL_DIV_N_MASK          0xFF
@@ -44,16 +44,16 @@
 #define PLL_DITH_FDBK_M_SHIFT   16
 #define PLL_DITH_FDBK_M_MASK    0xFFFF
 
-#define PLL2_MOD                ((unsigned int *)(MISC_BASE + 0x01C))
-#define PLL_CLK_CFG             ((unsigned int *)(MISC_BASE + 0x020))
-#define CORE_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x024))
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
 /* CORE CLK CFG register masks */
 #define PLL_HCLK_RATIO_SHIFT    10
 #define PLL_HCLK_RATIO_MASK     0x3
 #define HCLK_PCLK_RATIO_SHIFT   8
 #define HCLK_PCLK_RATIO_MASK    0x3
 
-#define PERIP_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x028))
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
 /* PERIP_CLK_CFG register masks */
 #define UART_CLK_SHIFT          4
 #define UART_CLK_MASK           0x1
@@ -63,10 +63,10 @@
 #define GPT1_CLK_SHIFT          11
 #define GPT2_CLK_SHIFT          12
 #define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_MASK       0
-#define AUX_CLK_PLL1_MASK       1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
 
-#define PERIP1_CLK_ENB          ((unsigned int *)(MISC_BASE + 0x02C))
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
 /* PERIP1_CLK_ENB register masks */
 #define UART_CLK_ENB            3
 #define SSP_CLK_ENB             5
@@ -85,34 +85,35 @@
 #define USBH_CLK_ENB            25
 #define C3_CLK_ENB              31
 
-#define SOC_CORE_ID             ((unsigned int *)(MISC_BASE + 0x030))
-#define RAS_CLK_ENB             ((unsigned int *)(MISC_BASE + 0x034))
-#define PERIP1_SOF_RST          ((unsigned int *)(MISC_BASE + 0x038))
+#define SOC_CORE_ID             (MISC_BASE + 0x030)
+#define RAS_CLK_ENB             (MISC_BASE + 0x034)
+#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
 /* PERIP1_SOF_RST register masks */
 #define JPEG_SOF_RST            8
 
-#define SOC_USER_ID             ((unsigned int *)(MISC_BASE + 0x03C))
-#define RAS_SOF_RST             ((unsigned int *)(MISC_BASE + 0x040))
-#define PRSC1_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x044))
-#define PRSC2_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x048))
-#define PRSC3_CLK_CFG           ((unsigned int *)(MISC_BASE + 0x04C))
+#define SOC_USER_ID             (MISC_BASE + 0x03C)
+#define RAS_SOF_RST             (MISC_BASE + 0x040)
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
 /* gpt synthesizer register masks */
 #define GPT_MSCALE_SHIFT        0
 #define GPT_MSCALE_MASK         0xFFF
 #define GPT_NSCALE_SHIFT        12
 #define GPT_NSCALE_MASK         0xF
 
-#define AMEM_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x050))
-#define EXPI_CLK_CFG            ((unsigned int *)(MISC_BASE + 0x054))
-#define CLCD_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x05C))
-#define FIRDA_CLK_SYNT          ((unsigned int *)(MISC_BASE + 0x060))
-#define UART_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x064))
-#define GMAC_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x068))
-#define RAS1_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x06C))
-#define RAS2_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x070))
-#define RAS3_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x074))
-#define RAS4_CLK_SYNT           ((unsigned int *)(MISC_BASE + 0x078))
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
 /* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
 #define AUX_EQ_SEL_SHIFT        30
 #define AUX_EQ_SEL_MASK         1
 #define AUX_EQ1_SEL             0
@@ -122,42 +123,42 @@
 #define AUX_YSCALE_SHIFT        0
 #define AUX_YSCALE_MASK         0xFFF
 
-#define ICM1_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x07C))
-#define ICM2_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x080))
-#define ICM3_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x084))
-#define ICM4_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x088))
-#define ICM5_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x08C))
-#define ICM6_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x090))
-#define ICM7_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x094))
-#define ICM8_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x098))
-#define ICM9_ARB_CFG            ((unsigned int *)(MISC_BASE + 0x09C))
-#define DMA_CHN_CFG             ((unsigned int *)(MISC_BASE + 0x0A0))
-#define USB2_PHY_CFG            ((unsigned int *)(MISC_BASE + 0x0A4))
-#define GMAC_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x0A8))
-#define EXPI_CFG_CTR            ((unsigned int *)(MISC_BASE + 0x0AC))
-#define PRC1_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C0))
-#define PRC2_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C4))
-#define PRC3_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0C8))
-#define PRC4_LOCK_CTR           ((unsigned int *)(MISC_BASE + 0x0CC))
-#define PRC1_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D0))
-#define PRC2_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D4))
-#define PRC3_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0D8))
-#define PRC4_IRQ_CTR            ((unsigned int *)(MISC_BASE + 0x0DC))
-#define PWRDOWN_CFG_CTR         ((unsigned int *)(MISC_BASE + 0x0E0))
-#define COMPSSTL_1V8_CFG        ((unsigned int *)(MISC_BASE + 0x0E4))
-#define COMPSSTL_2V5_CFG        ((unsigned int *)(MISC_BASE + 0x0E8))
-#define COMPCOR_3V3_CFG         ((unsigned int *)(MISC_BASE + 0x0EC))
-#define SSTLPAD_CFG_CTR         ((unsigned int *)(MISC_BASE + 0x0F0))
-#define BIST1_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0F4))
-#define BIST2_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0F8))
-#define BIST3_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x0FC))
-#define BIST4_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x100))
-#define BIST5_CFG_CTR           ((unsigned int *)(MISC_BASE + 0x104))
-#define BIST1_STS_RES           ((unsigned int *)(MISC_BASE + 0x108))
-#define BIST2_STS_RES           ((unsigned int *)(MISC_BASE + 0x10C))
-#define BIST3_STS_RES           ((unsigned int *)(MISC_BASE + 0x110))
-#define BIST4_STS_RES           ((unsigned int *)(MISC_BASE + 0x114))
-#define BIST5_STS_RES           ((unsigned int *)(MISC_BASE + 0x118))
-#define SYSERR_CFG_CTR          ((unsigned int *)(MISC_BASE + 0x11C))
+#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
+#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
+#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
+#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
+#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
+#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
+#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
+#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
+#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
+#define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
+#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
+#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
+#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
+#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
+#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
+#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
+#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
+#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
+#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
+#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
+#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
+#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
+#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
+#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
+#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
+#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
+#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
+#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
+#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
+#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
+#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
+#define BIST1_STS_RES           (MISC_BASE + 0x108)
+#define BIST2_STS_RES           (MISC_BASE + 0x10C)
+#define BIST3_STS_RES           (MISC_BASE + 0x110)
+#define BIST4_STS_RES           (MISC_BASE + 0x114)
+#define BIST5_STS_RES           (MISC_BASE + 0x118)
+#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index dcca8568a486..63fd98356919 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -14,124 +14,61 @@
 #ifndef __MACH_SPEAR3XX_H
 #define __MACH_SPEAR3XX_H
 
-#include <mach/hardware.h>
+#include <asm/memory.h>
 #include <mach/spear300.h>
 #include <mach/spear310.h>
 #include <mach/spear320.h>
 
-#define SPEAR3XX_ML_SDRAM_BASE          0x00000000
-#define SPEAR3XX_ML_SDRAM_SIZE          0x40000000
+#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
 
-#define SPEAR3XX_ICM9_BASE              0xC0000000
-#define SPEAR3XX_ICM9_SIZE              0x10000000
+#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE            0xD0000000
-#define SPEAR3XX_ICM1_2_SIZE            0x10000000
-
-#define SPEAR3XX_ICM1_UART_BASE         0xD0000000
+#define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
 #define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_UART_SIZE         0x00080000
-
-#define SPEAR3XX_ICM1_ADC_BASE          0xD0080000
-#define SPEAR3XX_ICM1_ADC_SIZE          0x00080000
-
-#define SPEAR3XX_ICM1_SSP_BASE          0xD0100000
-#define SPEAR3XX_ICM1_SSP_SIZE          0x00080000
-
-#define SPEAR3XX_ICM1_I2C_BASE          0xD0180000
-#define SPEAR3XX_ICM1_I2C_SIZE          0x00080000
-
-#define SPEAR3XX_ICM1_JPEG_BASE         0xD0800000
-#define SPEAR3XX_ICM1_JPEG_SIZE         0x00800000
-
-#define SPEAR3XX_ICM1_IRDA_BASE         0xD1000000
-#define SPEAR3XX_ICM1_IRDA_SIZE         0x00080000
-
-#define SPEAR3XX_ICM1_SRAM_BASE         0xD2800000
-#define SPEAR3XX_ICM1_SRAM_SIZE         0x05800000
+#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
+#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
+#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
+#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
+#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
+#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
 
 /* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     0xD8800000
-#define SPEAR3XX_ICM2_HWACCEL0_SIZE     0x00800000
-
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     0xD9000000
-#define SPEAR3XX_ICM2_HWACCEL1_SIZE     0x00800000
+#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
+#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
 
 /* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              0xE0000000
-#define SPEAR3XX_ICM4_SIZE              0x08000000
-
-#define SPEAR3XX_ICM4_MII_BASE          0xE0800000
-#define SPEAR3XX_ICM4_MII_SIZE          0x00800000
-
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    0xE1000000
-#define SPEAR3XX_ICM4_USBD_FIFO_SIZE    0x00100000
-
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     0xE1100000
-#define SPEAR3XX_ICM4_USBD_CSR_SIZE     0x00100000
-
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    0xE1200000
-#define SPEAR3XX_ICM4_USBD_PLDT_SIZE    0x00100000
-
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  0xE1800000
-#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE  0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    0xE1900000
-#define SPEAR3XX_ICM4_USB_OHCI0_SIZE    0x00100000
-
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    0xE2100000
-#define SPEAR3XX_ICM4_USB_OHCI1_SIZE    0x00100000
-
-#define SPEAR3XX_ICM4_USB_ARB_BASE      0xE2800000
-#define SPEAR3XX_ICM4_USB_ARB_SIZE      0x00010000
+#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
+#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
+#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
+#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE        0xF0000000
-#define SPEAR3XX_ICM3_ML1_2_SIZE        0x0F000000
-
-#define SPEAR3XX_ML1_TMR_BASE           0xF0000000
-#define SPEAR3XX_ML1_TMR_SIZE           0x00100000
-
-#define SPEAR3XX_ML1_VIC_BASE           0xF1100000
+#define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
+#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
+#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
 #define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
-#define SPEAR3XX_ML1_VIC_SIZE           0x00100000
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         0xF8000000
-#define SPEAR3XX_ICM3_SMEM_SIZE         0x04000000
-
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE     0xFC000000
-#define SPEAR3XX_ICM3_SMI_CTRL_SIZE     0x00200000
-
-#define SPEAR3XX_ICM3_DMA_BASE          0xFC400000
-#define SPEAR3XX_ICM3_DMA_SIZE          0x00200000
-
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   0xFC600000
-#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE   0x00200000
-
-#define SPEAR3XX_ICM3_TMR0_BASE         0xFC800000
-#define SPEAR3XX_ICM3_TMR0_SIZE         0x00080000
-
-#define SPEAR3XX_ICM3_WDT_BASE          0xFC880000
-#define SPEAR3XX_ICM3_WDT_SIZE          0x00080000
-
-#define SPEAR3XX_ICM3_RTC_BASE          0xFC900000
-#define SPEAR3XX_ICM3_RTC_SIZE          0x00080000
-
-#define SPEAR3XX_ICM3_GPIO_BASE         0xFC980000
-#define SPEAR3XX_ICM3_GPIO_SIZE         0x00080000
-
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE     0xFCA00000
+#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
+#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
+#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
+#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
+#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_SYS_CTRL_SIZE     0x00080000
-
-#define SPEAR3XX_ICM3_MISC_REG_BASE     0xFCA80000
+#define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_SIZE     0x00080000
-
-#define SPEAR3XX_ICM3_TMR1_BASE         0xFCB00000
-#define SPEAR3XX_ICM3_TMR1_SIZE         0x00080000
+#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index ccaa76522ee2..c723515f8853 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -17,11 +17,9 @@
 #define __MACH_SPEAR300_H
 
 /* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           0x50000000
-#define SPEAR300_TELECOM_SIZE           0x10000000
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
 
 /* Interrupt registers offsets and masks */
-#define SPEAR300_TELECOM_REG_SIZE       0x00010000
 #define INT_ENB_MASK_REG                0x54
 #define INT_STS_MASK_REG                0x58
 #define IT_PERS_S_IRQ_MASK              (1 << 0)
@@ -36,47 +34,20 @@
 
 #define SHIRQ_RAS1_MASK                 0x1FF
 
-#define SPEAR300_CLCD_BASE              0x60000000
-#define SPEAR300_CLCD_SIZE              0x10000000
-
-#define SPEAR300_SDIO_BASE              0x70000000
-#define SPEAR300_SDIO_SIZE              0x10000000
-
-#define SPEAR300_NAND_0_BASE            0x80000000
-#define SPEAR300_NAND_0_SIZE            0x04000000
-
-#define SPEAR300_NAND_1_BASE            0x84000000
-#define SPEAR300_NAND_1_SIZE            0x04000000
-
-#define SPEAR300_NAND_2_BASE            0x88000000
-#define SPEAR300_NAND_2_SIZE            0x04000000
-
-#define SPEAR300_NAND_3_BASE            0x8c000000
-#define SPEAR300_NAND_3_SIZE            0x04000000
-
-#define SPEAR300_NOR_0_BASE             0x90000000
-#define SPEAR300_NOR_0_SIZE             0x01000000
-
-#define SPEAR300_NOR_1_BASE             0x91000000
-#define SPEAR300_NOR_1_SIZE             0x01000000
-
-#define SPEAR300_NOR_2_BASE             0x92000000
-#define SPEAR300_NOR_2_SIZE             0x01000000
-
-#define SPEAR300_NOR_3_BASE             0x93000000
-#define SPEAR300_NOR_3_SIZE             0x01000000
-
-#define SPEAR300_FSMC_BASE              0x94000000
-#define SPEAR300_FSMC_SIZE              0x05000000
-
-#define SPEAR300_SOC_CONFIG_BASE        0x99000000
-#define SPEAR300_SOC_CONFIG_SIZE        0x00000008
-
-#define SPEAR300_KEYBOARD_BASE          0xA0000000
-#define SPEAR300_KEYBOARD_SIZE          0x09000000
-
-#define SPEAR300_GPIO_BASE              0xA9000000
-#define SPEAR300_GPIO_SIZE              0x07000000
+#define SPEAR300_CLCD_BASE              UL(0x60000000)
+#define SPEAR300_SDHCI_BASE             UL(0x70000000)
+#define SPEAR300_NAND_0_BASE            UL(0x80000000)
+#define SPEAR300_NAND_1_BASE            UL(0x84000000)
+#define SPEAR300_NAND_2_BASE            UL(0x88000000)
+#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
+#define SPEAR300_NOR_0_BASE             UL(0x90000000)
+#define SPEAR300_NOR_1_BASE             UL(0x91000000)
+#define SPEAR300_NOR_2_BASE             UL(0x92000000)
+#define SPEAR300_NOR_3_BASE             UL(0x93000000)
+#define SPEAR300_FSMC_BASE              UL(0x94000000)
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
+#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
+#define SPEAR300_GPIO_BASE              UL(0xA9000000)
 
 #endif /* __MACH_SPEAR300_H */
 
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index b27bb8af3309..1e853479b8cd 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,30 +16,18 @@
 #ifndef __MACH_SPEAR310_H
 #define __MACH_SPEAR310_H
 
-#define SPEAR310_NAND_BASE              0x40000000
-#define SPEAR310_NAND_SIZE              0x04000000
+#define SPEAR310_NAND_BASE              UL(0x40000000)
+#define SPEAR310_FSMC_BASE              UL(0x44000000)
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
+#define SPEAR310_HDLC_BASE              UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
 
-#define SPEAR310_FSMC_BASE              0x44000000
-#define SPEAR310_FSMC_SIZE              0x01000000
-
-#define SPEAR310_UART1_BASE             0xB2000000
-#define SPEAR310_UART2_BASE             0xB2080000
-#define SPEAR310_UART3_BASE             0xB2100000
-#define SPEAR310_UART4_BASE             0xB2180000
-#define SPEAR310_UART5_BASE             0xB2200000
-#define SPEAR310_UART_SIZE              0x00080000
-
-#define SPEAR310_HDLC_BASE              0xB2800000
-#define SPEAR310_HDLC_SIZE              0x00800000
-
-#define SPEAR310_RS485_0_BASE           0xB3000000
-#define SPEAR310_RS485_0_SIZE           0x00800000
-
-#define SPEAR310_RS485_1_BASE           0xB3800000
-#define SPEAR310_RS485_1_SIZE           0x00800000
-
-#define SPEAR310_SOC_CONFIG_BASE        0xB4000000
-#define SPEAR310_SOC_CONFIG_SIZE        0x00000070
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
 #define SMII0_IRQ_MASK                  (1 << 0)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958cd..940f0d85d959 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,54 +16,25 @@
 #ifndef __MACH_SPEAR320_H
 #define __MACH_SPEAR320_H
 
-#define SPEAR320_EMI_CTRL_BASE          0x40000000
-#define SPEAR320_EMI_CTRL_SIZE          0x08000000
+#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
+#define SPEAR320_FSMC_BASE              UL(0x4C000000)
+#define SPEAR320_NAND_BASE              UL(0x50000000)
+#define SPEAR320_I2S_BASE               UL(0x60000000)
+#define SPEAR320_SDHCI_BASE             UL(0x70000000)
+#define SPEAR320_CLCD_BASE              UL(0x90000000)
+#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
+#define SPEAR320_CAN0_BASE              UL(0xA1000000)
+#define SPEAR320_CAN1_BASE              UL(0xA2000000)
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+#define SPEAR320_I2C_BASE               UL(0xA7000000)
+#define SPEAR320_PWM_BASE               UL(0xA8000000)
+#define SPEAR320_SMII0_BASE             UL(0xAA000000)
+#define SPEAR320_SMII1_BASE             UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
 
-#define SPEAR320_FSMC_BASE              0x4C000000
-#define SPEAR320_FSMC_SIZE              0x01000000
-
-#define SPEAR320_I2S_BASE               0x60000000
-#define SPEAR320_I2S_SIZE               0x10000000
-
-#define SPEAR320_SDIO_BASE              0x70000000
-#define SPEAR320_SDIO_SIZE              0x10000000
-
-#define SPEAR320_CLCD_BASE              0x90000000
-#define SPEAR320_CLCD_SIZE              0x10000000
-
-#define SPEAR320_PAR_PORT_BASE          0xA0000000
-#define SPEAR320_PAR_PORT_SIZE          0x01000000
-
-#define SPEAR320_CAN0_BASE              0xA1000000
-#define SPEAR320_CAN0_SIZE              0x01000000
-
-#define SPEAR320_CAN1_BASE              0xA2000000
-#define SPEAR320_CAN1_SIZE              0x01000000
-
-#define SPEAR320_UART1_BASE             0xA3000000
-#define SPEAR320_UART2_BASE             0xA4000000
-#define SPEAR320_UART_SIZE              0x01000000
-
-#define SPEAR320_SSP0_BASE              0xA5000000
-#define SPEAR320_SSP0_SIZE              0x01000000
-
-#define SPEAR320_SSP1_BASE              0xA6000000
-#define SPEAR320_SSP1_SIZE              0x01000000
-
-#define SPEAR320_I2C_BASE               0xA7000000
-#define SPEAR320_I2C_SIZE               0x01000000
-
-#define SPEAR320_PWM_BASE               0xA8000000
-#define SPEAR320_PWM_SIZE               0x01000000
-
-#define SPEAR320_SMII0_BASE             0xAA000000
-#define SPEAR320_SMII0_SIZE             0x01000000
-
-#define SPEAR320_SMII1_BASE             0xAB000000
-#define SPEAR320_SMII1_SIZE             0x01000000
-
-#define SPEAR320_SOC_CONFIG_BASE        0xB4000000
-#define SPEAR320_SOC_CONFIG_SIZE        0x00000070
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
 #define INT_CLR_MASK_REG                0x04
@@ -74,7 +45,7 @@
 #define EMI_IRQ_MASK                    (1 << 7)
 #define CLCD_IRQ_MASK                   (1 << 8)
 #define SPP_IRQ_MASK                    (1 << 9)
-#define SDIO_IRQ_MASK                   (1 << 10)
+#define SDHCI_IRQ_MASK                  (1 << 10)
 #define CAN_U_IRQ_MASK                  (1 << 11)
 #define CAN_L_IRQ_MASK                  (1 << 12)
 #define UART1_IRQ_MASK                  (1 << 13)
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 5aa2d54ebfaa..2697e65adf86 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -15,9 +15,9 @@
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
 #include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/spear.h>
 #include <plat/shirq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -310,7 +310,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
         .enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
         {
                 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
                         HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
         },
 };
 
-struct pmx_dev pmx_telecom_sdio_4bit = {
-        .name = "telecom_sdio_4bit",
-        .modes = pmx_telecom_sdio_4bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
+struct pmx_dev pmx_telecom_sdhci_4bit = {
+        .name = "telecom_sdhci_4bit",
+        .modes = pmx_telecom_sdhci_4bit_modes,
+        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
         .enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
         {
                 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
                         HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -342,10 +342,10 @@ struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
         },
 };
 
-struct pmx_dev pmx_telecom_sdio_8bit = {
-        .name = "telecom_sdio_8bit",
-        .modes = pmx_telecom_sdio_8bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
+struct pmx_dev pmx_telecom_sdhci_8bit = {
+        .name = "telecom_sdhci_8bit",
+        .modes = pmx_telecom_sdhci_8bit_modes,
+        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
         .enb_on_reset = 1,
 };
 
@@ -370,26 +370,6 @@ struct pmx_driver pmx_driver = {
         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-        .gpio_base      = 8,
-        .irq_base       = SPEAR_GPIO1_INT_BASE,
-};
-
-struct amba_device gpio1_device = {
-        .dev = {
-                .init_name = "gpio1",
-                .platform_data = &gpio1_plat_data,
-        },
-        .res = {
-                .start = SPEAR300_GPIO_BASE,
-                .end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {VIRQ_GPIO1, NO_IRQ},
-};
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -443,6 +423,26 @@ struct spear_shirq shirq_ras1 = {
         },
 };
 
+/* Add spear300 specific devices here */
+/* arm gpio1 device registration */
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = SPEAR_GPIO1_INT_BASE,
+};
+
+struct amba_device gpio1_device = {
+        .dev = {
+                .init_name = "gpio1",
+                .platform_data = &gpio1_plat_data,
+        },
+        .res = {
+                .start = SPEAR300_GPIO_BASE,
+                .end = SPEAR300_GPIO_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {VIRQ_GPIO1, NO_IRQ},
+};
+
 /* spear300 routines */
 void __init spear300_init(void)
 {
@@ -452,17 +452,21 @@ void __init spear300_init(void)
         spear3xx_init();
 
         /* shared irq registration */
-        shirq_ras1.regs.base =
-                ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
+        shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
         if (shirq_ras1.regs.base) {
                 ret = spear_shirq_register(&shirq_ras1);
                 if (ret)
                         printk(KERN_ERR "Error registering Shared IRQ\n");
         }
-}
 
-void spear300_pmx_init(void)
-{
-        spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE,
-                        SPEAR300_SOC_CONFIG_SIZE);
+        /* pmx initialization */
+        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
+        if (pmx_driver.base) {
+                ret = pmx_register(&pmx_driver);
+                if (ret)
+                        printk(KERN_ERR "padmux: registeration failed. err no"
+                                        ": %d\n", ret);
+                /* Free Mapping, device selection already done */
+                iounmap(pmx_driver.base);
+        }
 }
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index bb21db152a23..42d2253ef540 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
@@ -28,7 +28,7 @@ static struct pmx_dev *pmx_devs[] = {
         /* spear300 specific devices */
         &pmx_fsmc_2_chips,
         &pmx_clcd,
-        &pmx_telecom_sdio_4bit,
+        &pmx_telecom_sdhci_4bit,
         &pmx_gpio1,
 };
 
@@ -51,14 +51,13 @@ static void __init spear300_evb_init(void)
 {
         unsigned int i;
 
-        /* call spear300 machine init function */
-        spear300_init();
-
-        /* padmux initialization */
+        /* padmux initialization, must be done before spear300_init */
         pmx_driver.mode = &photo_frame_mode;
         pmx_driver.devs = pmx_devs;
         pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-        spear300_pmx_init();
+
+        /* call spear300 machine init function */
+        spear300_init();
 
         /* Add Platform Devices */
         platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
@@ -72,6 +71,6 @@ MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
         .boot_params    =       0x00000100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
-        .timer          =       &spear_sys_timer,
+        .timer          =       &spear3xx_timer,
         .init_machine   =       spear300_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 53b41b52d7ee..5c0a67b60c2a 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -13,9 +13,9 @@
 
 #include <linux/ptrace.h>
 #include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/spear.h>
 #include <plat/shirq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -139,8 +139,6 @@ struct pmx_driver pmx_driver = {
         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear310 specific devices here */
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -257,6 +255,8 @@ struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
+/* Add spear310 specific devices here */
+
 /* spear310 routines */
 void __init spear310_init(void)
 {
@@ -267,7 +267,7 @@ void __init spear310_init(void)
         spear3xx_init();
 
         /* shared irq registration */
-        base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
+        base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
         if (base) {
                 /* shirq 1 */
                 shirq_ras1.regs.base = base;
@@ -293,10 +293,11 @@ void __init spear310_init(void)
                 if (ret)
                         printk(KERN_ERR "Error registering Shared IRQ 4\n");
         }
-}
 
-void spear310_pmx_init(void)
-{
-        spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
-                        SPEAR310_SOC_CONFIG_SIZE);
+        /* pmx initialization */
+        pmx_driver.base = base;
+        ret = pmx_register(&pmx_driver);
+        if (ret)
+                printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
+                                ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 7facf6643199..2d7f333bd67b 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
@@ -58,14 +58,13 @@ static void __init spear310_evb_init(void)
 {
         unsigned int i;
 
-        /* call spear310 machine init function */
-        spear310_init();
-
-        /* padmux initialization */
+        /* padmux initialization, must be done before spear310_init */
         pmx_driver.mode = NULL;
         pmx_driver.devs = pmx_devs;
         pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-        spear310_pmx_init();
+
+        /* call spear310 machine init function */
+        spear310_init();
 
         /* Add Platform Devices */
         platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
@@ -79,6 +78,6 @@ MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
         .boot_params    =       0x00000100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
-        .timer          =       &spear_sys_timer,
+        .timer          =       &spear3xx_timer,
         .init_machine   =       spear310_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 88b465284c36..741c1f414cbd 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -13,9 +13,9 @@
 
 #include <linux/ptrace.h>
 #include <asm/irq.h>
-#include <mach/generic.h>
-#include <mach/spear.h>
 #include <plat/shirq.h>
+#include <mach/generic.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
@@ -110,7 +110,7 @@ struct pmx_dev pmx_spp = {
         .enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_modes[] = {
+struct pmx_dev_mode pmx_sdhci_modes[] = {
         {
                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
                         SMALL_PRINTERS_MODE,
@@ -118,10 +118,10 @@ struct pmx_dev_mode pmx_sdio_modes[] = {
         },
 };
 
-struct pmx_dev pmx_sdio = {
-        .name = "sdio",
-        .modes = pmx_sdio_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdio_modes),
+struct pmx_dev pmx_sdhci = {
+        .name = "sdhci",
+        .modes = pmx_sdhci_modes,
+        .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
         .enb_on_reset = 1,
 };
 
@@ -215,17 +215,17 @@ struct pmx_dev pmx_can = {
         .enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_led_modes[] = {
+struct pmx_dev_mode pmx_sdhci_led_modes[] = {
         {
                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
                 .mask = PMX_SSP_CS_MASK,
         },
 };
 
-struct pmx_dev pmx_sdio_led = {
-        .name = "sdio_led",
-        .modes = pmx_sdio_led_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
+struct pmx_dev pmx_sdhci_led = {
+        .name = "sdhci_led",
+        .modes = pmx_sdhci_led_modes,
+        .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
         .enb_on_reset = 1,
 };
 
@@ -384,8 +384,6 @@ struct pmx_driver pmx_driver = {
         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear320 specific devices here */
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
         {
@@ -510,6 +508,8 @@ struct spear_shirq shirq_intrcomm_ras = {
         },
 };
 
+/* Add spear320 specific devices here */
+
 /* spear320 routines */
 void __init spear320_init(void)
 {
@@ -520,7 +520,7 @@ void __init spear320_init(void)
         spear3xx_init();
 
         /* shared irq registration */
-        base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
+        base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
         if (base) {
                 /* shirq 1 */
                 shirq_ras1.regs.base = base;
@@ -540,10 +540,11 @@ void __init spear320_init(void)
                 if (ret)
                         printk(KERN_ERR "Error registering Shared IRQ 4\n");
         }
-}
 
-void spear320_pmx_init(void)
-{
-        spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
-                        SPEAR320_SOC_CONFIG_SIZE);
+        /* pmx initialization */
+        pmx_driver.base = base;
+        ret = pmx_register(&pmx_driver);
+        if (ret)
+                printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
+                                ret);
 }
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 62ac685a4135..8213e4b66c14 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
@@ -26,7 +26,7 @@ static struct pmx_dev *pmx_devs[] = {
 
         /* spear320 specific devices */
         &pmx_fsmc,
-        &pmx_sdio,
+        &pmx_sdhci,
         &pmx_i2s,
         &pmx_uart1,
         &pmx_uart2,
@@ -55,14 +55,13 @@ static void __init spear320_evb_init(void)
 {
         unsigned int i;
 
-        /* call spear320 machine init function */
-        spear320_init();
-
-        /* padmux initialization */
+        /* padmux initialization, must be done before spear320_init */
         pmx_driver.mode = &auto_net_mii_mode;
         pmx_driver.devs = pmx_devs;
         pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-        spear320_pmx_init();
+
+        /* call spear320 machine init function */
+        spear320_init();
 
         /* Add Platform Devices */
         platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
@@ -76,6 +75,6 @@ MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
         .boot_params    =       0x00000100,
         .map_io         =       spear3xx_map_io,
         .init_irq       =       spear3xx_init_irq,
-        .timer          =       &spear_sys_timer,
+        .timer          =       &spear3xx_timer,
         .init_machine   =       spear320_evb_init,
 MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 52f553c8c46d..d3ba8ca1bc59 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -19,7 +19,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* Add spear3xx machines common devices here */
 /* gpio device registration */
@@ -35,7 +35,7 @@ struct amba_device gpio_device = {
         },
         .res = {
                 .start = SPEAR3XX_ICM3_GPIO_BASE,
-                .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1,
+                .end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
         },
         .irq = {IRQ_BASIC_GPIO, NO_IRQ},
@@ -48,7 +48,7 @@ struct amba_device uart_device = {
         },
         .res = {
                 .start = SPEAR3XX_ICM1_UART_BASE,
-                .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1,
+                .end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
         },
         .irq = {IRQ_UART, NO_IRQ},
@@ -71,22 +71,22 @@ struct map_desc spear3xx_io_desc[] __initdata = {
         {
                 .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-                .length         = SPEAR3XX_ICM1_UART_SIZE,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
                 .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
                 .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SPEAR3XX_ML1_VIC_SIZE,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
                 .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SPEAR3XX_ICM3_SYS_CTRL_SIZE,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
                 .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
                 .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-                .length         = SPEAR3XX_ICM3_MISC_REG_SIZE,
+                .length         = SZ_4K,
                 .type           = MT_DEVICE
         },
 };
@@ -523,26 +523,35 @@ struct pmx_dev pmx_plgpio_45_46_49_50 = {
         .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
         .enb_on_reset = 1,
 };
+#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
 
-#endif
-
-/* spear padmux initialization function */
-void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
+static void __init spear3xx_timer_init(void)
 {
-        int ret = 0;
+        char pclk_name[] = "pll3_48m_clk";
+        struct clk *gpt_clk, *pclk;
+
+        /* get the system timer clock */
+        gpt_clk = clk_get_sys("gpt0", NULL);
+        if (IS_ERR(gpt_clk)) {
+                pr_err("%s:couldn't get clk for gpt\n", __func__);
+                BUG();
+        }
 
-        /* pad mux initialization */
-        pmx_driver->base = ioremap(base, size);
-        if (!pmx_driver->base) {
-                ret = -ENOMEM;
-                goto pmx_fail;
+        /* get the suitable parent clock for timer*/
+        pclk = clk_get(NULL, pclk_name);
+        if (IS_ERR(pclk)) {
+                pr_err("%s:couldn't get %s as parent for gpt\n",
+                                __func__, pclk_name);
+                BUG();
         }
 
-        ret = pmx_register(pmx_driver);
-        iounmap(pmx_driver->base);
+        clk_set_parent(gpt_clk, pclk);
+        clk_put(gpt_clk);
+        clk_put(pclk);
 
-pmx_fail:
-        if (ret)
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
-                                ret);
+        spear_setup_timer();
 }
+
+struct sys_timer spear3xx_timer = {
+        .init = spear3xx_timer_init,
+};