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-rw-r--r--arch/arm/mach-spear3xx/Makefile2
-rw-r--r--arch/arm/mach-spear3xx/clock.c892
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h21
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h2
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h14
-rw-r--r--arch/arm/mach-spear3xx/spear300.c1
-rw-r--r--arch/arm/mach-spear3xx/spear310.c1
-rw-r--r--arch/arm/mach-spear3xx/spear320.c12
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
10 files changed, 31 insertions, 919 deletions
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index 17b5d83cf2d5..8d12faa178fd 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# common files 5# common files
6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o 6obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o
7 7
8# spear300 specific files 8# spear300 specific files
9obj-$(CONFIG_MACH_SPEAR300) += spear300.o 9obj-$(CONFIG_MACH_SPEAR300) += spear300.o
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
deleted file mode 100644
index cd6c11099083..000000000000
--- a/arch/arm/mach-spear3xx/clock.c
+++ /dev/null
@@ -1,892 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/clock.c
3 *
4 * SPEAr3xx machines clock framework source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/clkdev.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/of_platform.h>
19#include <asm/mach-types.h>
20#include <plat/clock.h>
21#include <mach/misc_regs.h>
22#include <mach/spear.h>
23
24#define PLL1_CTR (MISC_BASE + 0x008)
25#define PLL1_FRQ (MISC_BASE + 0x00C)
26#define PLL1_MOD (MISC_BASE + 0x010)
27#define PLL2_CTR (MISC_BASE + 0x014)
28/* PLL_CTR register masks */
29#define PLL_ENABLE 2
30#define PLL_MODE_SHIFT 4
31#define PLL_MODE_MASK 0x3
32#define PLL_MODE_NORMAL 0
33#define PLL_MODE_FRACTION 1
34#define PLL_MODE_DITH_DSB 2
35#define PLL_MODE_DITH_SSB 3
36
37#define PLL2_FRQ (MISC_BASE + 0x018)
38/* PLL FRQ register masks */
39#define PLL_DIV_N_SHIFT 0
40#define PLL_DIV_N_MASK 0xFF
41#define PLL_DIV_P_SHIFT 8
42#define PLL_DIV_P_MASK 0x7
43#define PLL_NORM_FDBK_M_SHIFT 24
44#define PLL_NORM_FDBK_M_MASK 0xFF
45#define PLL_DITH_FDBK_M_SHIFT 16
46#define PLL_DITH_FDBK_M_MASK 0xFFFF
47
48#define PLL2_MOD (MISC_BASE + 0x01C)
49#define PLL_CLK_CFG (MISC_BASE + 0x020)
50#define CORE_CLK_CFG (MISC_BASE + 0x024)
51/* CORE CLK CFG register masks */
52#define PLL_HCLK_RATIO_SHIFT 10
53#define PLL_HCLK_RATIO_MASK 0x3
54#define HCLK_PCLK_RATIO_SHIFT 8
55#define HCLK_PCLK_RATIO_MASK 0x3
56
57#define PERIP_CLK_CFG (MISC_BASE + 0x028)
58/* PERIP_CLK_CFG register masks */
59#define UART_CLK_SHIFT 4
60#define UART_CLK_MASK 0x1
61#define FIRDA_CLK_SHIFT 5
62#define FIRDA_CLK_MASK 0x3
63#define GPT0_CLK_SHIFT 8
64#define GPT1_CLK_SHIFT 11
65#define GPT2_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART_CLK_ENB 3
73#define SSP_CLK_ENB 5
74#define I2C_CLK_ENB 7
75#define JPEG_CLK_ENB 8
76#define FIRDA_CLK_ENB 10
77#define GPT1_CLK_ENB 11
78#define GPT2_CLK_ENB 12
79#define ADC_CLK_ENB 15
80#define RTC_CLK_ENB 17
81#define GPIO_CLK_ENB 18
82#define DMA_CLK_ENB 19
83#define SMI_CLK_ENB 21
84#define GMAC_CLK_ENB 23
85#define USBD_CLK_ENB 24
86#define USBH_CLK_ENB 25
87#define C3_CLK_ENB 31
88
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90
91#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
92#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
93#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
94/* gpt synthesizer register masks */
95#define GPT_MSCALE_SHIFT 0
96#define GPT_MSCALE_MASK 0xFFF
97#define GPT_NSCALE_SHIFT 12
98#define GPT_NSCALE_MASK 0xF
99
100#define AMEM_CLK_CFG (MISC_BASE + 0x050)
101#define EXPI_CLK_CFG (MISC_BASE + 0x054)
102#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
103#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
104#define UART_CLK_SYNT (MISC_BASE + 0x064)
105#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
106#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
107#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
108#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
109#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
110/* aux clk synthesiser register masks for irda to ras4 */
111#define AUX_SYNT_ENB 31
112#define AUX_EQ_SEL_SHIFT 30
113#define AUX_EQ_SEL_MASK 1
114#define AUX_EQ1_SEL 0
115#define AUX_EQ2_SEL 1
116#define AUX_XSCALE_SHIFT 16
117#define AUX_XSCALE_MASK 0xFFF
118#define AUX_YSCALE_SHIFT 0
119#define AUX_YSCALE_MASK 0xFFF
120
121/* root clks */
122/* 32 KHz oscillator clock */
123static struct clk osc_32k_clk = {
124 .flags = ALWAYS_ENABLED,
125 .rate = 32000,
126};
127
128/* 24 MHz oscillator clock */
129static struct clk osc_24m_clk = {
130 .flags = ALWAYS_ENABLED,
131 .rate = 24000000,
132};
133
134/* clock derived from 32 KHz osc clk */
135/* rtc clock */
136static struct clk rtc_clk = {
137 .pclk = &osc_32k_clk,
138 .en_reg = PERIP1_CLK_ENB,
139 .en_reg_bit = RTC_CLK_ENB,
140 .recalc = &follow_parent,
141};
142
143/* clock derived from 24 MHz osc clk */
144/* pll masks structure */
145static struct pll_clk_masks pll1_masks = {
146 .mode_mask = PLL_MODE_MASK,
147 .mode_shift = PLL_MODE_SHIFT,
148 .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
149 .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
150 .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
151 .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
152 .div_p_mask = PLL_DIV_P_MASK,
153 .div_p_shift = PLL_DIV_P_SHIFT,
154 .div_n_mask = PLL_DIV_N_MASK,
155 .div_n_shift = PLL_DIV_N_SHIFT,
156};
157
158/* pll1 configuration structure */
159static struct pll_clk_config pll1_config = {
160 .mode_reg = PLL1_CTR,
161 .cfg_reg = PLL1_FRQ,
162 .masks = &pll1_masks,
163};
164
165/* pll rate configuration table, in ascending order of rates */
166struct pll_rate_tbl pll_rtbl[] = {
167 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
168 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
169};
170
171/* PLL1 clock */
172static struct clk pll1_clk = {
173 .flags = ENABLED_ON_INIT,
174 .pclk = &osc_24m_clk,
175 .en_reg = PLL1_CTR,
176 .en_reg_bit = PLL_ENABLE,
177 .calc_rate = &pll_calc_rate,
178 .recalc = &pll_clk_recalc,
179 .set_rate = &pll_clk_set_rate,
180 .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
181 .private_data = &pll1_config,
182};
183
184/* PLL3 48 MHz clock */
185static struct clk pll3_48m_clk = {
186 .flags = ALWAYS_ENABLED,
187 .pclk = &osc_24m_clk,
188 .rate = 48000000,
189};
190
191/* watch dog timer clock */
192static struct clk wdt_clk = {
193 .flags = ALWAYS_ENABLED,
194 .pclk = &osc_24m_clk,
195 .recalc = &follow_parent,
196};
197
198/* clock derived from pll1 clk */
199/* cpu clock */
200static struct clk cpu_clk = {
201 .flags = ALWAYS_ENABLED,
202 .pclk = &pll1_clk,
203 .recalc = &follow_parent,
204};
205
206/* ahb masks structure */
207static struct bus_clk_masks ahb_masks = {
208 .mask = PLL_HCLK_RATIO_MASK,
209 .shift = PLL_HCLK_RATIO_SHIFT,
210};
211
212/* ahb configuration structure */
213static struct bus_clk_config ahb_config = {
214 .reg = CORE_CLK_CFG,
215 .masks = &ahb_masks,
216};
217
218/* ahb rate configuration table, in ascending order of rates */
219struct bus_rate_tbl bus_rtbl[] = {
220 {.div = 3}, /* == parent divided by 4 */
221 {.div = 2}, /* == parent divided by 3 */
222 {.div = 1}, /* == parent divided by 2 */
223 {.div = 0}, /* == parent divided by 1 */
224};
225
226/* ahb clock */
227static struct clk ahb_clk = {
228 .flags = ALWAYS_ENABLED,
229 .pclk = &pll1_clk,
230 .calc_rate = &bus_calc_rate,
231 .recalc = &bus_clk_recalc,
232 .set_rate = &bus_clk_set_rate,
233 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
234 .private_data = &ahb_config,
235};
236
237/* auxiliary synthesizers masks */
238static struct aux_clk_masks aux_masks = {
239 .eq_sel_mask = AUX_EQ_SEL_MASK,
240 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
241 .eq1_mask = AUX_EQ1_SEL,
242 .eq2_mask = AUX_EQ2_SEL,
243 .xscale_sel_mask = AUX_XSCALE_MASK,
244 .xscale_sel_shift = AUX_XSCALE_SHIFT,
245 .yscale_sel_mask = AUX_YSCALE_MASK,
246 .yscale_sel_shift = AUX_YSCALE_SHIFT,
247};
248
249/* uart synth configurations */
250static struct aux_clk_config uart_synth_config = {
251 .synth_reg = UART_CLK_SYNT,
252 .masks = &aux_masks,
253};
254
255/* aux rate configuration table, in ascending order of rates */
256struct aux_rate_tbl aux_rtbl[] = {
257 /* For PLL1 = 332 MHz */
258 {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
259 {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
260 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
261};
262
263/* uart synth clock */
264static struct clk uart_synth_clk = {
265 .en_reg = UART_CLK_SYNT,
266 .en_reg_bit = AUX_SYNT_ENB,
267 .pclk = &pll1_clk,
268 .calc_rate = &aux_calc_rate,
269 .recalc = &aux_clk_recalc,
270 .set_rate = &aux_clk_set_rate,
271 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
272 .private_data = &uart_synth_config,
273};
274
275/* uart parents */
276static struct pclk_info uart_pclk_info[] = {
277 {
278 .pclk = &uart_synth_clk,
279 .pclk_val = AUX_CLK_PLL1_VAL,
280 }, {
281 .pclk = &pll3_48m_clk,
282 .pclk_val = AUX_CLK_PLL3_VAL,
283 },
284};
285
286/* uart parent select structure */
287static struct pclk_sel uart_pclk_sel = {
288 .pclk_info = uart_pclk_info,
289 .pclk_count = ARRAY_SIZE(uart_pclk_info),
290 .pclk_sel_reg = PERIP_CLK_CFG,
291 .pclk_sel_mask = UART_CLK_MASK,
292};
293
294/* uart clock */
295static struct clk uart_clk = {
296 .en_reg = PERIP1_CLK_ENB,
297 .en_reg_bit = UART_CLK_ENB,
298 .pclk_sel = &uart_pclk_sel,
299 .pclk_sel_shift = UART_CLK_SHIFT,
300 .recalc = &follow_parent,
301};
302
303/* firda configurations */
304static struct aux_clk_config firda_synth_config = {
305 .synth_reg = FIRDA_CLK_SYNT,
306 .masks = &aux_masks,
307};
308
309/* firda synth clock */
310static struct clk firda_synth_clk = {
311 .en_reg = FIRDA_CLK_SYNT,
312 .en_reg_bit = AUX_SYNT_ENB,
313 .pclk = &pll1_clk,
314 .calc_rate = &aux_calc_rate,
315 .recalc = &aux_clk_recalc,
316 .set_rate = &aux_clk_set_rate,
317 .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1},
318 .private_data = &firda_synth_config,
319};
320
321/* firda parents */
322static struct pclk_info firda_pclk_info[] = {
323 {
324 .pclk = &firda_synth_clk,
325 .pclk_val = AUX_CLK_PLL1_VAL,
326 }, {
327 .pclk = &pll3_48m_clk,
328 .pclk_val = AUX_CLK_PLL3_VAL,
329 },
330};
331
332/* firda parent select structure */
333static struct pclk_sel firda_pclk_sel = {
334 .pclk_info = firda_pclk_info,
335 .pclk_count = ARRAY_SIZE(firda_pclk_info),
336 .pclk_sel_reg = PERIP_CLK_CFG,
337 .pclk_sel_mask = FIRDA_CLK_MASK,
338};
339
340/* firda clock */
341static struct clk firda_clk = {
342 .en_reg = PERIP1_CLK_ENB,
343 .en_reg_bit = FIRDA_CLK_ENB,
344 .pclk_sel = &firda_pclk_sel,
345 .pclk_sel_shift = FIRDA_CLK_SHIFT,
346 .recalc = &follow_parent,
347};
348
349/* gpt synthesizer masks */
350static struct gpt_clk_masks gpt_masks = {
351 .mscale_sel_mask = GPT_MSCALE_MASK,
352 .mscale_sel_shift = GPT_MSCALE_SHIFT,
353 .nscale_sel_mask = GPT_NSCALE_MASK,
354 .nscale_sel_shift = GPT_NSCALE_SHIFT,
355};
356
357/* gpt rate configuration table, in ascending order of rates */
358struct gpt_rate_tbl gpt_rtbl[] = {
359 /* For pll1 = 332 MHz */
360 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
361 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
362 {.mscale = 1, .nscale = 0}, /* 83 MHz */
363};
364
365/* gpt0 synth clk config*/
366static struct gpt_clk_config gpt0_synth_config = {
367 .synth_reg = PRSC1_CLK_CFG,
368 .masks = &gpt_masks,
369};
370
371/* gpt synth clock */
372static struct clk gpt0_synth_clk = {
373 .flags = ALWAYS_ENABLED,
374 .pclk = &pll1_clk,
375 .calc_rate = &gpt_calc_rate,
376 .recalc = &gpt_clk_recalc,
377 .set_rate = &gpt_clk_set_rate,
378 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
379 .private_data = &gpt0_synth_config,
380};
381
382/* gpt parents */
383static struct pclk_info gpt0_pclk_info[] = {
384 {
385 .pclk = &gpt0_synth_clk,
386 .pclk_val = AUX_CLK_PLL1_VAL,
387 }, {
388 .pclk = &pll3_48m_clk,
389 .pclk_val = AUX_CLK_PLL3_VAL,
390 },
391};
392
393/* gpt parent select structure */
394static struct pclk_sel gpt0_pclk_sel = {
395 .pclk_info = gpt0_pclk_info,
396 .pclk_count = ARRAY_SIZE(gpt0_pclk_info),
397 .pclk_sel_reg = PERIP_CLK_CFG,
398 .pclk_sel_mask = GPT_CLK_MASK,
399};
400
401/* gpt0 timer clock */
402static struct clk gpt0_clk = {
403 .flags = ALWAYS_ENABLED,
404 .pclk_sel = &gpt0_pclk_sel,
405 .pclk_sel_shift = GPT0_CLK_SHIFT,
406 .recalc = &follow_parent,
407};
408
409/* gpt1 synth clk configurations */
410static struct gpt_clk_config gpt1_synth_config = {
411 .synth_reg = PRSC2_CLK_CFG,
412 .masks = &gpt_masks,
413};
414
415/* gpt1 synth clock */
416static struct clk gpt1_synth_clk = {
417 .flags = ALWAYS_ENABLED,
418 .pclk = &pll1_clk,
419 .calc_rate = &gpt_calc_rate,
420 .recalc = &gpt_clk_recalc,
421 .set_rate = &gpt_clk_set_rate,
422 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
423 .private_data = &gpt1_synth_config,
424};
425
426static struct pclk_info gpt1_pclk_info[] = {
427 {
428 .pclk = &gpt1_synth_clk,
429 .pclk_val = AUX_CLK_PLL1_VAL,
430 }, {
431 .pclk = &pll3_48m_clk,
432 .pclk_val = AUX_CLK_PLL3_VAL,
433 },
434};
435
436/* gpt parent select structure */
437static struct pclk_sel gpt1_pclk_sel = {
438 .pclk_info = gpt1_pclk_info,
439 .pclk_count = ARRAY_SIZE(gpt1_pclk_info),
440 .pclk_sel_reg = PERIP_CLK_CFG,
441 .pclk_sel_mask = GPT_CLK_MASK,
442};
443
444/* gpt1 timer clock */
445static struct clk gpt1_clk = {
446 .en_reg = PERIP1_CLK_ENB,
447 .en_reg_bit = GPT1_CLK_ENB,
448 .pclk_sel = &gpt1_pclk_sel,
449 .pclk_sel_shift = GPT1_CLK_SHIFT,
450 .recalc = &follow_parent,
451};
452
453/* gpt2 synth clk configurations */
454static struct gpt_clk_config gpt2_synth_config = {
455 .synth_reg = PRSC3_CLK_CFG,
456 .masks = &gpt_masks,
457};
458
459/* gpt1 synth clock */
460static struct clk gpt2_synth_clk = {
461 .flags = ALWAYS_ENABLED,
462 .pclk = &pll1_clk,
463 .calc_rate = &gpt_calc_rate,
464 .recalc = &gpt_clk_recalc,
465 .set_rate = &gpt_clk_set_rate,
466 .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
467 .private_data = &gpt2_synth_config,
468};
469
470static struct pclk_info gpt2_pclk_info[] = {
471 {
472 .pclk = &gpt2_synth_clk,
473 .pclk_val = AUX_CLK_PLL1_VAL,
474 }, {
475 .pclk = &pll3_48m_clk,
476 .pclk_val = AUX_CLK_PLL3_VAL,
477 },
478};
479
480/* gpt parent select structure */
481static struct pclk_sel gpt2_pclk_sel = {
482 .pclk_info = gpt2_pclk_info,
483 .pclk_count = ARRAY_SIZE(gpt2_pclk_info),
484 .pclk_sel_reg = PERIP_CLK_CFG,
485 .pclk_sel_mask = GPT_CLK_MASK,
486};
487
488/* gpt2 timer clock */
489static struct clk gpt2_clk = {
490 .en_reg = PERIP1_CLK_ENB,
491 .en_reg_bit = GPT2_CLK_ENB,
492 .pclk_sel = &gpt2_pclk_sel,
493 .pclk_sel_shift = GPT2_CLK_SHIFT,
494 .recalc = &follow_parent,
495};
496
497/* clock derived from pll3 clk */
498/* usbh clock */
499static struct clk usbh_clk = {
500 .pclk = &pll3_48m_clk,
501 .en_reg = PERIP1_CLK_ENB,
502 .en_reg_bit = USBH_CLK_ENB,
503 .recalc = &follow_parent,
504};
505
506/* usbd clock */
507static struct clk usbd_clk = {
508 .pclk = &pll3_48m_clk,
509 .en_reg = PERIP1_CLK_ENB,
510 .en_reg_bit = USBD_CLK_ENB,
511 .recalc = &follow_parent,
512};
513
514/* clock derived from usbh clk */
515/* usbh0 clock */
516static struct clk usbh0_clk = {
517 .flags = ALWAYS_ENABLED,
518 .pclk = &usbh_clk,
519 .recalc = &follow_parent,
520};
521
522/* usbh1 clock */
523static struct clk usbh1_clk = {
524 .flags = ALWAYS_ENABLED,
525 .pclk = &usbh_clk,
526 .recalc = &follow_parent,
527};
528
529/* clock derived from ahb clk */
530/* apb masks structure */
531static struct bus_clk_masks apb_masks = {
532 .mask = HCLK_PCLK_RATIO_MASK,
533 .shift = HCLK_PCLK_RATIO_SHIFT,
534};
535
536/* apb configuration structure */
537static struct bus_clk_config apb_config = {
538 .reg = CORE_CLK_CFG,
539 .masks = &apb_masks,
540};
541
542/* apb clock */
543static struct clk apb_clk = {
544 .flags = ALWAYS_ENABLED,
545 .pclk = &ahb_clk,
546 .calc_rate = &bus_calc_rate,
547 .recalc = &bus_clk_recalc,
548 .set_rate = &bus_clk_set_rate,
549 .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
550 .private_data = &apb_config,
551};
552
553/* i2c clock */
554static struct clk i2c_clk = {
555 .pclk = &ahb_clk,
556 .en_reg = PERIP1_CLK_ENB,
557 .en_reg_bit = I2C_CLK_ENB,
558 .recalc = &follow_parent,
559};
560
561/* dma clock */
562static struct clk dma_clk = {
563 .pclk = &ahb_clk,
564 .en_reg = PERIP1_CLK_ENB,
565 .en_reg_bit = DMA_CLK_ENB,
566 .recalc = &follow_parent,
567};
568
569/* jpeg clock */
570static struct clk jpeg_clk = {
571 .pclk = &ahb_clk,
572 .en_reg = PERIP1_CLK_ENB,
573 .en_reg_bit = JPEG_CLK_ENB,
574 .recalc = &follow_parent,
575};
576
577/* gmac clock */
578static struct clk gmac_clk = {
579 .pclk = &ahb_clk,
580 .en_reg = PERIP1_CLK_ENB,
581 .en_reg_bit = GMAC_CLK_ENB,
582 .recalc = &follow_parent,
583};
584
585/* smi clock */
586static struct clk smi_clk = {
587 .pclk = &ahb_clk,
588 .en_reg = PERIP1_CLK_ENB,
589 .en_reg_bit = SMI_CLK_ENB,
590 .recalc = &follow_parent,
591};
592
593/* c3 clock */
594static struct clk c3_clk = {
595 .pclk = &ahb_clk,
596 .en_reg = PERIP1_CLK_ENB,
597 .en_reg_bit = C3_CLK_ENB,
598 .recalc = &follow_parent,
599};
600
601/* clock derived from apb clk */
602/* adc clock */
603static struct clk adc_clk = {
604 .pclk = &apb_clk,
605 .en_reg = PERIP1_CLK_ENB,
606 .en_reg_bit = ADC_CLK_ENB,
607 .recalc = &follow_parent,
608};
609
610#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
611/* emi clock */
612static struct clk emi_clk = {
613 .flags = ALWAYS_ENABLED,
614 .pclk = &ahb_clk,
615 .recalc = &follow_parent,
616};
617#endif
618
619/* ssp clock */
620static struct clk ssp0_clk = {
621 .pclk = &apb_clk,
622 .en_reg = PERIP1_CLK_ENB,
623 .en_reg_bit = SSP_CLK_ENB,
624 .recalc = &follow_parent,
625};
626
627/* gpio clock */
628static struct clk gpio_clk = {
629 .pclk = &apb_clk,
630 .en_reg = PERIP1_CLK_ENB,
631 .en_reg_bit = GPIO_CLK_ENB,
632 .recalc = &follow_parent,
633};
634
635static struct clk dummy_apb_pclk;
636
637#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
638 defined(CONFIG_MACH_SPEAR320)
639/* fsmc clock */
640static struct clk fsmc_clk = {
641 .flags = ALWAYS_ENABLED,
642 .pclk = &ahb_clk,
643 .recalc = &follow_parent,
644};
645#endif
646
647/* common clocks to spear310 and spear320 */
648#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
649/* uart1 clock */
650static struct clk uart1_clk = {
651 .flags = ALWAYS_ENABLED,
652 .pclk = &apb_clk,
653 .recalc = &follow_parent,
654};
655
656/* uart2 clock */
657static struct clk uart2_clk = {
658 .flags = ALWAYS_ENABLED,
659 .pclk = &apb_clk,
660 .recalc = &follow_parent,
661};
662#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
663
664/* common clocks to spear300 and spear320 */
665#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
666/* clcd clock */
667static struct clk clcd_clk = {
668 .flags = ALWAYS_ENABLED,
669 .pclk = &pll3_48m_clk,
670 .recalc = &follow_parent,
671};
672
673/* sdhci clock */
674static struct clk sdhci_clk = {
675 .flags = ALWAYS_ENABLED,
676 .pclk = &ahb_clk,
677 .recalc = &follow_parent,
678};
679#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
680
681/* spear300 machine specific clock structures */
682#ifdef CONFIG_MACH_SPEAR300
683/* gpio1 clock */
684static struct clk gpio1_clk = {
685 .flags = ALWAYS_ENABLED,
686 .pclk = &apb_clk,
687 .recalc = &follow_parent,
688};
689
690/* keyboard clock */
691static struct clk kbd_clk = {
692 .flags = ALWAYS_ENABLED,
693 .pclk = &apb_clk,
694 .recalc = &follow_parent,
695};
696
697#endif
698
699/* spear310 machine specific clock structures */
700#ifdef CONFIG_MACH_SPEAR310
701/* uart3 clock */
702static struct clk uart3_clk = {
703 .flags = ALWAYS_ENABLED,
704 .pclk = &apb_clk,
705 .recalc = &follow_parent,
706};
707
708/* uart4 clock */
709static struct clk uart4_clk = {
710 .flags = ALWAYS_ENABLED,
711 .pclk = &apb_clk,
712 .recalc = &follow_parent,
713};
714
715/* uart5 clock */
716static struct clk uart5_clk = {
717 .flags = ALWAYS_ENABLED,
718 .pclk = &apb_clk,
719 .recalc = &follow_parent,
720};
721#endif
722
723/* spear320 machine specific clock structures */
724#ifdef CONFIG_MACH_SPEAR320
725/* can0 clock */
726static struct clk can0_clk = {
727 .flags = ALWAYS_ENABLED,
728 .pclk = &apb_clk,
729 .recalc = &follow_parent,
730};
731
732/* can1 clock */
733static struct clk can1_clk = {
734 .flags = ALWAYS_ENABLED,
735 .pclk = &apb_clk,
736 .recalc = &follow_parent,
737};
738
739/* i2c1 clock */
740static struct clk i2c1_clk = {
741 .flags = ALWAYS_ENABLED,
742 .pclk = &ahb_clk,
743 .recalc = &follow_parent,
744};
745
746/* ssp1 clock */
747static struct clk ssp1_clk = {
748 .flags = ALWAYS_ENABLED,
749 .pclk = &apb_clk,
750 .recalc = &follow_parent,
751};
752
753/* ssp2 clock */
754static struct clk ssp2_clk = {
755 .flags = ALWAYS_ENABLED,
756 .pclk = &apb_clk,
757 .recalc = &follow_parent,
758};
759
760/* pwm clock */
761static struct clk pwm_clk = {
762 .flags = ALWAYS_ENABLED,
763 .pclk = &apb_clk,
764 .recalc = &follow_parent,
765};
766#endif
767
768/* array of all spear 3xx clock lookups */
769static struct clk_lookup spear_clk_lookups[] = {
770 CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
771 /* root clks */
772 CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
773 CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
774 /* clock derived from 32 KHz osc clk */
775 CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
776 /* clock derived from 24 MHz osc clk */
777 CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
778 CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
779 CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
780 /* clock derived from pll1 clk */
781 CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
782 CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
783 CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
784 CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
785 CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
786 CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
787 CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
788 CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
789 CLKDEV_INIT("firda", NULL, &firda_clk),
790 CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
791 CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
792 CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
793 /* clock derived from pll3 clk */
794 CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
795 CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
796 /* clock derived from usbh clk */
797 CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
798 CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
799 /* clock derived from ahb clk */
800 CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
801 CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
802 CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
803 CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
804 CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
805 CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
806 CLKDEV_INIT("c3", NULL, &c3_clk),
807 /* clock derived from apb clk */
808 CLKDEV_INIT("adc", NULL, &adc_clk),
809 CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
810 CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
811};
812
813/* array of all spear 300 clock lookups */
814#ifdef CONFIG_MACH_SPEAR300
815static struct clk_lookup spear300_clk_lookups[] = {
816 CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
817 CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
818 CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
819 CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
820 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
821};
822
823void __init spear300_clk_init(void)
824{
825 int i;
826
827 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
828 clk_register(&spear_clk_lookups[i]);
829
830 for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
831 clk_register(&spear300_clk_lookups[i]);
832
833 clk_init();
834}
835#endif
836
837/* array of all spear 310 clock lookups */
838#ifdef CONFIG_MACH_SPEAR310
839static struct clk_lookup spear310_clk_lookups[] = {
840 CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
841 CLKDEV_INIT(NULL, "emi", &emi_clk),
842 CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
843 CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
844 CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
845 CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
846 CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
847};
848
849void __init spear310_clk_init(void)
850{
851 int i;
852
853 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
854 clk_register(&spear_clk_lookups[i]);
855
856 for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
857 clk_register(&spear310_clk_lookups[i]);
858
859 clk_init();
860}
861#endif
862
863/* array of all spear 320 clock lookups */
864#ifdef CONFIG_MACH_SPEAR320
865static struct clk_lookup spear320_clk_lookups[] = {
866 CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
867 CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
868 CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
869 CLKDEV_INIT(NULL, "emi", &emi_clk),
870 CLKDEV_INIT("pwm", NULL, &pwm_clk),
871 CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
872 CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
873 CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
874 CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
875 CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
876 CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
877 CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
878};
879
880void __init spear320_clk_init(void)
881{
882 int i;
883
884 for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
885 clk_register(&spear_clk_lookups[i]);
886
887 for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
888 clk_register(&spear320_clk_lookups[i]);
889
890 clk_init();
891}
892#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index bdb304551caf..4a95b9453c2a 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,28 +27,11 @@ extern struct pl022_ssp_controller pl022_plat_data;
27extern struct pl08x_platform_data pl080_plat_data; 27extern struct pl08x_platform_data pl080_plat_data;
28 28
29/* Add spear3xx family function declarations here */ 29/* Add spear3xx family function declarations here */
30void __init spear_setup_timer(resource_size_t base, int irq); 30void __init spear_setup_of_timer(void);
31void __init spear3xx_clk_init(void);
31void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
32void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
33 34
34void spear_restart(char, const char *); 35void spear_restart(char, const char *);
35 36
36/* spear300 declarations */
37#ifdef CONFIG_MACH_SPEAR300
38void __init spear300_clk_init(void);
39
40#endif /* CONFIG_MACH_SPEAR300 */
41
42/* spear310 declarations */
43#ifdef CONFIG_MACH_SPEAR310
44void __init spear310_clk_init(void);
45
46#endif /* CONFIG_MACH_SPEAR310 */
47
48/* spear320 declarations */
49#ifdef CONFIG_MACH_SPEAR320
50void __init spear320_clk_init(void);
51
52#endif /* CONFIG_MACH_SPEAR320 */
53
54#endif /* __MACH_GENERIC_H */ 37#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 319620a1afb4..51bd62a0254c 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -16,7 +16,6 @@
16 16
17/* FIXME: probe all these from DT */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
19#define SPEAR3XX_IRQ_CPU_GPT1_1 2
20#define SPEAR3XX_IRQ_GEN_RAS_1 28 19#define SPEAR3XX_IRQ_GEN_RAS_1 28
21#define SPEAR3XX_IRQ_GEN_RAS_2 29 20#define SPEAR3XX_IRQ_GEN_RAS_2 29
22#define SPEAR3XX_IRQ_GEN_RAS_3 30 21#define SPEAR3XX_IRQ_GEN_RAS_3 30
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index e0ab72e61507..18e2ac576f25 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,6 +14,8 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/spear.h>
18
17#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
18#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 20#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
19 21
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 6d4dadc67633..51eb953148a9 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -26,7 +26,6 @@
26/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
29#define SPEAR3XX_CPU_TMR_BASE UL(0xF0000000)
30 29
31/* ICM3 - Basic Subsystem */ 30/* ICM3 - Basic Subsystem */
32#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 31#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
@@ -45,4 +44,17 @@
45#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE 44#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
46#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE 45#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
47 46
47/* SPEAr320 Macros */
48#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
49#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
50#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
51#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
52 #define SPEAR320_UARTX_PCLK_MASK 0x1
53 #define SPEAR320_UART2_PCLK_SHIFT 8
54 #define SPEAR320_UART3_PCLK_SHIFT 9
55 #define SPEAR320_UART4_PCLK_SHIFT 10
56 #define SPEAR320_UART5_PCLK_SHIFT 11
57 #define SPEAR320_UART6_PCLK_SHIFT 12
58 #define SPEAR320_RS485_PCLK_SHIFT 13
59
48#endif /* __MACH_SPEAR3XX_H */ 60#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f75fe25a620c..f74a05bdb829 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -337,7 +337,6 @@ static const char * const spear300_dt_board_compat[] = {
337static void __init spear300_map_io(void) 337static void __init spear300_map_io(void)
338{ 338{
339 spear3xx_map_io(); 339 spear3xx_map_io();
340 spear300_clk_init();
341} 340}
342 341
343DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree") 342DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index f0842a58dc02..84dfb0900747 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -478,7 +478,6 @@ static const char * const spear310_dt_board_compat[] = {
478static void __init spear310_map_io(void) 478static void __init spear310_map_io(void)
479{ 479{
480 spear3xx_map_io(); 480 spear3xx_map_io();
481 spear310_clk_init();
482} 481}
483 482
484DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") 483DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index e8caeef50a5c..a88fa841d29d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -27,7 +27,6 @@
27#define SPEAR320_UART2_BASE UL(0xA4000000) 27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000) 28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000) 29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
31 30
32/* Interrupt registers offsets and masks */ 31/* Interrupt registers offsets and masks */
33#define SPEAR320_INT_STS_MASK_REG 0x04 32#define SPEAR320_INT_STS_MASK_REG 0x04
@@ -481,10 +480,19 @@ static const char * const spear320_dt_board_compat[] = {
481 NULL, 480 NULL,
482}; 481};
483 482
483struct map_desc spear320_io_desc[] __initdata = {
484 {
485 .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
486 .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
487 .length = SZ_16M,
488 .type = MT_DEVICE
489 },
490};
491
484static void __init spear320_map_io(void) 492static void __init spear320_map_io(void)
485{ 493{
494 iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
486 spear3xx_map_io(); 495 spear3xx_map_io();
487 spear320_clk_init();
488} 496}
489 497
490DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree") 498DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 826ac20ef1e7..f22419ed74a8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -90,6 +90,8 @@ static void __init spear3xx_timer_init(void)
90 char pclk_name[] = "pll3_48m_clk"; 90 char pclk_name[] = "pll3_48m_clk";
91 struct clk *gpt_clk, *pclk; 91 struct clk *gpt_clk, *pclk;
92 92
93 spear3xx_clk_init();
94
93 /* get the system timer clock */ 95 /* get the system timer clock */
94 gpt_clk = clk_get_sys("gpt0", NULL); 96 gpt_clk = clk_get_sys("gpt0", NULL);
95 if (IS_ERR(gpt_clk)) { 97 if (IS_ERR(gpt_clk)) {
@@ -109,7 +111,7 @@ static void __init spear3xx_timer_init(void)
109 clk_put(gpt_clk); 111 clk_put(gpt_clk);
110 clk_put(pclk); 112 clk_put(pclk);
111 113
112 spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1); 114 spear_setup_of_timer();
113} 115}
114 116
115struct sys_timer spear3xx_timer = { 117struct sys_timer spear3xx_timer = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 12:31:07 -0500