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-rw-r--r--arch/arm/mach-spear3xx/spear320.c663
1 files changed, 273 insertions, 390 deletions
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index bfdad554319c..fb28c189688e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,388 +3,27 @@
3 * 3 *
4 * SPEAr320 machine source file 4 * SPEAr320 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/ptrace.h> 14#define pr_fmt(fmt) "SPEAr320: " fmt
15#include <asm/irq.h> 15
16#include <linux/amba/pl022.h>
17#include <linux/amba/pl08x.h>
18#include <linux/amba/serial.h>
19#include <linux/of_platform.h>
20#include <asm/hardware/vic.h>
21#include <asm/mach/arch.h>
16#include <plat/shirq.h> 22#include <plat/shirq.h>
17#include <mach/generic.h> 23#include <mach/generic.h>
18#include <mach/hardware.h> 24#include <mach/hardware.h>
19#include <mach/spear.h> 25#include <mach/spear.h>
20 26
21/* pad multiplexing support */
22/* muxing registers */
23#define PAD_MUX_CONFIG_REG 0x0C
24#define MODE_CONFIG_REG 0x10
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define ALL_MODES 0xF
32
33struct pmx_mode spear320_auto_net_smii_mode = {
34 .id = AUTO_NET_SMII_MODE,
35 .name = "Automation Networking SMII Mode",
36 .mask = 0x00,
37};
38
39struct pmx_mode spear320_auto_net_mii_mode = {
40 .id = AUTO_NET_MII_MODE,
41 .name = "Automation Networking MII Mode",
42 .mask = 0x01,
43};
44
45struct pmx_mode spear320_auto_exp_mode = {
46 .id = AUTO_EXP_MODE,
47 .name = "Automation Expanded Mode",
48 .mask = 0x02,
49};
50
51struct pmx_mode spear320_small_printers_mode = {
52 .id = SMALL_PRINTERS_MODE,
53 .name = "Small Printers Mode",
54 .mask = 0x03,
55};
56
57/* devices */
58static struct pmx_dev_mode pmx_clcd_modes[] = {
59 {
60 .ids = AUTO_NET_SMII_MODE,
61 .mask = 0x0,
62 },
63};
64
65struct pmx_dev spear320_pmx_clcd = {
66 .name = "clcd",
67 .modes = pmx_clcd_modes,
68 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
69 .enb_on_reset = 1,
70};
71
72static struct pmx_dev_mode pmx_emi_modes[] = {
73 {
74 .ids = AUTO_EXP_MODE,
75 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
76 },
77};
78
79struct pmx_dev spear320_pmx_emi = {
80 .name = "emi",
81 .modes = pmx_emi_modes,
82 .mode_count = ARRAY_SIZE(pmx_emi_modes),
83 .enb_on_reset = 1,
84};
85
86static struct pmx_dev_mode pmx_fsmc_modes[] = {
87 {
88 .ids = ALL_MODES,
89 .mask = 0x0,
90 },
91};
92
93struct pmx_dev spear320_pmx_fsmc = {
94 .name = "fsmc",
95 .modes = pmx_fsmc_modes,
96 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
97 .enb_on_reset = 1,
98};
99
100static struct pmx_dev_mode pmx_spp_modes[] = {
101 {
102 .ids = SMALL_PRINTERS_MODE,
103 .mask = 0x0,
104 },
105};
106
107struct pmx_dev spear320_pmx_spp = {
108 .name = "spp",
109 .modes = pmx_spp_modes,
110 .mode_count = ARRAY_SIZE(pmx_spp_modes),
111 .enb_on_reset = 1,
112};
113
114static struct pmx_dev_mode pmx_sdhci_modes[] = {
115 {
116 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
117 SMALL_PRINTERS_MODE,
118 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
119 },
120};
121
122struct pmx_dev spear320_pmx_sdhci = {
123 .name = "sdhci",
124 .modes = pmx_sdhci_modes,
125 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
126 .enb_on_reset = 1,
127};
128
129static struct pmx_dev_mode pmx_i2s_modes[] = {
130 {
131 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
132 .mask = PMX_UART0_MODEM_MASK,
133 },
134};
135
136struct pmx_dev spear320_pmx_i2s = {
137 .name = "i2s",
138 .modes = pmx_i2s_modes,
139 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
140 .enb_on_reset = 1,
141};
142
143static struct pmx_dev_mode pmx_uart1_modes[] = {
144 {
145 .ids = ALL_MODES,
146 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
147 },
148};
149
150struct pmx_dev spear320_pmx_uart1 = {
151 .name = "uart1",
152 .modes = pmx_uart1_modes,
153 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
154 .enb_on_reset = 1,
155};
156
157static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
158 {
159 .ids = AUTO_EXP_MODE,
160 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
161 PMX_SSP_CS_MASK,
162 }, {
163 .ids = SMALL_PRINTERS_MODE,
164 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
165 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
166 },
167};
168
169struct pmx_dev spear320_pmx_uart1_modem = {
170 .name = "uart1_modem",
171 .modes = pmx_uart1_modem_modes,
172 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
173 .enb_on_reset = 1,
174};
175
176static struct pmx_dev_mode pmx_uart2_modes[] = {
177 {
178 .ids = ALL_MODES,
179 .mask = PMX_FIRDA_MASK,
180 },
181};
182
183struct pmx_dev spear320_pmx_uart2 = {
184 .name = "uart2",
185 .modes = pmx_uart2_modes,
186 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
187 .enb_on_reset = 1,
188};
189
190static struct pmx_dev_mode pmx_touchscreen_modes[] = {
191 {
192 .ids = AUTO_NET_SMII_MODE,
193 .mask = PMX_SSP_CS_MASK,
194 },
195};
196
197struct pmx_dev spear320_pmx_touchscreen = {
198 .name = "touchscreen",
199 .modes = pmx_touchscreen_modes,
200 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
201 .enb_on_reset = 1,
202};
203
204static struct pmx_dev_mode pmx_can_modes[] = {
205 {
206 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
207 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
208 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
209 },
210};
211
212struct pmx_dev spear320_pmx_can = {
213 .name = "can",
214 .modes = pmx_can_modes,
215 .mode_count = ARRAY_SIZE(pmx_can_modes),
216 .enb_on_reset = 1,
217};
218
219static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
220 {
221 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
222 .mask = PMX_SSP_CS_MASK,
223 },
224};
225
226struct pmx_dev spear320_pmx_sdhci_led = {
227 .name = "sdhci_led",
228 .modes = pmx_sdhci_led_modes,
229 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
230 .enb_on_reset = 1,
231};
232
233static struct pmx_dev_mode pmx_pwm0_modes[] = {
234 {
235 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
236 .mask = PMX_UART0_MODEM_MASK,
237 }, {
238 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
239 .mask = PMX_MII_MASK,
240 },
241};
242
243struct pmx_dev spear320_pmx_pwm0 = {
244 .name = "pwm0",
245 .modes = pmx_pwm0_modes,
246 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
247 .enb_on_reset = 1,
248};
249
250static struct pmx_dev_mode pmx_pwm1_modes[] = {
251 {
252 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
253 .mask = PMX_UART0_MODEM_MASK,
254 }, {
255 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
256 .mask = PMX_MII_MASK,
257 },
258};
259
260struct pmx_dev spear320_pmx_pwm1 = {
261 .name = "pwm1",
262 .modes = pmx_pwm1_modes,
263 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
264 .enb_on_reset = 1,
265};
266
267static struct pmx_dev_mode pmx_pwm2_modes[] = {
268 {
269 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
270 .mask = PMX_SSP_CS_MASK,
271 }, {
272 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
273 .mask = PMX_MII_MASK,
274 },
275};
276
277struct pmx_dev spear320_pmx_pwm2 = {
278 .name = "pwm2",
279 .modes = pmx_pwm2_modes,
280 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
281 .enb_on_reset = 1,
282};
283
284static struct pmx_dev_mode pmx_pwm3_modes[] = {
285 {
286 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
287 .mask = PMX_MII_MASK,
288 },
289};
290
291struct pmx_dev spear320_pmx_pwm3 = {
292 .name = "pwm3",
293 .modes = pmx_pwm3_modes,
294 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_ssp1_modes[] = {
299 {
300 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
301 .mask = PMX_MII_MASK,
302 },
303};
304
305struct pmx_dev spear320_pmx_ssp1 = {
306 .name = "ssp1",
307 .modes = pmx_ssp1_modes,
308 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
309 .enb_on_reset = 1,
310};
311
312static struct pmx_dev_mode pmx_ssp2_modes[] = {
313 {
314 .ids = AUTO_NET_SMII_MODE,
315 .mask = PMX_MII_MASK,
316 },
317};
318
319struct pmx_dev spear320_pmx_ssp2 = {
320 .name = "ssp2",
321 .modes = pmx_ssp2_modes,
322 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
323 .enb_on_reset = 1,
324};
325
326static struct pmx_dev_mode pmx_mii1_modes[] = {
327 {
328 .ids = AUTO_NET_MII_MODE,
329 .mask = 0x0,
330 },
331};
332
333struct pmx_dev spear320_pmx_mii1 = {
334 .name = "mii1",
335 .modes = pmx_mii1_modes,
336 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
337 .enb_on_reset = 1,
338};
339
340static struct pmx_dev_mode pmx_smii0_modes[] = {
341 {
342 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
343 .mask = PMX_MII_MASK,
344 },
345};
346
347struct pmx_dev spear320_pmx_smii0 = {
348 .name = "smii0",
349 .modes = pmx_smii0_modes,
350 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
351 .enb_on_reset = 1,
352};
353
354static struct pmx_dev_mode pmx_smii1_modes[] = {
355 {
356 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
357 .mask = PMX_MII_MASK,
358 },
359};
360
361struct pmx_dev spear320_pmx_smii1 = {
362 .name = "smii1",
363 .modes = pmx_smii1_modes,
364 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
365 .enb_on_reset = 1,
366};
367
368static struct pmx_dev_mode pmx_i2c1_modes[] = {
369 {
370 .ids = AUTO_EXP_MODE,
371 .mask = 0x0,
372 },
373};
374
375struct pmx_dev spear320_pmx_i2c1 = {
376 .name = "i2c1",
377 .modes = pmx_i2c1_modes,
378 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
379 .enb_on_reset = 1,
380};
381
382/* pmx driver structure */
383static struct pmx_driver pmx_driver = {
384 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
385 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
386};
387
388/* spear3xx shared irq */ 27/* spear3xx shared irq */
389static struct shirq_dev_config shirq_ras1_config[] = { 28static struct shirq_dev_config shirq_ras1_config[] = {
390 { 29 {
@@ -509,17 +148,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
509 }, 148 },
510}; 149};
511 150
512/* Add spear320 specific devices here */ 151/* DMAC platform data's slave info */
152struct pl08x_channel_data spear320_dma_info[] = {
153 {
154 .bus_id = "uart0_rx",
155 .min_signal = 2,
156 .max_signal = 2,
157 .muxval = 0,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "uart0_tx",
162 .min_signal = 3,
163 .max_signal = 3,
164 .muxval = 0,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ssp0_rx",
169 .min_signal = 8,
170 .max_signal = 8,
171 .muxval = 0,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ssp0_tx",
176 .min_signal = 9,
177 .max_signal = 9,
178 .muxval = 0,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "i2c0_rx",
183 .min_signal = 10,
184 .max_signal = 10,
185 .muxval = 0,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "i2c0_tx",
190 .min_signal = 11,
191 .max_signal = 11,
192 .muxval = 0,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "irda",
197 .min_signal = 12,
198 .max_signal = 12,
199 .muxval = 0,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "adc",
204 .min_signal = 13,
205 .max_signal = 13,
206 .muxval = 0,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "to_jpeg",
211 .min_signal = 14,
212 .max_signal = 14,
213 .muxval = 0,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "from_jpeg",
218 .min_signal = 15,
219 .max_signal = 15,
220 .muxval = 0,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ssp1_rx",
225 .min_signal = 0,
226 .max_signal = 0,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB2,
230 }, {
231 .bus_id = "ssp1_tx",
232 .min_signal = 1,
233 .max_signal = 1,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB2,
237 }, {
238 .bus_id = "ssp2_rx",
239 .min_signal = 2,
240 .max_signal = 2,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB2,
244 }, {
245 .bus_id = "ssp2_tx",
246 .min_signal = 3,
247 .max_signal = 3,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB2,
251 }, {
252 .bus_id = "uart1_rx",
253 .min_signal = 4,
254 .max_signal = 4,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB2,
258 }, {
259 .bus_id = "uart1_tx",
260 .min_signal = 5,
261 .max_signal = 5,
262 .muxval = 1,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "uart2_rx",
267 .min_signal = 6,
268 .max_signal = 6,
269 .muxval = 1,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "uart2_tx",
274 .min_signal = 7,
275 .max_signal = 7,
276 .muxval = 1,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "i2c1_rx",
281 .min_signal = 8,
282 .max_signal = 8,
283 .muxval = 1,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "i2c1_tx",
288 .min_signal = 9,
289 .max_signal = 9,
290 .muxval = 1,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "i2c2_rx",
295 .min_signal = 10,
296 .max_signal = 10,
297 .muxval = 1,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "i2c2_tx",
302 .min_signal = 11,
303 .max_signal = 11,
304 .muxval = 1,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "i2s_rx",
309 .min_signal = 12,
310 .max_signal = 12,
311 .muxval = 1,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "i2s_tx",
316 .min_signal = 13,
317 .max_signal = 13,
318 .muxval = 1,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "rs485_rx",
323 .min_signal = 14,
324 .max_signal = 14,
325 .muxval = 1,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "rs485_tx",
330 .min_signal = 15,
331 .max_signal = 15,
332 .muxval = 1,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 },
336};
337
338static struct pl022_ssp_controller spear320_ssp_data[] = {
339 {
340 .bus_id = 1,
341 .enable_dma = 1,
342 .dma_filter = pl08x_filter_id,
343 .dma_tx_param = "ssp1_tx",
344 .dma_rx_param = "ssp1_rx",
345 .num_chipselect = 2,
346 }, {
347 .bus_id = 2,
348 .enable_dma = 1,
349 .dma_filter = pl08x_filter_id,
350 .dma_tx_param = "ssp2_tx",
351 .dma_rx_param = "ssp2_rx",
352 .num_chipselect = 2,
353 }
354};
355
356static struct amba_pl011_data spear320_uart_data[] = {
357 {
358 .dma_filter = pl08x_filter_id,
359 .dma_tx_param = "uart1_tx",
360 .dma_rx_param = "uart1_rx",
361 }, {
362 .dma_filter = pl08x_filter_id,
363 .dma_tx_param = "uart2_tx",
364 .dma_rx_param = "uart2_rx",
365 },
366};
513 367
514/* spear320 routines */ 368/* Add SPEAr310 auxdata to pass platform data */
515void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, 369static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
516 u8 pmx_dev_count) 370 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
371 &pl022_plat_data),
372 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
373 &pl080_plat_data),
374 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
375 &spear320_ssp_data[0]),
376 OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
377 &spear320_ssp_data[1]),
378 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
379 &spear320_uart_data[0]),
380 OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
381 &spear320_uart_data[1]),
382 {}
383};
384
385static void __init spear320_dt_init(void)
517{ 386{
518 void __iomem *base; 387 void __iomem *base;
519 int ret = 0; 388 int ret;
389
390 pl080_plat_data.slave_channels = spear320_dma_info;
391 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
520 392
521 /* call spear3xx family common init function */ 393 of_platform_populate(NULL, of_default_bus_match_table,
522 spear3xx_init(); 394 spear320_auxdata_lookup, NULL);
523 395
524 /* shared irq registration */ 396 /* shared irq registration */
525 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K); 397 base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -528,29 +400,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
528 shirq_ras1.regs.base = base; 400 shirq_ras1.regs.base = base;
529 ret = spear_shirq_register(&shirq_ras1); 401 ret = spear_shirq_register(&shirq_ras1);
530 if (ret) 402 if (ret)
531 printk(KERN_ERR "Error registering Shared IRQ 1\n"); 403 pr_err("Error registering Shared IRQ 1\n");
532 404
533 /* shirq 3 */ 405 /* shirq 3 */
534 shirq_ras3.regs.base = base; 406 shirq_ras3.regs.base = base;
535 ret = spear_shirq_register(&shirq_ras3); 407 ret = spear_shirq_register(&shirq_ras3);
536 if (ret) 408 if (ret)
537 printk(KERN_ERR "Error registering Shared IRQ 3\n"); 409 pr_err("Error registering Shared IRQ 3\n");
538 410
539 /* shirq 4 */ 411 /* shirq 4 */
540 shirq_intrcomm_ras.regs.base = base; 412 shirq_intrcomm_ras.regs.base = base;
541 ret = spear_shirq_register(&shirq_intrcomm_ras); 413 ret = spear_shirq_register(&shirq_intrcomm_ras);
542 if (ret) 414 if (ret)
543 printk(KERN_ERR "Error registering Shared IRQ 4\n"); 415 pr_err("Error registering Shared IRQ 4\n");
544 } 416 }
417}
545 418
546 /* pmx initialization */ 419static const char * const spear320_dt_board_compat[] = {
547 pmx_driver.base = base; 420 "st,spear320",
548 pmx_driver.mode = pmx_mode; 421 "st,spear320-evb",
549 pmx_driver.devs = pmx_devs; 422 NULL,
550 pmx_driver.devs_count = pmx_dev_count; 423};
551 424
552 ret = pmx_register(&pmx_driver); 425static void __init spear320_map_io(void)
553 if (ret) 426{
554 printk(KERN_ERR "padmux: registration failed. err no: %d\n", 427 spear3xx_map_io();
555 ret); 428 spear320_clk_init();
556} 429}
430
431DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
432 .map_io = spear320_map_io,
433 .init_irq = spear3xx_dt_init_irq,
434 .handle_irq = vic_handle_irq,
435 .timer = &spear3xx_timer,
436 .init_machine = spear320_dt_init,
437 .restart = spear_restart,
438 .dt_compat = spear320_dt_board_compat,
439MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 09:11:26 -0500