aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-spear3xx/spear320.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-spear3xx/spear320.c')
-rw-r--r--arch/arm/mach-spear3xx/spear320.c251
1 files changed, 128 insertions, 123 deletions
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 741c1f414cbd..ee29bef43074 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -29,88 +29,88 @@
29#define SMALL_PRINTERS_MODE (1 << 3) 29#define SMALL_PRINTERS_MODE (1 << 3)
30#define ALL_MODES 0xF 30#define ALL_MODES 0xF
31 31
32struct pmx_mode auto_net_smii_mode = { 32struct pmx_mode spear320_auto_net_smii_mode = {
33 .id = AUTO_NET_SMII_MODE, 33 .id = AUTO_NET_SMII_MODE,
34 .name = "Automation Networking SMII Mode", 34 .name = "Automation Networking SMII Mode",
35 .mask = 0x00, 35 .mask = 0x00,
36}; 36};
37 37
38struct pmx_mode auto_net_mii_mode = { 38struct pmx_mode spear320_auto_net_mii_mode = {
39 .id = AUTO_NET_MII_MODE, 39 .id = AUTO_NET_MII_MODE,
40 .name = "Automation Networking MII Mode", 40 .name = "Automation Networking MII Mode",
41 .mask = 0x01, 41 .mask = 0x01,
42}; 42};
43 43
44struct pmx_mode auto_exp_mode = { 44struct pmx_mode spear320_auto_exp_mode = {
45 .id = AUTO_EXP_MODE, 45 .id = AUTO_EXP_MODE,
46 .name = "Automation Expanded Mode", 46 .name = "Automation Expanded Mode",
47 .mask = 0x02, 47 .mask = 0x02,
48}; 48};
49 49
50struct pmx_mode small_printers_mode = { 50struct pmx_mode spear320_small_printers_mode = {
51 .id = SMALL_PRINTERS_MODE, 51 .id = SMALL_PRINTERS_MODE,
52 .name = "Small Printers Mode", 52 .name = "Small Printers Mode",
53 .mask = 0x03, 53 .mask = 0x03,
54}; 54};
55 55
56/* devices */ 56/* devices */
57struct pmx_dev_mode pmx_clcd_modes[] = { 57static struct pmx_dev_mode pmx_clcd_modes[] = {
58 { 58 {
59 .ids = AUTO_NET_SMII_MODE, 59 .ids = AUTO_NET_SMII_MODE,
60 .mask = 0x0, 60 .mask = 0x0,
61 }, 61 },
62}; 62};
63 63
64struct pmx_dev pmx_clcd = { 64struct pmx_dev spear320_pmx_clcd = {
65 .name = "clcd", 65 .name = "clcd",
66 .modes = pmx_clcd_modes, 66 .modes = pmx_clcd_modes,
67 .mode_count = ARRAY_SIZE(pmx_clcd_modes), 67 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
68 .enb_on_reset = 1, 68 .enb_on_reset = 1,
69}; 69};
70 70
71struct pmx_dev_mode pmx_emi_modes[] = { 71static struct pmx_dev_mode pmx_emi_modes[] = {
72 { 72 {
73 .ids = AUTO_EXP_MODE, 73 .ids = AUTO_EXP_MODE,
74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, 74 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
75 }, 75 },
76}; 76};
77 77
78struct pmx_dev pmx_emi = { 78struct pmx_dev spear320_pmx_emi = {
79 .name = "emi", 79 .name = "emi",
80 .modes = pmx_emi_modes, 80 .modes = pmx_emi_modes,
81 .mode_count = ARRAY_SIZE(pmx_emi_modes), 81 .mode_count = ARRAY_SIZE(pmx_emi_modes),
82 .enb_on_reset = 1, 82 .enb_on_reset = 1,
83}; 83};
84 84
85struct pmx_dev_mode pmx_fsmc_modes[] = { 85static struct pmx_dev_mode pmx_fsmc_modes[] = {
86 { 86 {
87 .ids = ALL_MODES, 87 .ids = ALL_MODES,
88 .mask = 0x0, 88 .mask = 0x0,
89 }, 89 },
90}; 90};
91 91
92struct pmx_dev pmx_fsmc = { 92struct pmx_dev spear320_pmx_fsmc = {
93 .name = "fsmc", 93 .name = "fsmc",
94 .modes = pmx_fsmc_modes, 94 .modes = pmx_fsmc_modes,
95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes), 95 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
96 .enb_on_reset = 1, 96 .enb_on_reset = 1,
97}; 97};
98 98
99struct pmx_dev_mode pmx_spp_modes[] = { 99static struct pmx_dev_mode pmx_spp_modes[] = {
100 { 100 {
101 .ids = SMALL_PRINTERS_MODE, 101 .ids = SMALL_PRINTERS_MODE,
102 .mask = 0x0, 102 .mask = 0x0,
103 }, 103 },
104}; 104};
105 105
106struct pmx_dev pmx_spp = { 106struct pmx_dev spear320_pmx_spp = {
107 .name = "spp", 107 .name = "spp",
108 .modes = pmx_spp_modes, 108 .modes = pmx_spp_modes,
109 .mode_count = ARRAY_SIZE(pmx_spp_modes), 109 .mode_count = ARRAY_SIZE(pmx_spp_modes),
110 .enb_on_reset = 1, 110 .enb_on_reset = 1,
111}; 111};
112 112
113struct pmx_dev_mode pmx_sdhci_modes[] = { 113static struct pmx_dev_mode pmx_sdhci_modes[] = {
114 { 114 {
115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | 115 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
116 SMALL_PRINTERS_MODE, 116 SMALL_PRINTERS_MODE,
@@ -118,42 +118,42 @@ struct pmx_dev_mode pmx_sdhci_modes[] = {
118 }, 118 },
119}; 119};
120 120
121struct pmx_dev pmx_sdhci = { 121struct pmx_dev spear320_pmx_sdhci = {
122 .name = "sdhci", 122 .name = "sdhci",
123 .modes = pmx_sdhci_modes, 123 .modes = pmx_sdhci_modes,
124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes), 124 .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
125 .enb_on_reset = 1, 125 .enb_on_reset = 1,
126}; 126};
127 127
128struct pmx_dev_mode pmx_i2s_modes[] = { 128static struct pmx_dev_mode pmx_i2s_modes[] = {
129 { 129 {
130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 130 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
131 .mask = PMX_UART0_MODEM_MASK, 131 .mask = PMX_UART0_MODEM_MASK,
132 }, 132 },
133}; 133};
134 134
135struct pmx_dev pmx_i2s = { 135struct pmx_dev spear320_pmx_i2s = {
136 .name = "i2s", 136 .name = "i2s",
137 .modes = pmx_i2s_modes, 137 .modes = pmx_i2s_modes,
138 .mode_count = ARRAY_SIZE(pmx_i2s_modes), 138 .mode_count = ARRAY_SIZE(pmx_i2s_modes),
139 .enb_on_reset = 1, 139 .enb_on_reset = 1,
140}; 140};
141 141
142struct pmx_dev_mode pmx_uart1_modes[] = { 142static struct pmx_dev_mode pmx_uart1_modes[] = {
143 { 143 {
144 .ids = ALL_MODES, 144 .ids = ALL_MODES,
145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, 145 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
146 }, 146 },
147}; 147};
148 148
149struct pmx_dev pmx_uart1 = { 149struct pmx_dev spear320_pmx_uart1 = {
150 .name = "uart1", 150 .name = "uart1",
151 .modes = pmx_uart1_modes, 151 .modes = pmx_uart1_modes,
152 .mode_count = ARRAY_SIZE(pmx_uart1_modes), 152 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
153 .enb_on_reset = 1, 153 .enb_on_reset = 1,
154}; 154};
155 155
156struct pmx_dev_mode pmx_uart1_modem_modes[] = { 156static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
157 { 157 {
158 .ids = AUTO_EXP_MODE, 158 .ids = AUTO_EXP_MODE,
159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | 159 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
@@ -165,42 +165,42 @@ struct pmx_dev_mode pmx_uart1_modem_modes[] = {
165 }, 165 },
166}; 166};
167 167
168struct pmx_dev pmx_uart1_modem = { 168struct pmx_dev spear320_pmx_uart1_modem = {
169 .name = "uart1_modem", 169 .name = "uart1_modem",
170 .modes = pmx_uart1_modem_modes, 170 .modes = pmx_uart1_modem_modes,
171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), 171 .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
172 .enb_on_reset = 1, 172 .enb_on_reset = 1,
173}; 173};
174 174
175struct pmx_dev_mode pmx_uart2_modes[] = { 175static struct pmx_dev_mode pmx_uart2_modes[] = {
176 { 176 {
177 .ids = ALL_MODES, 177 .ids = ALL_MODES,
178 .mask = PMX_FIRDA_MASK, 178 .mask = PMX_FIRDA_MASK,
179 }, 179 },
180}; 180};
181 181
182struct pmx_dev pmx_uart2 = { 182struct pmx_dev spear320_pmx_uart2 = {
183 .name = "uart2", 183 .name = "uart2",
184 .modes = pmx_uart2_modes, 184 .modes = pmx_uart2_modes,
185 .mode_count = ARRAY_SIZE(pmx_uart2_modes), 185 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
186 .enb_on_reset = 1, 186 .enb_on_reset = 1,
187}; 187};
188 188
189struct pmx_dev_mode pmx_touchscreen_modes[] = { 189static struct pmx_dev_mode pmx_touchscreen_modes[] = {
190 { 190 {
191 .ids = AUTO_NET_SMII_MODE, 191 .ids = AUTO_NET_SMII_MODE,
192 .mask = PMX_SSP_CS_MASK, 192 .mask = PMX_SSP_CS_MASK,
193 }, 193 },
194}; 194};
195 195
196struct pmx_dev pmx_touchscreen = { 196struct pmx_dev spear320_pmx_touchscreen = {
197 .name = "touchscreen", 197 .name = "touchscreen",
198 .modes = pmx_touchscreen_modes, 198 .modes = pmx_touchscreen_modes,
199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), 199 .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
200 .enb_on_reset = 1, 200 .enb_on_reset = 1,
201}; 201};
202 202
203struct pmx_dev_mode pmx_can_modes[] = { 203static struct pmx_dev_mode pmx_can_modes[] = {
204 { 204 {
205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, 205 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | 206 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
@@ -208,28 +208,28 @@ struct pmx_dev_mode pmx_can_modes[] = {
208 }, 208 },
209}; 209};
210 210
211struct pmx_dev pmx_can = { 211struct pmx_dev spear320_pmx_can = {
212 .name = "can", 212 .name = "can",
213 .modes = pmx_can_modes, 213 .modes = pmx_can_modes,
214 .mode_count = ARRAY_SIZE(pmx_can_modes), 214 .mode_count = ARRAY_SIZE(pmx_can_modes),
215 .enb_on_reset = 1, 215 .enb_on_reset = 1,
216}; 216};
217 217
218struct pmx_dev_mode pmx_sdhci_led_modes[] = { 218static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
219 { 219 {
220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 220 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
221 .mask = PMX_SSP_CS_MASK, 221 .mask = PMX_SSP_CS_MASK,
222 }, 222 },
223}; 223};
224 224
225struct pmx_dev pmx_sdhci_led = { 225struct pmx_dev spear320_pmx_sdhci_led = {
226 .name = "sdhci_led", 226 .name = "sdhci_led",
227 .modes = pmx_sdhci_led_modes, 227 .modes = pmx_sdhci_led_modes,
228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), 228 .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
229 .enb_on_reset = 1, 229 .enb_on_reset = 1,
230}; 230};
231 231
232struct pmx_dev_mode pmx_pwm0_modes[] = { 232static struct pmx_dev_mode pmx_pwm0_modes[] = {
233 { 233 {
234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 234 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
235 .mask = PMX_UART0_MODEM_MASK, 235 .mask = PMX_UART0_MODEM_MASK,
@@ -239,14 +239,14 @@ struct pmx_dev_mode pmx_pwm0_modes[] = {
239 }, 239 },
240}; 240};
241 241
242struct pmx_dev pmx_pwm0 = { 242struct pmx_dev spear320_pmx_pwm0 = {
243 .name = "pwm0", 243 .name = "pwm0",
244 .modes = pmx_pwm0_modes, 244 .modes = pmx_pwm0_modes,
245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes), 245 .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
246 .enb_on_reset = 1, 246 .enb_on_reset = 1,
247}; 247};
248 248
249struct pmx_dev_mode pmx_pwm1_modes[] = { 249static struct pmx_dev_mode pmx_pwm1_modes[] = {
250 { 250 {
251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 251 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
252 .mask = PMX_UART0_MODEM_MASK, 252 .mask = PMX_UART0_MODEM_MASK,
@@ -256,14 +256,14 @@ struct pmx_dev_mode pmx_pwm1_modes[] = {
256 }, 256 },
257}; 257};
258 258
259struct pmx_dev pmx_pwm1 = { 259struct pmx_dev spear320_pmx_pwm1 = {
260 .name = "pwm1", 260 .name = "pwm1",
261 .modes = pmx_pwm1_modes, 261 .modes = pmx_pwm1_modes,
262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes), 262 .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
263 .enb_on_reset = 1, 263 .enb_on_reset = 1,
264}; 264};
265 265
266struct pmx_dev_mode pmx_pwm2_modes[] = { 266static struct pmx_dev_mode pmx_pwm2_modes[] = {
267 { 267 {
268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, 268 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
269 .mask = PMX_SSP_CS_MASK, 269 .mask = PMX_SSP_CS_MASK,
@@ -273,105 +273,105 @@ struct pmx_dev_mode pmx_pwm2_modes[] = {
273 }, 273 },
274}; 274};
275 275
276struct pmx_dev pmx_pwm2 = { 276struct pmx_dev spear320_pmx_pwm2 = {
277 .name = "pwm2", 277 .name = "pwm2",
278 .modes = pmx_pwm2_modes, 278 .modes = pmx_pwm2_modes,
279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes), 279 .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
280 .enb_on_reset = 1, 280 .enb_on_reset = 1,
281}; 281};
282 282
283struct pmx_dev_mode pmx_pwm3_modes[] = { 283static struct pmx_dev_mode pmx_pwm3_modes[] = {
284 { 284 {
285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 285 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
286 .mask = PMX_MII_MASK, 286 .mask = PMX_MII_MASK,
287 }, 287 },
288}; 288};
289 289
290struct pmx_dev pmx_pwm3 = { 290struct pmx_dev spear320_pmx_pwm3 = {
291 .name = "pwm3", 291 .name = "pwm3",
292 .modes = pmx_pwm3_modes, 292 .modes = pmx_pwm3_modes,
293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes), 293 .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
294 .enb_on_reset = 1, 294 .enb_on_reset = 1,
295}; 295};
296 296
297struct pmx_dev_mode pmx_ssp1_modes[] = { 297static struct pmx_dev_mode pmx_ssp1_modes[] = {
298 { 298 {
299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, 299 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
300 .mask = PMX_MII_MASK, 300 .mask = PMX_MII_MASK,
301 }, 301 },
302}; 302};
303 303
304struct pmx_dev pmx_ssp1 = { 304struct pmx_dev spear320_pmx_ssp1 = {
305 .name = "ssp1", 305 .name = "ssp1",
306 .modes = pmx_ssp1_modes, 306 .modes = pmx_ssp1_modes,
307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes), 307 .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
308 .enb_on_reset = 1, 308 .enb_on_reset = 1,
309}; 309};
310 310
311struct pmx_dev_mode pmx_ssp2_modes[] = { 311static struct pmx_dev_mode pmx_ssp2_modes[] = {
312 { 312 {
313 .ids = AUTO_NET_SMII_MODE, 313 .ids = AUTO_NET_SMII_MODE,
314 .mask = PMX_MII_MASK, 314 .mask = PMX_MII_MASK,
315 }, 315 },
316}; 316};
317 317
318struct pmx_dev pmx_ssp2 = { 318struct pmx_dev spear320_pmx_ssp2 = {
319 .name = "ssp2", 319 .name = "ssp2",
320 .modes = pmx_ssp2_modes, 320 .modes = pmx_ssp2_modes,
321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes), 321 .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
322 .enb_on_reset = 1, 322 .enb_on_reset = 1,
323}; 323};
324 324
325struct pmx_dev_mode pmx_mii1_modes[] = { 325static struct pmx_dev_mode pmx_mii1_modes[] = {
326 { 326 {
327 .ids = AUTO_NET_MII_MODE, 327 .ids = AUTO_NET_MII_MODE,
328 .mask = 0x0, 328 .mask = 0x0,
329 }, 329 },
330}; 330};
331 331
332struct pmx_dev pmx_mii1 = { 332struct pmx_dev spear320_pmx_mii1 = {
333 .name = "mii1", 333 .name = "mii1",
334 .modes = pmx_mii1_modes, 334 .modes = pmx_mii1_modes,
335 .mode_count = ARRAY_SIZE(pmx_mii1_modes), 335 .mode_count = ARRAY_SIZE(pmx_mii1_modes),
336 .enb_on_reset = 1, 336 .enb_on_reset = 1,
337}; 337};
338 338
339struct pmx_dev_mode pmx_smii0_modes[] = { 339static struct pmx_dev_mode pmx_smii0_modes[] = {
340 { 340 {
341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, 341 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
342 .mask = PMX_MII_MASK, 342 .mask = PMX_MII_MASK,
343 }, 343 },
344}; 344};
345 345
346struct pmx_dev pmx_smii0 = { 346struct pmx_dev spear320_pmx_smii0 = {
347 .name = "smii0", 347 .name = "smii0",
348 .modes = pmx_smii0_modes, 348 .modes = pmx_smii0_modes,
349 .mode_count = ARRAY_SIZE(pmx_smii0_modes), 349 .mode_count = ARRAY_SIZE(pmx_smii0_modes),
350 .enb_on_reset = 1, 350 .enb_on_reset = 1,
351}; 351};
352 352
353struct pmx_dev_mode pmx_smii1_modes[] = { 353static struct pmx_dev_mode pmx_smii1_modes[] = {
354 { 354 {
355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, 355 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
356 .mask = PMX_MII_MASK, 356 .mask = PMX_MII_MASK,
357 }, 357 },
358}; 358};
359 359
360struct pmx_dev pmx_smii1 = { 360struct pmx_dev spear320_pmx_smii1 = {
361 .name = "smii1", 361 .name = "smii1",
362 .modes = pmx_smii1_modes, 362 .modes = pmx_smii1_modes,
363 .mode_count = ARRAY_SIZE(pmx_smii1_modes), 363 .mode_count = ARRAY_SIZE(pmx_smii1_modes),
364 .enb_on_reset = 1, 364 .enb_on_reset = 1,
365}; 365};
366 366
367struct pmx_dev_mode pmx_i2c1_modes[] = { 367static struct pmx_dev_mode pmx_i2c1_modes[] = {
368 { 368 {
369 .ids = AUTO_EXP_MODE, 369 .ids = AUTO_EXP_MODE,
370 .mask = 0x0, 370 .mask = 0x0,
371 }, 371 },
372}; 372};
373 373
374struct pmx_dev pmx_i2c1 = { 374struct pmx_dev spear320_pmx_i2c1 = {
375 .name = "i2c1", 375 .name = "i2c1",
376 .modes = pmx_i2c1_modes, 376 .modes = pmx_i2c1_modes,
377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes), 377 .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
@@ -379,131 +379,131 @@ struct pmx_dev pmx_i2c1 = {
379}; 379};
380 380
381/* pmx driver structure */ 381/* pmx driver structure */
382struct pmx_driver pmx_driver = { 382static struct pmx_driver pmx_driver = {
383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, 383 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, 384 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
385}; 385};
386 386
387/* spear3xx shared irq */ 387/* spear3xx shared irq */
388struct shirq_dev_config shirq_ras1_config[] = { 388static struct shirq_dev_config shirq_ras1_config[] = {
389 { 389 {
390 .virq = VIRQ_EMI, 390 .virq = SPEAR320_VIRQ_EMI,
391 .status_mask = EMI_IRQ_MASK, 391 .status_mask = SPEAR320_EMI_IRQ_MASK,
392 .clear_mask = EMI_IRQ_MASK, 392 .clear_mask = SPEAR320_EMI_IRQ_MASK,
393 }, { 393 }, {
394 .virq = VIRQ_CLCD, 394 .virq = SPEAR320_VIRQ_CLCD,
395 .status_mask = CLCD_IRQ_MASK, 395 .status_mask = SPEAR320_CLCD_IRQ_MASK,
396 .clear_mask = CLCD_IRQ_MASK, 396 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
397 }, { 397 }, {
398 .virq = VIRQ_SPP, 398 .virq = SPEAR320_VIRQ_SPP,
399 .status_mask = SPP_IRQ_MASK, 399 .status_mask = SPEAR320_SPP_IRQ_MASK,
400 .clear_mask = SPP_IRQ_MASK, 400 .clear_mask = SPEAR320_SPP_IRQ_MASK,
401 }, 401 },
402}; 402};
403 403
404struct spear_shirq shirq_ras1 = { 404static struct spear_shirq shirq_ras1 = {
405 .irq = IRQ_GEN_RAS_1, 405 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
406 .dev_config = shirq_ras1_config, 406 .dev_config = shirq_ras1_config,
407 .dev_count = ARRAY_SIZE(shirq_ras1_config), 407 .dev_count = ARRAY_SIZE(shirq_ras1_config),
408 .regs = { 408 .regs = {
409 .enb_reg = -1, 409 .enb_reg = -1,
410 .status_reg = INT_STS_MASK_REG, 410 .status_reg = SPEAR320_INT_STS_MASK_REG,
411 .status_reg_mask = SHIRQ_RAS1_MASK, 411 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
412 .clear_reg = INT_CLR_MASK_REG, 412 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
413 .reset_to_clear = 1, 413 .reset_to_clear = 1,
414 }, 414 },
415}; 415};
416 416
417struct shirq_dev_config shirq_ras3_config[] = { 417static struct shirq_dev_config shirq_ras3_config[] = {
418 { 418 {
419 .virq = VIRQ_PLGPIO, 419 .virq = SPEAR320_VIRQ_PLGPIO,
420 .enb_mask = GPIO_IRQ_MASK, 420 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
421 .status_mask = GPIO_IRQ_MASK, 421 .status_mask = SPEAR320_GPIO_IRQ_MASK,
422 .clear_mask = GPIO_IRQ_MASK, 422 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
423 }, { 423 }, {
424 .virq = VIRQ_I2S_PLAY, 424 .virq = SPEAR320_VIRQ_I2S_PLAY,
425 .enb_mask = I2S_PLAY_IRQ_MASK, 425 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
426 .status_mask = I2S_PLAY_IRQ_MASK, 426 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
427 .clear_mask = I2S_PLAY_IRQ_MASK, 427 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
428 }, { 428 }, {
429 .virq = VIRQ_I2S_REC, 429 .virq = SPEAR320_VIRQ_I2S_REC,
430 .enb_mask = I2S_REC_IRQ_MASK, 430 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
431 .status_mask = I2S_REC_IRQ_MASK, 431 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
432 .clear_mask = I2S_REC_IRQ_MASK, 432 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
433 }, 433 },
434}; 434};
435 435
436struct spear_shirq shirq_ras3 = { 436static struct spear_shirq shirq_ras3 = {
437 .irq = IRQ_GEN_RAS_3, 437 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
438 .dev_config = shirq_ras3_config, 438 .dev_config = shirq_ras3_config,
439 .dev_count = ARRAY_SIZE(shirq_ras3_config), 439 .dev_count = ARRAY_SIZE(shirq_ras3_config),
440 .regs = { 440 .regs = {
441 .enb_reg = INT_ENB_MASK_REG, 441 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
442 .reset_to_enb = 1, 442 .reset_to_enb = 1,
443 .status_reg = INT_STS_MASK_REG, 443 .status_reg = SPEAR320_INT_STS_MASK_REG,
444 .status_reg_mask = SHIRQ_RAS3_MASK, 444 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
445 .clear_reg = INT_CLR_MASK_REG, 445 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
446 .reset_to_clear = 1, 446 .reset_to_clear = 1,
447 }, 447 },
448}; 448};
449 449
450struct shirq_dev_config shirq_intrcomm_ras_config[] = { 450static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
451 { 451 {
452 .virq = VIRQ_CANU, 452 .virq = SPEAR320_VIRQ_CANU,
453 .status_mask = CAN_U_IRQ_MASK, 453 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
454 .clear_mask = CAN_U_IRQ_MASK, 454 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
455 }, { 455 }, {
456 .virq = VIRQ_CANL, 456 .virq = SPEAR320_VIRQ_CANL,
457 .status_mask = CAN_L_IRQ_MASK, 457 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
458 .clear_mask = CAN_L_IRQ_MASK, 458 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
459 }, { 459 }, {
460 .virq = VIRQ_UART1, 460 .virq = SPEAR320_VIRQ_UART1,
461 .status_mask = UART1_IRQ_MASK, 461 .status_mask = SPEAR320_UART1_IRQ_MASK,
462 .clear_mask = UART1_IRQ_MASK, 462 .clear_mask = SPEAR320_UART1_IRQ_MASK,
463 }, { 463 }, {
464 .virq = VIRQ_UART2, 464 .virq = SPEAR320_VIRQ_UART2,
465 .status_mask = UART2_IRQ_MASK, 465 .status_mask = SPEAR320_UART2_IRQ_MASK,
466 .clear_mask = UART2_IRQ_MASK, 466 .clear_mask = SPEAR320_UART2_IRQ_MASK,
467 }, { 467 }, {
468 .virq = VIRQ_SSP1, 468 .virq = SPEAR320_VIRQ_SSP1,
469 .status_mask = SSP1_IRQ_MASK, 469 .status_mask = SPEAR320_SSP1_IRQ_MASK,
470 .clear_mask = SSP1_IRQ_MASK, 470 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
471 }, { 471 }, {
472 .virq = VIRQ_SSP2, 472 .virq = SPEAR320_VIRQ_SSP2,
473 .status_mask = SSP2_IRQ_MASK, 473 .status_mask = SPEAR320_SSP2_IRQ_MASK,
474 .clear_mask = SSP2_IRQ_MASK, 474 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
475 }, { 475 }, {
476 .virq = VIRQ_SMII0, 476 .virq = SPEAR320_VIRQ_SMII0,
477 .status_mask = SMII0_IRQ_MASK, 477 .status_mask = SPEAR320_SMII0_IRQ_MASK,
478 .clear_mask = SMII0_IRQ_MASK, 478 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
479 }, { 479 }, {
480 .virq = VIRQ_MII1_SMII1, 480 .virq = SPEAR320_VIRQ_MII1_SMII1,
481 .status_mask = MII1_SMII1_IRQ_MASK, 481 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
482 .clear_mask = MII1_SMII1_IRQ_MASK, 482 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
483 }, { 483 }, {
484 .virq = VIRQ_WAKEUP_SMII0, 484 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
485 .status_mask = WAKEUP_SMII0_IRQ_MASK, 485 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
486 .clear_mask = WAKEUP_SMII0_IRQ_MASK, 486 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
487 }, { 487 }, {
488 .virq = VIRQ_WAKEUP_MII1_SMII1, 488 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
489 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 489 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
490 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK, 490 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
491 }, { 491 }, {
492 .virq = VIRQ_I2C, 492 .virq = SPEAR320_VIRQ_I2C1,
493 .status_mask = I2C1_IRQ_MASK, 493 .status_mask = SPEAR320_I2C1_IRQ_MASK,
494 .clear_mask = I2C1_IRQ_MASK, 494 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
495 }, 495 },
496}; 496};
497 497
498struct spear_shirq shirq_intrcomm_ras = { 498static struct spear_shirq shirq_intrcomm_ras = {
499 .irq = IRQ_INTRCOMM_RAS_ARM, 499 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
500 .dev_config = shirq_intrcomm_ras_config, 500 .dev_config = shirq_intrcomm_ras_config,
501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), 501 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
502 .regs = { 502 .regs = {
503 .enb_reg = -1, 503 .enb_reg = -1,
504 .status_reg = INT_STS_MASK_REG, 504 .status_reg = SPEAR320_INT_STS_MASK_REG,
505 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK, 505 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
506 .clear_reg = INT_CLR_MASK_REG, 506 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
507 .reset_to_clear = 1, 507 .reset_to_clear = 1,
508 }, 508 },
509}; 509};
@@ -511,7 +511,8 @@ struct spear_shirq shirq_intrcomm_ras = {
511/* Add spear320 specific devices here */ 511/* Add spear320 specific devices here */
512 512
513/* spear320 routines */ 513/* spear320 routines */
514void __init spear320_init(void) 514void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
515 u8 pmx_dev_count)
515{ 516{
516 void __iomem *base; 517 void __iomem *base;
517 int ret = 0; 518 int ret = 0;
@@ -543,6 +544,10 @@ void __init spear320_init(void)
543 544
544 /* pmx initialization */ 545 /* pmx initialization */
545 pmx_driver.base = base; 546 pmx_driver.base = base;
547 pmx_driver.mode = pmx_mode;
548 pmx_driver.devs = pmx_devs;
549 pmx_driver.devs_count = pmx_dev_count;
550
546 ret = pmx_register(&pmx_driver); 551 ret = pmx_register(&pmx_driver);
547 if (ret) 552 if (ret)
548 printk(KERN_ERR "padmux: registeration failed. err no: %d\n", 553 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",