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-rw-r--r--arch/arm/mach-spear3xx/spear300.c613
1 files changed, 229 insertions, 384 deletions
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..2db0bd14e481 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,373 +3,24 @@
3 * 3 *
4 * SPEAr300 machine source file 4 * SPEAr300 machine source file
5 * 5 *
6 * Copyright (C) 2009 ST Microelectronics 6 * Copyright (C) 2009-2012 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com> 7 * Viresh Kumar <viresh.kumar@st.com>
8 * 8 *
9 * This file is licensed under the terms of the GNU General Public 9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any 10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/types.h> 14#define pr_fmt(fmt) "SPEAr300: " fmt
15#include <linux/amba/pl061.h> 15
16#include <linux/ptrace.h> 16#include <linux/amba/pl08x.h>
17#include <asm/irq.h> 17#include <linux/of_platform.h>
18#include <asm/hardware/vic.h>
19#include <asm/mach/arch.h>
18#include <plat/shirq.h> 20#include <plat/shirq.h>
19#include <mach/generic.h> 21#include <mach/generic.h>
20#include <mach/hardware.h> 22#include <mach/hardware.h>
21 23
22/* pad multiplexing support */
23/* muxing registers */
24#define PAD_MUX_CONFIG_REG 0x00
25#define MODE_CONFIG_REG 0x04
26
27/* modes */
28#define NAND_MODE (1 << 0)
29#define NOR_MODE (1 << 1)
30#define PHOTO_FRAME_MODE (1 << 2)
31#define LEND_IP_PHONE_MODE (1 << 3)
32#define HEND_IP_PHONE_MODE (1 << 4)
33#define LEND_WIFI_PHONE_MODE (1 << 5)
34#define HEND_WIFI_PHONE_MODE (1 << 6)
35#define ATA_PABX_WI2S_MODE (1 << 7)
36#define ATA_PABX_I2S_MODE (1 << 8)
37#define CAML_LCDW_MODE (1 << 9)
38#define CAMU_LCD_MODE (1 << 10)
39#define CAMU_WLCD_MODE (1 << 11)
40#define CAML_LCD_MODE (1 << 12)
41#define ALL_MODES 0x1FFF
42
43struct pmx_mode spear300_nand_mode = {
44 .id = NAND_MODE,
45 .name = "nand mode",
46 .mask = 0x00,
47};
48
49struct pmx_mode spear300_nor_mode = {
50 .id = NOR_MODE,
51 .name = "nor mode",
52 .mask = 0x01,
53};
54
55struct pmx_mode spear300_photo_frame_mode = {
56 .id = PHOTO_FRAME_MODE,
57 .name = "photo frame mode",
58 .mask = 0x02,
59};
60
61struct pmx_mode spear300_lend_ip_phone_mode = {
62 .id = LEND_IP_PHONE_MODE,
63 .name = "lend ip phone mode",
64 .mask = 0x03,
65};
66
67struct pmx_mode spear300_hend_ip_phone_mode = {
68 .id = HEND_IP_PHONE_MODE,
69 .name = "hend ip phone mode",
70 .mask = 0x04,
71};
72
73struct pmx_mode spear300_lend_wifi_phone_mode = {
74 .id = LEND_WIFI_PHONE_MODE,
75 .name = "lend wifi phone mode",
76 .mask = 0x05,
77};
78
79struct pmx_mode spear300_hend_wifi_phone_mode = {
80 .id = HEND_WIFI_PHONE_MODE,
81 .name = "hend wifi phone mode",
82 .mask = 0x06,
83};
84
85struct pmx_mode spear300_ata_pabx_wi2s_mode = {
86 .id = ATA_PABX_WI2S_MODE,
87 .name = "ata pabx wi2s mode",
88 .mask = 0x07,
89};
90
91struct pmx_mode spear300_ata_pabx_i2s_mode = {
92 .id = ATA_PABX_I2S_MODE,
93 .name = "ata pabx i2s mode",
94 .mask = 0x08,
95};
96
97struct pmx_mode spear300_caml_lcdw_mode = {
98 .id = CAML_LCDW_MODE,
99 .name = "caml lcdw mode",
100 .mask = 0x0C,
101};
102
103struct pmx_mode spear300_camu_lcd_mode = {
104 .id = CAMU_LCD_MODE,
105 .name = "camu lcd mode",
106 .mask = 0x0D,
107};
108
109struct pmx_mode spear300_camu_wlcd_mode = {
110 .id = CAMU_WLCD_MODE,
111 .name = "camu wlcd mode",
112 .mask = 0x0E,
113};
114
115struct pmx_mode spear300_caml_lcd_mode = {
116 .id = CAML_LCD_MODE,
117 .name = "caml lcd mode",
118 .mask = 0x0F,
119};
120
121/* devices */
122static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
123 {
124 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
125 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
126 .mask = PMX_FIRDA_MASK,
127 },
128};
129
130struct pmx_dev spear300_pmx_fsmc_2_chips = {
131 .name = "fsmc_2_chips",
132 .modes = pmx_fsmc_2_chips_modes,
133 .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
134 .enb_on_reset = 1,
135};
136
137static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
138 {
139 .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
140 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
141 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
142 },
143};
144
145struct pmx_dev spear300_pmx_fsmc_4_chips = {
146 .name = "fsmc_4_chips",
147 .modes = pmx_fsmc_4_chips_modes,
148 .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
149 .enb_on_reset = 1,
150};
151
152static struct pmx_dev_mode pmx_keyboard_modes[] = {
153 {
154 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
155 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
156 CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
157 CAML_LCD_MODE,
158 .mask = 0x0,
159 },
160};
161
162struct pmx_dev spear300_pmx_keyboard = {
163 .name = "keyboard",
164 .modes = pmx_keyboard_modes,
165 .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
166 .enb_on_reset = 1,
167};
168
169static struct pmx_dev_mode pmx_clcd_modes[] = {
170 {
171 .ids = PHOTO_FRAME_MODE,
172 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
173 }, {
174 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
175 CAMU_LCD_MODE | CAML_LCD_MODE,
176 .mask = PMX_TIMER_3_4_MASK,
177 },
178};
179
180struct pmx_dev spear300_pmx_clcd = {
181 .name = "clcd",
182 .modes = pmx_clcd_modes,
183 .mode_count = ARRAY_SIZE(pmx_clcd_modes),
184 .enb_on_reset = 1,
185};
186
187static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
188 {
189 .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
190 .mask = PMX_MII_MASK,
191 }, {
192 .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
193 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
194 }, {
195 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
196 .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
197 }, {
198 .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
199 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
200 }, {
201 .ids = ATA_PABX_WI2S_MODE,
202 .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
203 | PMX_UART0_MODEM_MASK,
204 },
205};
206
207struct pmx_dev spear300_pmx_telecom_gpio = {
208 .name = "telecom_gpio",
209 .modes = pmx_telecom_gpio_modes,
210 .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
211 .enb_on_reset = 1,
212};
213
214static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
215 {
216 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
217 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
218 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
219 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
220 | CAMU_WLCD_MODE | CAML_LCD_MODE,
221 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
222 },
223};
224
225struct pmx_dev spear300_pmx_telecom_tdm = {
226 .name = "telecom_tdm",
227 .modes = pmx_telecom_tdm_modes,
228 .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
229 .enb_on_reset = 1,
230};
231
232static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
233 {
234 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
235 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
236 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
237 CAML_LCDW_MODE | CAML_LCD_MODE,
238 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
239 },
240};
241
242struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
243 .name = "telecom_spi_cs_i2c_clk",
244 .modes = pmx_telecom_spi_cs_i2c_clk_modes,
245 .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
246 .enb_on_reset = 1,
247};
248
249static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
250 {
251 .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
252 .mask = PMX_MII_MASK,
253 }, {
254 .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
255 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
256 },
257};
258
259struct pmx_dev spear300_pmx_telecom_camera = {
260 .name = "telecom_camera",
261 .modes = pmx_telecom_camera_modes,
262 .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
263 .enb_on_reset = 1,
264};
265
266static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
267 {
268 .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
269 | CAMU_WLCD_MODE | CAML_LCD_MODE,
270 .mask = PMX_TIMER_1_2_MASK,
271 },
272};
273
274struct pmx_dev spear300_pmx_telecom_dac = {
275 .name = "telecom_dac",
276 .modes = pmx_telecom_dac_modes,
277 .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
278 .enb_on_reset = 1,
279};
280
281static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
282 {
283 .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
284 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
285 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
286 | CAMU_WLCD_MODE | CAML_LCD_MODE,
287 .mask = PMX_UART0_MODEM_MASK,
288 },
289};
290
291struct pmx_dev spear300_pmx_telecom_i2s = {
292 .name = "telecom_i2s",
293 .modes = pmx_telecom_i2s_modes,
294 .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
295 .enb_on_reset = 1,
296};
297
298static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
299 {
300 .ids = NAND_MODE | NOR_MODE,
301 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
302 PMX_TIMER_3_4_MASK,
303 },
304};
305
306struct pmx_dev spear300_pmx_telecom_boot_pins = {
307 .name = "telecom_boot_pins",
308 .modes = pmx_telecom_boot_pins_modes,
309 .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
310 .enb_on_reset = 1,
311};
312
313static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
314 {
315 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
316 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
317 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
318 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
319 ATA_PABX_I2S_MODE,
320 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
321 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
322 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
323 },
324};
325
326struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
327 .name = "telecom_sdhci_4bit",
328 .modes = pmx_telecom_sdhci_4bit_modes,
329 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
330 .enb_on_reset = 1,
331};
332
333static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
334 {
335 .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
336 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
337 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
338 CAMU_WLCD_MODE | CAML_LCD_MODE,
339 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
340 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
341 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
342 },
343};
344
345struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
346 .name = "telecom_sdhci_8bit",
347 .modes = pmx_telecom_sdhci_8bit_modes,
348 .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
349 .enb_on_reset = 1,
350};
351
352static struct pmx_dev_mode pmx_gpio1_modes[] = {
353 {
354 .ids = PHOTO_FRAME_MODE,
355 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
356 PMX_TIMER_3_4_MASK,
357 },
358};
359
360struct pmx_dev spear300_pmx_gpio1 = {
361 .name = "arm gpio1",
362 .modes = pmx_gpio1_modes,
363 .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
364 .enb_on_reset = 1,
365};
366
367/* pmx driver structure */
368static struct pmx_driver pmx_driver = {
369 .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
370 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
371};
372
373/* spear3xx shared irq */ 24/* spear3xx shared irq */
374static struct shirq_dev_config shirq_ras1_config[] = { 25static struct shirq_dev_config shirq_ras1_config[] = {
375 { 26 {
@@ -423,45 +74,239 @@ static struct spear_shirq shirq_ras1 = {
423 }, 74 },
424}; 75};
425 76
426/* Add spear300 specific devices here */ 77/* DMAC platform data's slave info */
427/* arm gpio1 device registration */ 78struct pl08x_channel_data spear300_dma_info[] = {
428static struct pl061_platform_data gpio1_plat_data = { 79 {
429 .gpio_base = 8, 80 .bus_id = "uart0_rx",
430 .irq_base = SPEAR300_GPIO1_INT_BASE, 81 .min_signal = 2,
82 .max_signal = 2,
83 .muxval = 0,
84 .cctl = 0,
85 .periph_buses = PL08X_AHB1,
86 }, {
87 .bus_id = "uart0_tx",
88 .min_signal = 3,
89 .max_signal = 3,
90 .muxval = 0,
91 .cctl = 0,
92 .periph_buses = PL08X_AHB1,
93 }, {
94 .bus_id = "ssp0_rx",
95 .min_signal = 8,
96 .max_signal = 8,
97 .muxval = 0,
98 .cctl = 0,
99 .periph_buses = PL08X_AHB1,
100 }, {
101 .bus_id = "ssp0_tx",
102 .min_signal = 9,
103 .max_signal = 9,
104 .muxval = 0,
105 .cctl = 0,
106 .periph_buses = PL08X_AHB1,
107 }, {
108 .bus_id = "i2c_rx",
109 .min_signal = 10,
110 .max_signal = 10,
111 .muxval = 0,
112 .cctl = 0,
113 .periph_buses = PL08X_AHB1,
114 }, {
115 .bus_id = "i2c_tx",
116 .min_signal = 11,
117 .max_signal = 11,
118 .muxval = 0,
119 .cctl = 0,
120 .periph_buses = PL08X_AHB1,
121 }, {
122 .bus_id = "irda",
123 .min_signal = 12,
124 .max_signal = 12,
125 .muxval = 0,
126 .cctl = 0,
127 .periph_buses = PL08X_AHB1,
128 }, {
129 .bus_id = "adc",
130 .min_signal = 13,
131 .max_signal = 13,
132 .muxval = 0,
133 .cctl = 0,
134 .periph_buses = PL08X_AHB1,
135 }, {
136 .bus_id = "to_jpeg",
137 .min_signal = 14,
138 .max_signal = 14,
139 .muxval = 0,
140 .cctl = 0,
141 .periph_buses = PL08X_AHB1,
142 }, {
143 .bus_id = "from_jpeg",
144 .min_signal = 15,
145 .max_signal = 15,
146 .muxval = 0,
147 .cctl = 0,
148 .periph_buses = PL08X_AHB1,
149 }, {
150 .bus_id = "ras0_rx",
151 .min_signal = 0,
152 .max_signal = 0,
153 .muxval = 1,
154 .cctl = 0,
155 .periph_buses = PL08X_AHB1,
156 }, {
157 .bus_id = "ras0_tx",
158 .min_signal = 1,
159 .max_signal = 1,
160 .muxval = 1,
161 .cctl = 0,
162 .periph_buses = PL08X_AHB1,
163 }, {
164 .bus_id = "ras1_rx",
165 .min_signal = 2,
166 .max_signal = 2,
167 .muxval = 1,
168 .cctl = 0,
169 .periph_buses = PL08X_AHB1,
170 }, {
171 .bus_id = "ras1_tx",
172 .min_signal = 3,
173 .max_signal = 3,
174 .muxval = 1,
175 .cctl = 0,
176 .periph_buses = PL08X_AHB1,
177 }, {
178 .bus_id = "ras2_rx",
179 .min_signal = 4,
180 .max_signal = 4,
181 .muxval = 1,
182 .cctl = 0,
183 .periph_buses = PL08X_AHB1,
184 }, {
185 .bus_id = "ras2_tx",
186 .min_signal = 5,
187 .max_signal = 5,
188 .muxval = 1,
189 .cctl = 0,
190 .periph_buses = PL08X_AHB1,
191 }, {
192 .bus_id = "ras3_rx",
193 .min_signal = 6,
194 .max_signal = 6,
195 .muxval = 1,
196 .cctl = 0,
197 .periph_buses = PL08X_AHB1,
198 }, {
199 .bus_id = "ras3_tx",
200 .min_signal = 7,
201 .max_signal = 7,
202 .muxval = 1,
203 .cctl = 0,
204 .periph_buses = PL08X_AHB1,
205 }, {
206 .bus_id = "ras4_rx",
207 .min_signal = 8,
208 .max_signal = 8,
209 .muxval = 1,
210 .cctl = 0,
211 .periph_buses = PL08X_AHB1,
212 }, {
213 .bus_id = "ras4_tx",
214 .min_signal = 9,
215 .max_signal = 9,
216 .muxval = 1,
217 .cctl = 0,
218 .periph_buses = PL08X_AHB1,
219 }, {
220 .bus_id = "ras5_rx",
221 .min_signal = 10,
222 .max_signal = 10,
223 .muxval = 1,
224 .cctl = 0,
225 .periph_buses = PL08X_AHB1,
226 }, {
227 .bus_id = "ras5_tx",
228 .min_signal = 11,
229 .max_signal = 11,
230 .muxval = 1,
231 .cctl = 0,
232 .periph_buses = PL08X_AHB1,
233 }, {
234 .bus_id = "ras6_rx",
235 .min_signal = 12,
236 .max_signal = 12,
237 .muxval = 1,
238 .cctl = 0,
239 .periph_buses = PL08X_AHB1,
240 }, {
241 .bus_id = "ras6_tx",
242 .min_signal = 13,
243 .max_signal = 13,
244 .muxval = 1,
245 .cctl = 0,
246 .periph_buses = PL08X_AHB1,
247 }, {
248 .bus_id = "ras7_rx",
249 .min_signal = 14,
250 .max_signal = 14,
251 .muxval = 1,
252 .cctl = 0,
253 .periph_buses = PL08X_AHB1,
254 }, {
255 .bus_id = "ras7_tx",
256 .min_signal = 15,
257 .max_signal = 15,
258 .muxval = 1,
259 .cctl = 0,
260 .periph_buses = PL08X_AHB1,
261 },
431}; 262};
432 263
433AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE, 264/* Add SPEAr300 auxdata to pass platform data */
434 {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data); 265static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
266 OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
267 &pl022_plat_data),
268 OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
269 &pl080_plat_data),
270 {}
271};
435 272
436/* spear300 routines */ 273static void __init spear300_dt_init(void)
437void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
438 u8 pmx_dev_count)
439{ 274{
440 int ret = 0; 275 int ret;
276
277 pl080_plat_data.slave_channels = spear300_dma_info;
278 pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
441 279
442 /* call spear3xx family common init function */ 280 of_platform_populate(NULL, of_default_bus_match_table,
443 spear3xx_init(); 281 spear300_auxdata_lookup, NULL);
444 282
445 /* shared irq registration */ 283 /* shared irq registration */
446 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K); 284 shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
447 if (shirq_ras1.regs.base) { 285 if (shirq_ras1.regs.base) {
448 ret = spear_shirq_register(&shirq_ras1); 286 ret = spear_shirq_register(&shirq_ras1);
449 if (ret) 287 if (ret)
450 printk(KERN_ERR "Error registering Shared IRQ\n"); 288 pr_err("Error registering Shared IRQ\n");
451 } 289 }
290}
452 291
453 /* pmx initialization */ 292static const char * const spear300_dt_board_compat[] = {
454 pmx_driver.mode = pmx_mode; 293 "st,spear300",
455 pmx_driver.devs = pmx_devs; 294 "st,spear300-evb",
456 pmx_driver.devs_count = pmx_dev_count; 295 NULL,
296};
457 297
458 pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); 298static void __init spear300_map_io(void)
459 if (pmx_driver.base) { 299{
460 ret = pmx_register(&pmx_driver); 300 spear3xx_map_io();
461 if (ret) 301 spear300_clk_init();
462 printk(KERN_ERR "padmux: registration failed. err no"
463 ": %d\n", ret);
464 /* Free Mapping, device selection already done */
465 iounmap(pmx_driver.base);
466 }
467} 302}
303
304DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
305 .map_io = spear300_map_io,
306 .init_irq = spear3xx_dt_init_irq,
307 .handle_irq = vic_handle_irq,
308 .timer = &spear3xx_timer,
309 .init_machine = spear300_dt_init,
310 .restart = spear_restart,
311 .dt_compat = spear300_dt_board_compat,
312MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 04:26:18 -0500